CN111463286A - N-tube IO assembly and manufacturing method thereof - Google Patents

N-tube IO assembly and manufacturing method thereof Download PDF

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CN111463286A
CN111463286A CN202010277151.7A CN202010277151A CN111463286A CN 111463286 A CN111463286 A CN 111463286A CN 202010277151 A CN202010277151 A CN 202010277151A CN 111463286 A CN111463286 A CN 111463286A
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implantation
lightly doped
halo
doped drain
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CN111463286B (en
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白文琦
王世铭
黄志森
胡展源
杨会山
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

The invention discloses an N-tube IO assembly.A lightly doped drain region has a distributed structure for reducing a drain end electric field, doped impurities of the lightly doped drain region are phosphorus, ion implantation of the lightly doped drain region is angled lightly doped drain implantation, and the distributed structure of the lightly doped drain region is adjusted by combining the diffusivity of the phosphorus, the implantation angle of the lightly doped drain implantation and the implantation energy and is adjusted to ensure that the service life of a hot carrier meets a required value; the halo implantation region comprises a boron and carbon doped structure doped by a common halo ion implantation process; the carbon impurity distribution structure of the halo injection region is used as a barrier structure for phosphorus impurity diffusion of the lightly doped drain region. The invention also discloses a manufacturing method of the N-tube IO assembly. The invention can prolong the service life of hot carriers and reduce the effect of the hot carriers.

Description

N-tube IO assembly and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an N-transistor (NFET) input/output (IO) component. The invention also relates to a manufacturing method of the N-tube IO assembly.
Background
When the device works, carriers move from the source end to the drain end, kinetic energy is obtained in a high electric field area of the drain end, and along with energy accumulation, energy higher than lattice heat energy is called hot carriers. When the hot carrier energy exceeds a certain threshold, impact ionization (impact ionization) is generated, and more hole-electron pairs are generated by the impact ionization hole-electron pairs, so that the avalanche effect is caused. Hot carriers with higher energy can be injected into the gate oxide layer or damage the interface of the gate oxide layer/silicon substrate, thereby causing the electrical property degradation of the device and the abnormal operation of the device. With the evolution of process nodes, in devices below the 65nm technology node, the drain field generating is very dense (electric field generating), which causes hot carrier effect (HCI) to become a problem to be solved urgently, especially for NFET IO devices, because the operating voltage is high, the electric field at the drain is very strong, and the carriers are electrons, which causes the hot carrier effect to be more obvious, and the promotion of HCI of NFET IO becomes a technical problem acknowledged in the industry.
FIG. 1 is a schematic structural diagram of a conventional N-tube IO module; the conventional N-transistor IO device includes a gate structure, a sidewall 107, a lightly doped drain region 105, a source region 108, a drain region 109, and a halo implant region 106.
The gate structure is formed on a surface of a semiconductor substrate 101. A field oxide 102 is also formed on the semiconductor substrate 101, and the field oxide 102 isolates an active region.
Generally, a P-type well is formed on the semiconductor substrate 101, a formation region of the N-tube IO assembly is located in a formation region of the P-type well, the gate structure is formed on a surface of the P-type well, an N-type doped channel region is formed by the P-type well located between the lightly doped drain regions 105 and between the source region 108 and the drain region 109 and covered by the gate structure, and a surface of the channel region covered by the gate structure is used for forming a channel. The P-type wells are formed in the semiconductor substrate 101 in the regions shown in fig. 1, and the positions of the regions of the P-type wells are directly referred to the regions of the semiconductor substrate 110, and the P-type wells are not separately marked.
The gate structure comprises a gate dielectric layer 103 and a gate conductive material layer 104 which are sequentially overlapped. Typically, the gate dielectric layer 103 is silicon dioxide or a high dielectric constant material; the gate conductive material layer 104 is a polysilicon gate or a metal gate.
The lightly doped drain region 105 is formed in the semiconductor substrate 101 at two sides of the gate structure in a self-aligned manner. For the conventional N-transistor IO device with a technology node of 65nm or less, it is desirable to obtain the lightly doped drain 105 with a shallower junction depth, so the doping impurity of the lightly doped drain 105 is usually arsenic (As) instead of phosphorus (P) with a larger diffusion coefficient.
The spacers 107 are formed on both sides of the gate structure in a self-aligned manner.
The N + doped source region 108 and the drain region 109 are formed in the semiconductor substrate 101 on both sides of the gate structure, and the source region 108 and the drain region 109 are self-aligned with the corresponding side walls 107.
The halo implant region 106 is located in the semiconductor substrate 101 at the bottom of the lightly doped drain region 105 and the halo implant region 106 wraps the lightly doped drain region 105.
As shown in fig. 2, which is a flow chart of a manufacturing method of a conventional N-type FET, fig. 2 only shows a flow corresponding to an ion implantation process, and it can be seen that the main steps of the conventional method are:
a well implant corresponding to step 201 is performed to form a P-well corresponding to the N-transistor IO device before the gate structure is formed.
A halo ion implant of boron corresponding to step 203 is then performed to form the halo implant region 106.
A lightly doped drain implant of As is performed to form lightly doped drain region 105 in step 204.
Spacers 107 are then formed on the sides of the gate structure.
A corresponding source drain implant is then performed at step 206 to form source region 108 and drain region 109.
As shown in fig. 1, as the size is reduced, the junction depth and the width of the lightly doped drain 105 of the conventional N-transistor IO device become smaller, but the operating voltage of the IO device is not reduced in the same equal proportion, and the operating voltage of the IO device is still higher, so that a very dense electric field is formed near a PN junction formed by the lightly doped drain 105 with a smaller junction depth and a channel region by the high operating voltage applied from the drain 109, so that the peak value of the electric field intensity is larger, and finally, carriers in the channel enter a larger electric field intensity region to be accelerated and finally generate a hot carrier effect, so that the performance of the device is degraded or damaged.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an N-tube IO assembly, which can prolong the service life of hot carriers and reduce the hot carrier effect. Therefore, the invention also provides a manufacturing method of the N-tube IO assembly.
In order to solve the technical problem, the N-tube IO assembly provided by the invention comprises a gate structure, a side wall, a channel region, a lightly doped drain region, a source region, a drain region and a halo implantation region.
The gate structure is formed on a surface of a semiconductor substrate.
The lightly doped drain region is formed in the semiconductor substrate on two sides of the grid structure in a self-alignment mode.
The side walls are formed on two side surfaces of the grid structure in a self-aligning mode.
And the N + doped source region and the drain region are formed in the semiconductor substrate at two sides of the grid structure, and the source region and the drain region are self-aligned with the corresponding side surfaces of the side walls.
The lightly doped drain region is provided with a distributed structure for reducing a drain end electric field, the doping impurity of the lightly doped drain region is phosphorus, the ion implantation of the lightly doped drain region is angled lightly doped drain implantation, the distributed structure of the lightly doped drain region is adjusted by combining the diffusivity of the phosphorus, the implantation angle of the lightly doped drain implantation and the implantation energy, and the distributed structure of the lightly doped drain region is adjusted to enable the service life of a hot carrier to meet a required value.
The halo implantation region wraps the lightly doped drain region, and the halo implantation region comprises a boron and carbon doped structure doped by adopting a common halo ion implantation process.
The carbon impurity distribution structure of the halo implantation region is used as a barrier structure for phosphorus impurity diffusion of the lightly doped drain region and is used as an adjusting structure for improving a short channel effect caused by phosphorus diffusion into the P-type doped channel region, and the carbon impurity distribution structure of the halo implantation region is adjusted through the implantation angle and implantation energy of the halo ion implantation.
The boron impurity distribution structure of the halo implantation region is used as an adjusting structure for improving a short channel effect and reducing a source-drain punch-through effect, and the boron impurity distribution structure of the halo implantation region is adjusted through the implantation angle and implantation energy of halo ion implantation.
In a further improvement, a P-type well is formed on the semiconductor substrate, a forming region of the N-tube IO assembly is located in the forming region of the P-type well, and the gate structure is formed on the surface of the P-type well; the channel region is composed of the P-type trap which is positioned between the lightly doped drain regions and between the source region and the drain region and covered by the grid structure, and the surface of the channel region covered by the grid structure is used for forming a channel.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the gate structure comprises a gate dielectric layer and a gate conductive material layer which are sequentially stacked.
The further improvement is that the gate dielectric layer is silicon dioxide or a high dielectric constant material.
In a further improvement, the gate conductive material layer is a polysilicon gate or a metal gate.
The further improvement is that the halo ion implantation is large-angle ion implantation taking the side surface of the gate structure as a self-aligned boundary, and the implantation angle of the halo ion implantation is 10-50 degrees.
In a further improvement, the surfaces of both sides of the gate structure have surfaces subjected to pre-amorphization ion implantation treatment.
The halo ion implantation is performed before or after the ion implantation of the lightly doped drain region, and the pre-amorphization ion implantation is performed before the common ion implantation of the halo implantation region and the ion implantation of the lightly doped drain region.
The further improvement is that the technical node of the N-tube IO component is less than 65 nm.
In order to solve the technical problem, the manufacturing method of the N-tube IO assembly provided by the invention comprises the following steps:
step one, forming a grid structure of the N-tube IO assembly on the surface of the semiconductor substrate.
And secondly, injecting a self-aligned lightly doped drain into the semiconductor substrate at two sides of the grid structure to form a lightly doped drain region.
The lightly doped drain region is provided with a distributed structure for reducing a drain end electric field, the doping impurities of the lightly doped drain region are phosphorus, the lightly doped drain implantation is angled ion implantation, the distributed structure of the lightly doped drain region is adjusted by combining the diffusivity of the phosphorus, the implantation angle of the lightly doped drain implantation and the implantation energy, and the distributed structure of the lightly doped drain region is adjusted to enable the service life of a hot carrier to meet a required value.
And step three, carrying out self-aligned halo ion implantation to form halo implantation regions in the semiconductor substrate at two sides of the grid structure, wherein the halo implantation regions wrap the lightly doped drain regions.
The halo implant region includes a boron and carbon doped structure that is doped using a common halo ion implantation process.
The carbon impurity distribution structure of the halo implantation region is used as a barrier structure for phosphorus impurity diffusion of the lightly doped drain region and is used as an adjusting structure for improving a short channel effect caused by phosphorus diffusion into the P-type doped channel region, and the carbon impurity distribution structure of the halo implantation region is adjusted through the implantation angle and implantation energy of the halo ion implantation.
The boron impurity distribution structure of the halo implantation region is used as an adjusting structure for improving a short channel effect and reducing a source-drain punch-through effect, and the boron impurity distribution structure of the halo implantation region is adjusted through the implantation angle and implantation energy of halo ion implantation.
And step four, forming a side wall on the side surface of the grid structure.
And fifthly, injecting N + doped source and drain into the semiconductor substrate on two sides of the grid structure by taking the side face of the side wall as a self-alignment condition to form a source region and a drain region.
In a further improvement, a P-type well is formed on the semiconductor substrate, a forming region of the N-tube IO assembly is located in the forming region of the P-type well, and the gate structure is formed on the surface of the P-type well; the channel region is composed of the P-type trap which is positioned between the lightly doped drain regions and between the source region and the drain region and covered by the grid structure, and the surface of the channel region covered by the grid structure is used for forming a channel.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
The further improvement is that the grid structure comprises a grid dielectric layer and a polysilicon grid which are sequentially overlapped.
The further improvement is that the gate dielectric layer is silicon dioxide or a high dielectric constant material.
The further improvement is that the gate structure in the step one is a final gate structure; or, the gate structure in the first step is a dummy gate structure, and in a subsequent process, a gate replacement process is further performed to replace a polysilicon gate of the dummy gate structure with a metal gate and form a final gate structure.
The further improvement is that the halo ion implantation is large-angle ion implantation, and the implantation angle is 10-50 degrees.
The further improvement is that the sequence of the step two and the step three can be exchanged. After the first step is completed and before the second step and the third step are carried out, the method further comprises the following steps:
and performing pre-amorphization ion implantation to realize pre-amorphization ion implantation treatment on the surfaces of two sides of the grid structure.
The further improvement is that the technical node of the N-tube IO component is less than 65 nm.
The invention has made the pointed design to the technical problem that the operation voltage of the IO assembly of N pipe is high and thus can produce the hot carrier effect easily, wherein, the lightly doped drain adopts the distributed structure with electric field of the drain terminal of reducing, and As with smaller diffusion coefficient As doping impurity of the lightly doped drain of the IO assembly of N pipe of small size such As technical node under 65nm in the prior art, the invention adopts P with larger diffusion coefficient As doping impurity of the lightly doped drain, meanwhile, As element, the atomic weight of P is smaller, so the lightly doped drain injection of P will produce smaller destruction to the lattice structure of the semiconductor substrate in the lightly doped drain, the invention also adjusts the injection angle and injection energy of the lightly doped drain injection, can make the diffusion area of the lightly doped drain bigger and the lattice structure better finally, this is favorable to the dispersion of the electric field intensity and the reduction of the peak value of the electric field intensity, and finally, the energy of hot carriers, namely hot electrons, can be reduced, thereby reducing the hot carrier effect and prolonging the service life of the hot carriers.
However, because a small-sized device has a requirement on the junction depth of the lightly doped drain region, the P doping structure can cause the junction depth of the lightly doped drain region to be too large, so that the short channel effect problem is caused, such as the increase of subthreshold leakage current and source-drain punch-through current, therefore, the structure of the lightly doped drain region is improved, and the structure of the halo implantation region is also improved at the same time.
In addition, boron doping in the halo implant region can improve the short channel effect of the device and reduce source-drain punch-through.
The distribution structure of carbon doping, boron doping and phosphorus doping in the lightly doped drain region of the halo implantation region is easily adjusted and optimized through implantation conditions such as implantation angles and implantation energy, so that the performance of the device can meet application requirements.
In addition, the invention can be realized by only correspondingly optimizing the doping structures of the lightly doped drain region and the halo injection region, and does not need to add an additional photomask or change the manufacturing process, so the invention also has the advantages of low process cost and compatibility with the existing manufacturing process.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a conventional N-pipe IO assembly;
FIG. 2 is a flow chart of a method of manufacturing a prior art N-transistor IO assembly;
FIG. 3 is a schematic structural diagram of an N-transistor IO assembly according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of a method for manufacturing an N-transistor IO assembly in accordance with an embodiment of the present invention.
Detailed Description
Fig. 3 is a schematic structural diagram of an N-transistor IO assembly according to an embodiment of the present invention; the N-tube IO component comprises a grid structure, a side wall 7, a channel region, a lightly doped drain region 5, a source region 8, a drain region 9 and a halo injection region 6.
The gate structure is formed on the surface of the semiconductor substrate 1. A field oxide 2 is also formed on the semiconductor substrate 1, and the field oxide 2 isolates an active region 8.
A P-type well is formed on the semiconductor substrate 1, a formation region of the N-tube IO component is located in a formation region of the P-type well, the P-type well is formed in the semiconductor substrate 1 in a region shown in fig. 3, a region position of the P-type well is directly referred to the region of the semiconductor substrate 1, and the P-type well is not marked independently. The gate structure is formed on the surface of the P-type well; the channel region is composed of the P-type wells which are positioned between the lightly doped drain regions 5 and between the source region 8 and the drain region 9 and are covered by the gate structure, and the surface of the channel region covered by the gate structure is used for forming a channel.
The semiconductor substrate 1 includes a silicon substrate.
The grid structure comprises a grid dielectric layer 3 and a grid conducting material layer 4 which are sequentially overlapped. In the embodiment of the invention, the gate dielectric layer 3 is silicon dioxide; the gate conductive material layer 4 is a polysilicon gate. In other embodiments, this can also be: the gate dielectric layer 3 is made of a high dielectric constant material; the gate conductive material layer 4 is a metal gate.
The lightly doped drain region 5 is formed in the semiconductor substrate 1 at two sides of the gate structure in a self-aligned manner.
The side walls 7 are formed on two side surfaces of the gate structure in a self-aligned manner.
The N + doped source region 8 and the drain region 9 are formed in the semiconductor substrate 1 on two sides of the gate structure, and the source region 8 and the drain region 9 are self-aligned with the corresponding side surfaces of the side walls 7.
The lightly doped drain region 5 is provided with a distributed structure for reducing a drain end electric field, the doping impurity of the lightly doped drain region 5 is phosphorus, the ion implantation of the lightly doped drain region 5 is angled lightly doped drain implantation, the distributed structure of the lightly doped drain region 5 is adjusted by combining the diffusivity of phosphorus, the implantation angle of the lightly doped drain implantation and the implantation energy, and the distributed structure of the lightly doped drain region 5 is adjusted to enable the service life of a hot carrier to meet a required value.
The halo implant region 6 encapsulates the lightly doped drain region 5, the halo implant region 6 comprising a boron and carbon doped structure doped with a common halo ion implantation process.
The carbon impurity distribution structure of the halo implantation region 6 serves as a barrier structure for phosphorus impurity diffusion of the lightly doped drain region 5 and the carbon impurity distribution structure of the halo implantation region 6 serves as an adjustment structure for improving a short channel effect caused by phosphorus diffusion into a P-type doped channel region, and the carbon impurity distribution structure of the halo implantation region 6 is adjusted by an implantation angle and implantation energy of the halo ion implantation.
The boron impurity distribution structure of the halo implantation region 6 is used as an adjusting structure for improving a short channel effect and reducing a source-drain punch-through effect, and the boron impurity distribution structure of the halo implantation region 6 is adjusted through the implantation angle and implantation energy of halo ion implantation.
The halo ion implantation is large-angle ion implantation taking the side surface of the grid structure as a self-alignment boundary, and the implantation angle of the halo ion implantation is 10-50 degrees.
The surfaces of the two sides of the grid structure are provided with surfaces which are subjected to pre-amorphization ion implantation treatment.
The halo ion implantation is performed before or after the ion implantation of the lightly doped drain region 5, and the pre-amorphization ion implantation is performed before the common ion implantation of the halo implantation region 6 and the ion implantation of the lightly doped drain region 5.
Preferably, the technical node of the N-tube IO component is 65nm or less.
The embodiment of the invention makes a targeted design for the technical problem that the N-tube IO component has high operating voltage so As to easily generate a hot carrier effect, wherein the lightly doped drain region 5 and the halo implantation region 6 of the device adopt a distributed structure with a reduced drain end electric field, and the lightly doped drain region 5 of the N-tube IO component with small size such As a technical node below 65nm in the prior art adopts As with a smaller diffusion coefficient As a doping impurity, the embodiment of the invention adopts P with a larger diffusion coefficient As the doping impurity of the lightly doped drain region 5, and meanwhile, compared with an As element, the atomic weight of P is smaller, so that the lightly doped drain implantation of P can generate smaller damage to the lattice structure of the semiconductor substrate 1 in the lightly doped drain region 5, and the embodiment of the invention also adjusts the implantation angle and implantation energy of the lightly doped drain implantation, finally, the diffusion area of the lightly doped drain region 5 can be larger and the lattice structure can be better, which is beneficial to the dispersion of the electric field intensity and the reduction of the peak value of the electric field intensity, and finally, the energy of hot carriers, namely hot electrons, can be reduced, thereby reducing the hot carrier effect and prolonging the service life of the hot carriers. Simulation experiments show that compared with the conventional device, the service life of the hot carrier of the device provided by the embodiment of the invention can be prolonged by about 100 times.
However, since a small-sized device has a requirement on the junction depth of the lightly doped drain region 5, the P-doped structure can cause the junction depth of the lightly doped drain region 5 to be too large, and thus a short channel effect problem is generated, such as sub-threshold leakage current and source-drain punch-through current increase, for this reason, the embodiment of the present invention improves the structure of the lightly doped drain region 5 and improves the structure of the halo implantation region 6 at the same time, the halo implantation region 6 of the embodiment of the present invention adds the common ion implantation of carbon on the basis of the halo ion implantation of boron, the common ion implantation of carbon is an implantation added on the basis of the existing N-tube IO device, the carbon doping in the halo implantation region 6 in combination with the P-doped lightly doped drain region 5 can improve the short channel effect caused by the diffusion of phosphorus into the P-type doped channel region, and can overcome the problem caused by the P-doping of the lightly doped drain region 5.
In addition, the boron doping in the halo implant region 6 improves the short channel effect of the device and reduces source-drain punch-through.
The distribution structures of the carbon doping, the boron doping and the phosphorus doping in the halo implantation region 6 and the lightly doped drain region 5 in the embodiment of the invention are easily adjusted and optimized through implantation conditions such as implantation angles and implantation energies, so that the performance of the device can meet the application requirements.
In addition, the embodiment of the invention can be realized by only correspondingly optimizing the doping structures of the lightly doped drain region 5 and the halo injection region 6, and does not need to add an additional photomask or change the manufacturing process, so the embodiment of the invention also has the advantages of low process cost and compatibility with the existing manufacturing process.
In order to solve the technical problem, the manufacturing method of the N-tube IO assembly provided by the invention comprises the following steps:
step one, forming a grid structure of an N-tube IO assembly on the surface of a semiconductor substrate 1.
In the method according to the embodiment of the present invention, a P-type well is formed on the semiconductor substrate 1, that is, before the gate structure is formed, a step of performing well implantation to form a P-type well is further included, and the well implantation corresponds to the step denoted by reference numeral 301 in fig. 4.
The forming region of the N-tube IO component is located in the forming region of the P-type well, and the gate structure is formed on the surface of the P-type well; the channel region is composed of the P-type wells which are positioned between the lightly doped drain regions 5 formed later and between the source region 8 and the drain region 9 formed later and are covered by the gate structure, and the surface of the channel region covered by the gate structure is used for forming a channel. The P-type wells are formed in the semiconductor substrate 1 in the regions shown in fig. 3, and the positions of the regions of the P-type wells are directly referred to the regions of the semiconductor substrate 1, and the P-type wells are not separately marked.
The semiconductor substrate 1 includes a silicon substrate. A field oxide 2 is also formed on the semiconductor substrate 1, and the field oxide 2 isolates an active region.
The grid structure comprises a grid dielectric layer 3 and a polysilicon grid which are sequentially overlapped.
The gate dielectric layer 3 is silicon dioxide. In other embodiments the method can also be: the gate dielectric layer 3 is made of a high dielectric constant material.
And step two, injecting a self-aligned lightly doped drain into the semiconductor substrate 1 at two sides of the grid structure to form a lightly doped drain region 5. The lightly doped drain implant is an angled lightly doped drain implant of P corresponding to step 305 in fig. 4.
The lightly doped drain region 5 is provided with a distributed structure for reducing a drain end electric field, the doping impurities of the lightly doped drain region 5 are phosphorus, the lightly doped drain implantation is angled ion implantation, the distributed structure of the lightly doped drain region 5 is adjusted by combining the diffusivity of the phosphorus, the implantation angle and the implantation energy of the lightly doped drain implantation, and the distributed structure of the lightly doped drain region 5 is adjusted to enable the service life of a hot carrier to meet a required value.
And step three, performing self-aligned halo ion implantation to form halo implantation regions 6 in the semiconductor substrate 1 on two sides of the gate structure, wherein the halo implantation regions 6 wrap the lightly doped drain regions 5.
The halo implant region 6 comprises a doped structure of boron and carbon doped using a common halo ion implantation process.
The carbon impurity distribution structure of the halo implantation region 6 serves as a barrier structure for phosphorus impurity diffusion of the lightly doped drain region 5 and the carbon impurity distribution structure of the halo implantation region 6 serves as an adjustment structure for improving a short channel effect caused by phosphorus diffusion into a P-type doped channel region, and the carbon impurity distribution structure of the halo implantation region 6 is adjusted by an implantation angle and implantation energy of the halo ion implantation.
The boron impurity distribution structure of the halo implantation region 6 is used as an adjusting structure for improving a short channel effect and reducing a source-drain punch-through effect, and the boron impurity distribution structure of the halo implantation region 6 is adjusted through the implantation angle and implantation energy of halo ion implantation.
The halo ion implantation of boron in the halo implantation region 6 is the halo ion implantation of B corresponding to step 303 in fig. 4.
The common ion implantation of carbon in the halo implant region 6 is the common ion implantation of C corresponding to step 304 in fig. 4.
And step four, forming a side wall 7 on the side surface of the grid structure.
And fifthly, performing N + doped source-drain injection by taking the side surface of the side wall 7 as a self-alignment condition to form a source region 8 and a drain region 9 in the semiconductor substrate 1 at two sides of the gate structure. The source-drain implant is the source-drain implant corresponding to step 306 in fig. 4.
The halo ion implantation is large-angle ion implantation, and the implantation angle is 10-50 degrees.
The sequence of the second step and the third step can be exchanged. After the first step is completed and before the second step and the third step are carried out, the method further comprises the following steps:
pre-amorphizing ion implantation is performed to perform a pre-amorphizing ion implantation process on the surfaces on both sides of the gate structure, and PAI implantation, i.e., pre-amorphizing ion implantation, corresponds to the PAI implantation shown in step 302 of fig. 4.
And the grid structure in the first step is a final grid structure. In other embodiments can also be: and the grid structure in the first step is a pseudo grid structure, and in the subsequent process, a grid replacement process is carried out to replace the polycrystalline silicon grid of the pseudo grid structure with a metal grid and form a final grid structure.
Preferably, the technical node of the N-tube IO component is 65nm or less.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (18)

1. An N pipe IO subassembly which characterized in that: the N-tube IO component comprises a grid structure, a side wall, a channel region, a lightly doped drain region, a source region, a drain region and a halo injection region;
the grid structure is formed on the surface of the semiconductor substrate;
the lightly doped drain region is formed in the semiconductor substrate at two sides of the grid structure in a self-alignment manner;
the side walls are formed on two side surfaces of the grid structure in a self-alignment manner;
the N + doped source region and the drain region are formed in the semiconductor substrate on two sides of the grid structure, and the source region and the drain region are self-aligned with the corresponding side faces of the side walls;
the lightly doped drain region is provided with a distributed structure for reducing a drain end electric field, the doping impurity of the lightly doped drain region is phosphorus, the ion implantation of the lightly doped drain region is angled lightly doped drain implantation, the distributed structure of the lightly doped drain region is adjusted by combining the diffusivity of the phosphorus, the implantation angle of the lightly doped drain implantation and the implantation energy, and the distributed structure of the lightly doped drain region is adjusted to enable the service life of a hot carrier to meet a required value;
the halo implantation region wraps the lightly doped drain region, and comprises a boron and carbon doped structure doped by adopting a common halo ion implantation process;
the carbon impurity distribution structure of the halo implantation region is used as a barrier structure for phosphorus impurity diffusion of the lightly doped drain region and is used as an adjusting structure for improving short channel effect caused by phosphorus diffusion into the P-type doped channel region, and the carbon impurity distribution structure of the halo implantation region is adjusted by the implantation angle and implantation energy of the halo ion implantation;
the boron impurity distribution structure of the halo implantation region is used as an adjusting structure for improving a short channel effect and reducing a source-drain punch-through effect, and the boron impurity distribution structure of the halo implantation region is adjusted through the implantation angle and implantation energy of halo ion implantation.
2. The N-pipe IO assembly of claim 1, wherein: a P-type well is formed on the semiconductor substrate, a forming region of the N-tube IO assembly is located in the forming region of the P-type well, and the gate structure is formed on the surface of the P-type well; the channel region is composed of the P-type trap which is positioned between the lightly doped drain regions and between the source region and the drain region and covered by the grid structure, and the surface of the channel region covered by the grid structure is used for forming a channel.
3. The N-pipe IO assembly of claim 2, wherein: the semiconductor substrate includes a silicon substrate.
4. The N-pipe IO assembly of claim 1, 2 or 3, wherein: the grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped.
5. The N-pipe IO assembly of claim 4 wherein: the gate dielectric layer is silicon dioxide or a high dielectric constant material.
6. The N-pipe IO assembly of claim 4 wherein: the grid electrode conducting material layer is a polysilicon grid or a metal grid.
7. The N-pipe IO assembly of claim 1, wherein: the halo ion implantation is large-angle ion implantation taking the side surface of the grid structure as a self-alignment boundary, and the implantation angle of the halo ion implantation is 10-50 degrees.
8. The N-pipe IO assembly of claim 7, wherein: the surfaces of the two sides of the grid structure are provided with surfaces subjected to pre-amorphization ion implantation treatment;
the halo ion implantation is performed before or after the ion implantation of the lightly doped drain region, and the pre-amorphization ion implantation is performed before the common ion implantation of the halo implantation region and the ion implantation of the lightly doped drain region.
9. The N-pipe IO assembly of claim 1, wherein: the technical node of the N-tube IO assembly is less than 65 nm.
10. A manufacturing method of an N-tube IO assembly is characterized by comprising the following steps:
step one, forming a grid structure of an N-tube IO assembly on the surface of a semiconductor substrate;
injecting a self-aligned lightly doped drain into the semiconductor substrate at two sides of the grid structure to form a lightly doped drain region;
the lightly doped drain region is provided with a distributed structure for reducing a drain end electric field, the doping impurity of the lightly doped drain region is phosphorus, the lightly doped drain implantation is angled ion implantation, the distributed structure of the lightly doped drain region is adjusted by combining the diffusivity of the phosphorus, the implantation angle and the implantation energy of the lightly doped drain implantation, and the distributed structure of the lightly doped drain region is adjusted to enable the service life of a hot carrier to meet a required value;
step three, self-aligned halo ions are implanted into the semiconductor substrate on two sides of the grid structure to form halo implantation regions, and the halo implantation regions wrap the lightly doped drain regions;
the halo implantation region comprises a boron and carbon doped structure doped by adopting a common halo ion implantation process;
the carbon impurity distribution structure of the halo implantation region is used as a barrier structure for phosphorus impurity diffusion of the lightly doped drain region and is used as an adjusting structure for improving short channel effect caused by phosphorus diffusion into the P-type doped channel region, and the carbon impurity distribution structure of the halo implantation region is adjusted by the implantation angle and implantation energy of the halo ion implantation;
the boron impurity distribution structure of the halo implantation region is used as an adjusting structure for improving a short channel effect and reducing a source-drain punch-through effect, and the boron impurity distribution structure of the halo implantation region is adjusted through the implantation angle and implantation energy of halo ion implantation;
fourthly, forming a side wall on the side face of the grid structure;
and fifthly, injecting N + doped source and drain into the semiconductor substrate on two sides of the grid structure by taking the side face of the side wall as a self-alignment condition to form a source region and a drain region.
11. The method of manufacturing an N-tube IO assembly of claim 10, wherein: a P-type well is formed on the semiconductor substrate, a forming region of the N-tube IO assembly is located in the forming region of the P-type well, and the gate structure is formed on the surface of the P-type well; the channel region is composed of the P-type trap which is positioned between the lightly doped drain regions and between the source region and the drain region and covered by the grid structure, and the surface of the channel region covered by the grid structure is used for forming a channel.
12. The method of manufacturing an N-tube IO assembly of claim 11, wherein: the semiconductor substrate includes a silicon substrate.
13. The method of manufacturing an N-tube IO assembly of claim 10, 11 or 12, wherein: the grid structure comprises a grid dielectric layer and a polysilicon grid which are sequentially overlapped.
14. The method of manufacturing an N-tube IO assembly of claim 13, wherein: the gate dielectric layer is silicon dioxide or a high dielectric constant material.
15. The method of manufacturing an N-tube IO assembly of claim 13, wherein: the grid structure in the first step is a final grid structure; or, the gate structure in the first step is a dummy gate structure, and in a subsequent process, a gate replacement process is further performed to replace a polysilicon gate of the dummy gate structure with a metal gate and form a final gate structure.
16. The method of manufacturing an N-tube IO assembly of claim 10, wherein: the halo ion implantation is large-angle ion implantation, and the implantation angle is 10-50 degrees.
17. The method of manufacturing an N-tube IO assembly of claim 10 or 16, wherein:
the sequence of the second step and the third step can be exchanged;
after the first step is completed and before the second step and the third step are carried out, the method further comprises the following steps:
and performing pre-amorphization ion implantation to realize pre-amorphization ion implantation treatment on the surfaces of two sides of the grid structure.
18. The method of manufacturing an N-tube IO assembly of claim 10, wherein: the technical node of the N-tube IO assembly is less than 65 nm.
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CN101777496A (en) * 2003-01-31 2010-07-14 富士通微电子株式会社 Method for manufacturing nMOS (n-channel Metal Oxide Semiconductor) transistor
CN103187276A (en) * 2011-12-27 2013-07-03 中芯国际集成电路制造(上海)有限公司 N-type MOS field-effect transistor and formation method thereof, semiconductor device and formation method of semiconductor device
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CN101777496A (en) * 2003-01-31 2010-07-14 富士通微电子株式会社 Method for manufacturing nMOS (n-channel Metal Oxide Semiconductor) transistor
US20050085055A1 (en) * 2003-10-17 2005-04-21 Chartered Semiconductor Manufacturing Ltd. End of range (EOR) secondary defect engineering using substitutional carbon doping
CN101350300A (en) * 2007-07-20 2009-01-21 中芯国际集成电路制造(上海)有限公司 Method for injecting ion into light dope source drain electrode
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