CN101697346B - Method for increasing length of effective channel of PMOS - Google Patents
Method for increasing length of effective channel of PMOS Download PDFInfo
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- CN101697346B CN101697346B CN2009101978059A CN200910197805A CN101697346B CN 101697346 B CN101697346 B CN 101697346B CN 2009101978059 A CN2009101978059 A CN 2009101978059A CN 200910197805 A CN200910197805 A CN 200910197805A CN 101697346 B CN101697346 B CN 101697346B
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Abstract
The invention provides a method for increasing the length of an effective channel of a PMOS, which comprises the following steps of: making an n-well and a p-well in a substrate; making a first polysilicon gate on the n-well and making a second polysilicon gate on the p-well; growing a first oxidation layer; injecting lightly doped source/drain in an n-well area; respectively growing a second oxidation layer on the surface of the n-well and the p-well; injecting lightly doped source/drain in a p-well area; respectively growing a silicon nitride layer and a third oxidation layer in the n-well and the p-well areas; etching the first oxidation layer, the second oxidation layer, the silicon nitride layer and the third oxidation layer; respectively forming a side wall around the polysilicon gates of the n-well and the p-well; injecting heavily doped source/drain in the n-well area; and injecting heavily doped source/drain in the p-well area. The method moves the step of injecting the lightly doped source/drain in the p-well area between the step of growing the second oxidation layer and the step of growing the silicon nitride layer and increases the length of the effective channel of the PMOS by using the second oxidation layer.
Description
Technical field
The invention belongs to a kind of semiconductor technology, relate in particular to a kind of method of the PMOS of increasing length of effective channel.
Background technology
In 90nm technique, with lower node, because dwindle (such as 65nm) of gate features size caused serious short-channel effect, make the leakage current of device sharply raise.Short-channel effect is exactly that the threshold voltage of explaining of MOSFET reduces along with dwindling of channel length.If add an operating voltage in drain electrode, short-channel effect can be exacerbated so.The result of short-channel effect is exactly the leakage current that increases device.In CMOS VLSI technique, channel length can be because the reason of technique has certain variation.Therefore, in the device design, short-channel effect is a very important Consideration.We must guarantee that the threshold voltage of minimum channel size in the middle of a chip can not be too low.
When source/leakage (Source/Drain) institute, making alive is very little, and grid (Gate) voltage is while being less than threshold voltage, transistor is in exhausting or weak transoid (Depletion/weak-Inversion), also referred to as sub-threshold region, Source at this moment and the leakage current between Drain are subthreshold current.Subthreshold current is mainly the diffusion leakage current of the PN junction of Drain end and weak transoid substrate, also can be referred to as weak pull-down current, and this electric current is relevant with the threshold voltage that the work function of the material on oxidated layer thickness, both sides determines.
In short channel device, because raceway groove is very little, near channel surface, between source depletion region and drain depletion region, influence each other, the depletion region at raceway groove Source/Drain two ends is deep into the below of Gate, the length of effective channel (LEFF) that makes Gate control diminishes, and so just may produce so-called short-channel effect (ShortChannel Effect).Example LEFF as shown in Figure 1 is less, just easily produces short-channel effect, especially all the more so for p channel transistor.The depletion region at raceway groove Source/Drain two ends is deep into the below of Gate, reduced the height of PN junction potential barrier, the charge carrier in source region is seized the opportunity the control that is not subject to grid voltage into drain region, add and add high level as short channel device Drain, the Drain electric field strengthens, some can directly be penetrated into the Source zone power line that Drain is sent, cause Source district electron emission, cause source-substrate potential barrier to reduce, these two kinds of phenomenons are called leakage inductance and answer potential barrier to reduce (Drain-induced Barrier Lowering, DIBL).
Simultaneously, because in the PMOS device, light dope is used is B or BF2, that the nmos device light dope is used is As or P, and the former B or BF2 more easily spread than latter As or P, cause the length of effective channel of PMOS less than NMOS.So, in the technique (shrink) for the device scaled down, it is larger that the electric leakage of PMOS can become.
In order to address this problem, United States Patent (USP) (the patent No.: the method that has adopted increase PMOS length of effective channel (LEFF) US5291052), the method utilization thickens the side wall of grid both sides, make original short channel elongated, as shown in Figure 2, the length of the LEFF marked in Fig. 2 is greater than the length of the LEFF of mark in Fig. 1.For long channel device, the voltage between source electrode and drain electrode is relatively very little on the impact of length of effective channel, and the size of subthreshold current and the size of voltage are substantially irrelevant, can avoid producing short-channel effect fully.But this manufacture method, owing on p channel transistor and N channel transistor size, difference having occurred, just need the masks that use more, is unfavorable for controlling cost.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method, solves the problem that produces short-channel effect in PMOS.
To achieve these goals, the present invention proposes a kind of method of the PMOS of increasing length of effective channel, said method comprising the steps of: make n trap and p trap in substrate, between described n trap and described p trap with a shallow trench isolation from, make the first polysilicon gate on described n trap, make the second polysilicon gate on described p trap; In said structure superficial growth the first oxide layer, form the ground floor grid side wall of first, second polysilicon; Described p well area is with photoresist masking, and at described n well area, described the first polysilicon gate of take injects as mask carries out lightly-doped source/leakage; In described n trap and described p trap superficial growth the second oxide layer, form the second layer side wall of polysilicon gate; Described n well area is with photoresist masking, and at described p well area, described the second polysilicon gate of take injects as mask carries out lightly-doped source/leakage; In n trap and p well area grown silicon nitride layer and the 3rd oxide layer, form the 3rd, the 4th layer of side wall of polysilicon gate, the recycling etch process, described the first oxide layer of etching, described the second oxide layer, described silicon nitride layer and described the 3rd oxide layer form the final side wall of polysilicon gate around the polysilicon gate of described n well area and described p well area; At described n well area, the final side wall of described polysilicon gate of take carries out after heavy-doped source/leakage injects removing the photoresist of described P well area as mask, at described p well area, the final side wall of described polysilicon gate of take carries out after heavy-doped source/leakage injects removing the photoresist of described n well area as mask.
Optionally, carry out at described n well area the mixture that dopant material that lightly-doped source/leakage injects is arsenic, phosphorus or arsenic and phosphorus.
Optionally, carrying out at described p well area the dopant material that lightly-doped source/leakage injects is BF
2, boron or BF
2Mixture with boron.
The scope of the density of the dopant material that optionally, described lightly-doped source/leakage is injected is 10
16To 10
17Between every cubic centimetre, individual ion.
Optionally, carry out at described n well area the mixture that dopant material that heavy-doped source/leakage injects is arsenic, phosphorus or arsenic and phosphorus.
Optionally, carrying out at described p well area the dopant material that heavy-doped source/leakage injects is BF
2, boron or BF
2Mixture with boron.
The scope of the density of the dopant material that optionally, described heavy-doped source/leakage is injected is 10
20To 10
21Between every cubic centimetre, individual ion.
Optionally, described the first oxidated layer thickness is that 10 dust to 60 dusts, described the second oxidated layer thickness are that 100 dust to 200 dusts, described silicon nitride layer thickness are that 200 dust to 400 dusts, described the 3rd oxidated layer thickness are 500 dust to 1500 dusts.
The useful technique effect of the method for a kind of PMOS of increasing length of effective channel of the present invention is: the step that the method for a kind of PMOS of increasing length of effective channel of the present invention is carried out lightly-doped source/leakage injection by the p well area has moved on between growth regulation dioxide layer and silicon nitride layer, has utilized the second oxide layer to increase PMOS effective communication length; In addition, without increasing extra mask, be conducive to the control of cost in the present invention.
The accompanying drawing explanation
Fig. 1 is the structural representation of existing CMOS;
Fig. 2 is the structural representation after existing CMOS improves;
Fig. 3 is the schematic flow sheet of the method for a kind of PMOS of increasing length of effective channel of the present invention;
Fig. 4 to Fig. 6 is the part manufacturing process schematic diagram of the method for a kind of PMOS of increasing length of effective channel of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Please refer to Fig. 3, Fig. 3 is the schematic flow sheet of the method for a kind of PMOS of increasing length of effective channel of the present invention, comprises the following steps:
Step 11: make n trap and p trap in substrate, between described n trap and described p trap with a shallow trench isolation from, make the first polysilicon gate on described n trap, make the second polysilicon gate shallow trench isolation from mainly being divided into three steps on described p trap, respectively groove etched, oxide is filled and the oxide planarization, in transistor, the making of grid structure is a step of most critical in flow process, because it has comprised the heat growth of the thinnest gate oxide and mint-mark and the etching of polysilicon gate, the polysilicon grating structure basic technology comprises the growth of gate oxide, polysilicon deposit and polysilicon gate etching, step 12: in said structure superficial growth the first oxide layer, form the ground floor grid side wall of first, second polysilicon, described oxide layer is silicon dioxide layer, the purpose of first oxide layer of growing is to escape injury for protection substrate in follow-up ion implantation process, this layer of side wall is generally that thickness is generally at 10 dust to 60 dusts by the layer of silicon dioxide of the method generation of boiler tube or high-temperature quick thermal annealing, step 13: described p well area is with photoresist masking, at described n well area, described the first polysilicon gate of take injects as mask carries out lightly-doped source/leakage, the mixture that dopant material is arsenic, phosphorus or arsenic and phosphorus, and the density range of the dopant material that described lightly doped drain injects is 10
16to 10
17between every cubic centimetre, individual ion, energy, dosage and junction depth all are starkly lower than the relevant parameter adopted while forming the n trap, step 14: in described n trap and described p trap superficial growth the second oxide layer, form the second layer side wall of polysilicon gate, the purpose one of growth regulation dioxide layer is in order to shield, the 2nd, can increase the thickness of the side wall around the second polysilicon gate, stop impurity to invade raceway groove, thereby increased the PMOS length of effective channel, this layer of oxidated layer thickness is 100 dust to 200 dusts, step 15: described n well area is with photoresist masking, and at described p well area, described the second polysilicon gate of take injects as mask carries out lightly-doped source/leakage, and the dopant material that carries out the lightly doped drain injection at described p well area is BF
2, boron or BF
2with the mixture of boron, the density range of the dopant material that described lightly doped drain injects is 10
16to 10
17between every cubic centimetre, individual ion, step 16: in n trap and p well area grown silicon nitride layer and the 3rd oxide layer, form the 3rd, the 4th layer of side wall of polysilicon gate, the recycling etch process, described the first oxide layer of etching, described the second oxide layer, described silicon nitride layer and described the 3rd oxide layer, form the final side wall of polysilicon gate around the polysilicon gate of described n well area and described p well area, described silicon nitride layer thickness is that 200 dust to 400 dusts, described the 3rd oxidated layer thickness are 500 dust to 1500 dusts, step 17: at described n well area, the final side wall of described polysilicon gate of take carries out after heavy-doped source/leakage injects removing the photoresist of described P well area as mask, at described p well area, the final side wall of described polysilicon gate of take carries out after heavy-doped source/leakage injects removing the photoresist of described n well area as mask, the dopant material that carries out heavy-doped source/leakage injection at described n well area is still the mixture of arsenic, phosphorus or arsenic and phosphorus, and the density range of the dopant material that described heavy-doped source/leakage is injected is 10
20to 10
21between every cubic centimetre, individual ion, the dopant material that carries out heavy-doped source/leakage injection at described p well area is BF
2, boron or BF
2with the mixture of boron, the scope of the density of the dopant material that described heavy-doped source/leakage is injected is 10
20to 10
21between every cubic centimetre, individual ion.
Then, please refer to Fig. 4 to Fig. 6, Fig. 4 to Fig. 6 is the part manufacturing process schematic diagram of the method for a kind of PMOS of increasing length of effective channel of the present invention, in Fig. 4, p well area 28 is sheltered with photoresist 24, the first polysilicon gate 21 is positioned at n well area 27, the second polysilicon gate 22 is positioned at p well area 28, between n well area 27 and p well area 28 with a shallow trench isolation from 25, at n well area 27, the zone of not sheltered by photoresist 24, first polysilicon gate 21 of take carries out the lightly doped drain injection as mask, arrow shown in figure is the direction of Implantation, about the type of ion and the dosage of injection, the preceding paragraph has been done detailed elaboration, in this superfluous words no longer.In addition, can also see first oxide layer 23 of having grown on n well area 27 and p well area 28 in figure.Fig. 5 is on the basis of Fig. 4, first removes the photoresist of p well area 28, then on the first oxide layer 23 growth regulation dioxide layer 26.Fig. 6 is on the basis of Fig. 5, n well area 27 is sheltered with photoresist 24, p well area 28 be take the second polysilicon gate 22 and is injected as mask carries out lightly-doped source/leakage, afterwards at n trap 27 and p trap 28 region growing silicon nitride layers and the 3rd oxide layer (not shown), the recycling etch process, described the first oxide layer of etching, described the second oxide layer, described silicon nitride layer and described the 3rd oxide layer form the final side wall of polysilicon gate around the polysilicon gate of described n well area and described p well area.Carry out after heavy-doped source/leakage is injected removing the photoresist of described P well area 28 at described n well area 27, carry out after heavy-doped source/leakage is injected removing the photoresist of described n well area 27 at described p well area 28.
The step that p well area in the present invention carries out lightly-doped source/leakage injection has moved on between growth regulation dioxide layer and silicon nitride layer, has utilized the second oxide layer to increase PMOS effective communication length.
Although the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have and usually know the knowledgeable in technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (4)
1. a method that increases the PMOS length of effective channel is characterized in that said method comprising the steps of:
Make n trap and p trap in substrate, between described n trap and described p trap with a shallow trench isolation from, make the first polysilicon gate on described n trap, making the second polysilicon gate on described p trap;
Growth the first oxide layer on described n trap and described p trap, described the first oxidated layer thickness is 10 dust to 60 dusts, forms the ground floor side wall of first, second polysilicon gate;
Described p well area is with photoresist masking, and at described n well area, described the first polysilicon gate of take injects as mask carries out lightly-doped source/leakage, the mixture that dopant material is arsenic, phosphorus or arsenic and phosphorus, and the scope of doping density is 10
20To 10
21Between every cubic centimetre, individual ion;
Growth regulation dioxide layer on described n trap and described p trap, described the second oxidated layer thickness is 100 dust to 200 dusts, forms the second layer side wall of first, second polysilicon gate;
Described n well area is with photoresist masking, and at described p well area, described the second polysilicon gate of take injects as mask carries out lightly-doped source/leakage, and dopant material is BF
2, boron or BF
2With the mixture of boron, the scope of doping density is 10
20To 10
21Between every cubic centimetre, individual ion;
In n trap and p well area grown silicon nitride layer and the 3rd oxide layer, described silicon nitride layer thickness is that 200 dust to 400 dusts, described the 3rd oxidated layer thickness are 500 dust to 1500 dusts, form the 3rd, the 4th layer of side wall of the first polysilicon gate and the 3rd, the 4th layer of side wall of the second polysilicon gate, the recycling etch process, described the first oxide layer of etching, described the second oxide layer, described silicon nitride layer and described the 3rd oxide layer form the final side wall of polysilicon gate around the polysilicon gate of described n well area and described p well area;
At described n well area, the final side wall of described polysilicon gate of take carries out after heavy-doped source/leakage injects removing the photoresist of described p well area as mask, at described p well area, the final side wall of described polysilicon gate of take carries out after heavy-doped source/leakage injects removing the photoresist of described n well area as mask.
2. a kind of method that increases the PMOS length of effective channel according to claim 1, is characterized in that carrying out at described n well area the mixture that dopant material that heavy-doped source/leakage injects is arsenic, phosphorus or arsenic and phosphorus.
3. a kind of method that increases the PMOS length of effective channel according to claim 1, is characterized in that carrying out at described p well area the dopant material that heavy-doped source/leakage injects is BF
2, boron or BF
2Mixture with boron.
4. according to a kind of described method that increases the PMOS length of effective channel of claim 2 or 3, it is characterized in that, the scope of the doping density that described heavy-doped source/leakage is injected is 10
20To 10
21Between every cubic centimetre, individual ion.
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| CN101697346B true CN101697346B (en) | 2013-12-04 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153455A (en) * | 1998-10-13 | 2000-11-28 | Advanced Micro Devices | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
| CN1534756A (en) * | 2003-04-02 | 2004-10-06 | 世界先进积体电路股份有限公司 | High voltage assembly capable of increasing penetrating voltage and manufacturing method of low voltage assembly matching with it |
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| JP2003100902A (en) * | 2001-09-21 | 2003-04-04 | Mitsubishi Electric Corp | Manufacturing method for semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153455A (en) * | 1998-10-13 | 2000-11-28 | Advanced Micro Devices | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
| CN1534756A (en) * | 2003-04-02 | 2004-10-06 | 世界先进积体电路股份有限公司 | High voltage assembly capable of increasing penetrating voltage and manufacturing method of low voltage assembly matching with it |
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