CN111463129A - GaN device based on in-situ passivation and oxidation process and preparation method thereof - Google Patents
GaN device based on in-situ passivation and oxidation process and preparation method thereof Download PDFInfo
- Publication number
- CN111463129A CN111463129A CN202010556931.5A CN202010556931A CN111463129A CN 111463129 A CN111463129 A CN 111463129A CN 202010556931 A CN202010556931 A CN 202010556931A CN 111463129 A CN111463129 A CN 111463129A
- Authority
- CN
- China
- Prior art keywords
- layer
- epitaxial
- gate oxide
- oxide dielectric
- top functional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 68
- 238000011065 in-situ storage Methods 0.000 title claims abstract description 46
- 230000008569 process Effects 0.000 title claims abstract description 46
- 230000003647 oxidation Effects 0.000 title claims abstract description 27
- 238000007254 oxidation reaction Methods 0.000 title claims abstract description 27
- 238000002161 passivation Methods 0.000 title claims abstract description 25
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 314
- 239000002346 layers by function Substances 0.000 claims abstract description 68
- 230000008021 deposition Effects 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000013589 supplement Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims description 53
- 230000004888 barrier function Effects 0.000 claims description 39
- 230000000153 supplemental effect Effects 0.000 claims description 35
- 229910002704 AlGaN Inorganic materials 0.000 claims description 19
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 6
- 239000012445 acidic reagent Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims 2
- 238000002203 pretreatment Methods 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910001882 dioxygen Inorganic materials 0.000 description 6
- 230000006911 nucleation Effects 0.000 description 5
- 238000010899 nucleation Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000011066 ex-situ storage Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000001657 homoepitaxy Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- BYFGZMCJNACEKR-UHFFFAOYSA-N aluminium(i) oxide Chemical compound [Al]O[Al] BYFGZMCJNACEKR-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 150000002902 organometallic compounds Chemical class 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000001963 growth medium Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010952 in-situ formation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000002609 medium Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a GaN device based on in-situ passivation and oxidation process and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate, forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer, the epitaxial structure is provided with a top functional layer positioned on the uppermost layer, an epitaxial supplement layer is deposited on the surface of the top functional layer in a deposition chamber, the material of the epitaxial supplement layer is the same as that of the top functional layer, and a gate oxide dielectric layer is deposited on the epitaxial supplement layer in situ. According to the invention, through the deposition of the epitaxial supplement layer and the in-situ deposition of the gate oxide dielectric layer, the in-situ high-quality interface of the epitaxial supplement layer/the gate oxide dielectric layer is realized, the film quality of the gate oxide dielectric layer is improved, the interface defect is reduced, and the device performance is optimized. Less positive fixed charge, lower leakage current and higher breakdown voltage can be achieved.
Description
Technical Field
The invention belongs to the field of semiconductor power electronic devices, and particularly relates to a GaN device based on an in-situ passivation and oxidation process and a preparation method thereof.
Background
Nowadays, human production and life are not free from electric power, and with the improvement of energy-saving consciousness of people, power semiconductor devices with high conversion efficiency become hot spots of domestic and foreign research. The power semiconductor device is widely applied to household appliances, power converters, industrial control and the like, and different power semiconductor devices are adopted under different rated voltages and currents. High Electron Mobility Transistors (HEMTs) are hot spots developed at home and abroad, have made breakthroughs in many fields, and have a wide application prospect particularly in the aspects of High temperature, High power, High frequency and the like.
GaN transistors are used for their excellent material properties, such as: wide band gap, large critical electric field, high electron mobility, high saturation velocity and high density two-dimensional electron gas (2 DEG) caused by spontaneous and piezoelectric polarization effects, and has good application in the fields of power switches and radio frequency. GaN devices suffer from high gate leakage current, current collapse effects and poor long-term stability. Replacing a Heterojunction (HFET) schottky gate structure with a Metal Oxide Semiconductor (MOS) structure may suppress gate leakage current. Surface passivation techniques using various dielectrics can improve the current collapse effect by reducing the density of surface states. There are still several challenges to be solved. In particular, the dielectric material and its interface are optimized to reduce leakage current, eliminate current collapse effect, etc.
Therefore, how to provide an in-situ passivation and oxidation process-based GaN device and a method for fabricating the same are necessary to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an in-situ passivation and oxidation process-based GaN device and a method for fabricating the same, which are used to solve the problems of the prior art, such as gate dielectric material performance to be optimized and leakage current.
In order to achieve the above objects and other related objects, the present invention provides a method for fabricating a GaN device based on in-situ passivation and oxidation processes, the method comprising the steps of:
providing a semiconductor substrate;
forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer, and the epitaxial structure is provided with a top functional layer positioned on the uppermost layer;
depositing an epitaxial supplementary layer on the surface of the top functional layer of the epitaxial structure in a deposition chamber, wherein the material of the epitaxial supplementary layer is the same as that of the top functional layer; and;
and forming a gate oxide dielectric layer on the epitaxial supplement layer by in-situ deposition based on the same deposition chamber.
Optionally, the top functional layer comprises the GaN channel layer or a barrier layer formed on the GaN channel layer.
Optionally, when the top functional layer is the barrier layer, the sum of the thicknesses of the barrier layer and the epitaxial supplementary layer is less than 30nm, the barrier layer includes an AlGaN layer or an InAlN layer, and the epitaxial supplementary layer correspondingly includes an AlGaN layer or an InAlN layer; and when the top functional layer is the GaN channel layer, the thickness of the epitaxial supplementary layer is less than 10 nm.
Optionally, a pretreatment process is performed on the surface of the top functional layer before the epitaxial supplemental layer is formed, wherein the pretreatment process includes a process of ozone oxidation and acid reagent cleaning to treat the surface of the top functional layer.
Optionally, when the top functional layer is the barrier layer, etching away a first preset thickness of the barrier layer based on the pretreatment process, and controlling the sum of the thicknesses of the barrier layer and the epitaxial supplementary layer to be less than 30nm based on the first preset thickness; and when the top functional layer is the GaN channel layer, etching off a second preset thickness of the GaN channel layer based on the pretreatment process, wherein the second preset thickness is between 1 and 5 nm.
Optionally, the deposition temperature of the epitaxial supplemental layer is between 900 ℃ and 1000 ℃.
Optionally, the deposition temperature of the gate oxide dielectric layer is between 600 ℃ and 800 ℃.
Optionally, the deposition pressure of the gate oxide dielectric layer is between 80Torr and 100 Torr.
Optionally, the thickness of the gate oxide dielectric layer is between 20nm and 50 nm.
Optionally, the method further includes, after forming the gate oxide dielectric layer: and forming a source electrode opening and a drain electrode opening on the gate dielectric layer, wherein the epitaxial supplement layer is exposed from the source electrode opening and the drain electrode opening, a gate structure is formed on the gate oxide dielectric layer, a source electrode is formed on the epitaxial supplement layer corresponding to the source electrode opening, and a source electrode and a drain electrode are formed on the epitaxial supplement layer corresponding to the drain electrode opening.
Optionally, the deposition chamber includes a metal organic compound chemical vapor deposition chamber, and the epitaxial supplemental layer and the gate oxide dielectric layer are formed by metal organic compound chemical vapor deposition in-situ deposition.
Optionally, the oxygen source of the gate oxide dielectric layer includes oxygen gas or ozone.
The invention also provides a GaN device based on the in-situ passivation and oxidation process, which is preferably prepared by the preparation method of the GaN device based on the in-situ passivation and oxidation process, of the invention, and of course, can also be prepared by other preparation methods, wherein the GaN device comprises:
a semiconductor substrate;
an epitaxial structure comprising a GaN channel layer, wherein the epitaxial structure has a top functional layer located at an uppermost layer;
the epitaxial supplementary layer is formed on the surface of the top functional layer, and the material of the epitaxial supplementary layer is the same as that of the top functional layer; and;
and the gate oxide dielectric layer is formed on the epitaxial supplementary layer, and the gate oxide dielectric layer and the epitaxial supplementary layer are material layers subjected to in-situ deposition based on the same deposition chamber.
Optionally, the top functional layer comprises the GaN channel layer or a barrier layer formed on the GaN channel layer.
Optionally, the in-situ passivation and oxidation process-based GaN device further includes a gate structure formed on the gate oxide dielectric layer, and a source electrode and a drain electrode formed on the epitaxial supplemental layer.
Optionally, the oxygen source of the gate oxide dielectric layer includes oxygen gas or ozone.
Optionally, the thickness of the gate oxide dielectric layer is between 20nm and 50 nm.
Optionally, when the top functional layer is the barrier layer, the sum of the thicknesses of the barrier layer and the epitaxial supplementary layer is less than 30nm, the barrier layer includes an AlGaN layer or an InAlN layer, and the epitaxial supplementary layer correspondingly includes an AlGaN layer or an InAlN layer; and when the top functional layer is the GaN channel layer, the thickness of the epitaxial supplementary layer is less than 10 nm.
According to the GaN device based on the in-situ passivation and oxidation process and the preparation method thereof, the epitaxial supplement layer is deposited, the gate oxide dielectric layer is deposited in situ, the in-situ high-quality interface of the epitaxial supplement layer/the gate oxide dielectric layer is realized, the film quality of the gate oxide dielectric layer is improved, the interface defect is reduced, and the device performance is optimized. Less positive fixed charge, lower leakage current and higher breakdown voltage can be achieved.
Drawings
Fig. 1 is a flow chart illustrating the fabrication of a GaN device based on in-situ passivation and oxidation processes according to an exemplary embodiment of the present invention.
Fig. 2 shows a schematic structural view of a semiconductor substrate provided in the fabrication of an exemplary GaN device of the present invention.
Fig. 3 is a schematic structural diagram illustrating the formation of an epitaxial structure in the fabrication of an exemplary GaN device according to the present invention.
Fig. 4 is a schematic structural view illustrating the formation of an epitaxial structure in the fabrication of another exemplary GaN device according to the present invention.
FIG. 5 is a schematic diagram of the structure of the epitaxial supplemental layer formed in the fabrication of an exemplary GaN device of the invention.
FIG. 6 is a schematic structural diagram illustrating the formation of a gate oxide dielectric layer in the fabrication of an exemplary GaN device of the invention.
Fig. 7 is a schematic diagram illustrating the formation of a source structure, a drain electrode, and a source electrode in the fabrication of an exemplary GaN device of the present invention.
Description of the element reference numerals
100-a semiconductor substrate, 101-an epitaxial structure, 102-a nucleation layer, 103-a GaN channel layer, 104-a barrier layer, 105-a top functional layer, 106-an epitaxial supplementary layer, 107-a gate oxide dielectric layer, 108-a gate structure, 109-a source electrode, 110-a drain electrode, and S1-S4.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, number and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for manufacturing a GaN device based on in-situ passivation and oxidation processes, the method comprising the steps of:
s1: providing a semiconductor substrate;
s2: forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer, and the epitaxial structure is provided with a top functional layer positioned on the uppermost layer;
s3: depositing an epitaxial supplementary layer on the surface of the top functional layer of the epitaxial structure in a deposition chamber, wherein the material of the epitaxial supplementary layer is the same as that of the top functional layer;
s4: and forming a gate oxide dielectric layer on the epitaxial supplement layer by in-situ deposition based on the same deposition chamber.
The method for manufacturing the semiconductor device structure of the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the manufacturing sequence of the semiconductor device structure of the present invention, and the skilled person can change the sequence according to the actual process steps, and fig. 1 shows only the manufacturing steps of the semiconductor device structure in one example.
As shown in S1 in fig. 1 and fig. 2, step S1 is performed to provide the semiconductor substrate 100. The semiconductor substrate 100 may include a sapphire substrate, a SiC substrate, a Si substrate, a GaN substrate, and the like as substrates, in other embodiments, the semiconductor substrate 100 may also be a substrate including other element semiconductors or compound semiconductors, and in addition, the semiconductor substrate 100 may also be a stacked structure.
As shown in S2 of fig. 1 and fig. 3, step S2 is performed to form an epitaxial structure 101 on the semiconductor substrate 100, where the epitaxial structure 101 includes a GaN channel layer 103, and the epitaxial structure 101 has a top functional layer 105 on an uppermost layer. As an example, the top functional layer 105 may be the GaN channel layer 103, i.e., the GaN channel layer 103 serves as the uppermost material layer of the epitaxial structure 101, so that a MOSFET device structure may be formed by gate oxide on the basis of the above. In another example, the top functional layer 105 may be a barrier layer 104 on the GaN channel layer 103, i.e., the barrier layer 104 is formed on the GaN channel layer 103 as the uppermost material layer of the epitaxial structure 101, so that the GaN channel layer 103 and barrier layer 104 structure further forms a MOS-HEMT device structure on the basis of the above structure. In the MOSFET structure, GaN is used as a channel, and no additional barrier layer polarizes two-dimensional electron gas in the GaN channel at the uppermost layer, so that the device is controlled to be started through a grid electrode; in the MOS-HEMT structure, GaN is taken as a channel, an AlGaN or InAlN barrier layer covers the GaN, and the barrier layer polarizes a two-dimensional electronic gas channel in the GaN channel and is a normally-open depletion device.
In an example, the epitaxial structure 101 further includes a nucleation layer 102 and a buffer layer 102a, wherein the nucleation layer 102 is formed on the semiconductor substrate 100, the buffer layer 102a is formed on the nucleation layer 102, and the GaN channel layer 103 is formed on the buffer layer 102a, wherein the nucleation layer 102 includes, but is not limited to, an AlN layer. The buffer layer 102a includes, but is not limited to, an AlGaN layer. The barrier layer 104 includes an AlGaN layer or an InAlN layer. The invention has no requirement on epitaxial wafers, is not limited to the above examples, and can carry out the in-situ passivation and oxidation process provided by the invention.
As shown in S3 of fig. 1 and fig. 5, next, in step S3, an epitaxial supplemental layer 106 is formed on the top functional layer 105 in the deposition chamber. As an example, the material of the epitaxial supplemental layer 106 is the same as the material of the top functional layer 105. The epitaxial supplemental layer 106 may serve as a passivation layer and may also serve as a part of the epitaxial structure, in this case, the epitaxial structure 101 may be understood as an initial epitaxial wafer, and as will be understood by those skilled in the art, in addition, the epitaxial supplemental layer 106 also serves as a transition layer of a subsequent material layer, so as to provide a structural basis for implementation of a subsequent process, in an example, the deposition chamber includes a Metal Organic Chemical Vapor Deposition (MOCVD) chamber, and the epitaxial supplemental layer 106 is deposited by using a Metal Organic Chemical Vapor Deposition (MOCVD).
The material of the epitaxial supplemental layer 106 is designed to be the same as the material of the top functional layer 105, for example, both materials are selected to be GaN (the same as the material of the GaN channel layer 103), or both materials are selected to be an AlGaN layer or an InAlN layer (the same as the material of the barrier layer 104), so that homoepitaxy can be realized on the top functional layer 105, and the quality of the deposited material layer can be improved. Meanwhile, the epitaxial supplement layer 106 can be made thinner, so that the effect of the epitaxial supplement layer can be exerted, the performance of the final device cannot be affected due to too thick deposition, further, compared with heteroepitaxy, the process difficulty is lower, the process is easy to ensure the purity and the quality, and meanwhile, homoepitaxy can relieve the defects caused by the problems of different lattice constants and thermal mismatch, and relieve the influence of the defects on the film forming quality of a subsequently formed gate oxide dielectric layer. When the top functional layer 105 is the barrier layer 104, the sum of the thicknesses of the barrier layer 104 and the epitaxial supplemental layer 106 is less than 30nm, for example, the sum of the thicknesses may be 12nm, 15nm, or 20 nm; when the top functional layer 105 is the GaN channel layer 103, the thickness of the epitaxial supplemental layer 106 is less than 10nm, for example, 6nm or 8 nm.
As an example, the surface of the top functional layer 105 is subjected to a pretreatment process before the epitaxial supplemental layer 106 is formed, and the pretreatment process includes a process of ozone oxidation and acid reagent cleaning to treat the surface of the top functional layer 105. For example, surface cleaning is performed by ozone, and the surface of the epitaxial wafer is oxidized by introducing ozone into the oxidation furnace, and then the surface oxide is removed by using an HF reagent, thereby performing the function of surface cleaning and purification. This treatment can effectively remove carbon (C) and organic contaminants from the surface of the top functional layer 105 (e.g., GaN layer or AlGaN layer or InAlN layer) to provide a clean surface for other process steps.
As an example, a first preset thickness of the top functional layer 105 is etched based on the pretreatment process, and the sum of the thicknesses of the top functional layer 105 and the epitaxial supplement layer 106 is controlled to be less than 30nm based on the first preset thickness, that is, in an example, if the thickness of the top functional layer 105 is already close to or greater than or equal to 30, the top functional layer 105 with the first preset thickness may be etched by the pretreatment process, for example, the top functional layer 105 with the first preset thickness may be oxidized by O2 plasma, and then the top functional layer 105 with the remaining 15nm (such as an AlGaN layer or an InAlN layer) is etched by HCl, and then the epitaxial supplement layer 106 with a thickness of 3nm (such as an AlGaN layer or an InAlN layer) is formed by MOCVD epitaxy.
In another example, when the top functional layer 105 is the GaN channel layer 103, a second predetermined thickness of the GaN channel layer 103 is etched based on the pretreatment process, where the second predetermined thickness is between 1 nm and 5nm, for example, 2nm and 3nm, which is beneficial to ensure the surface modification by the pretreatment process and reduce the process difficulty.
As shown in S3 of fig. 1 and fig. 6, step S4 is finally performed to form a gate oxide dielectric layer 107 on the epitaxial supplemental layer 106 based on the same deposition chamber. The gate oxide dielectric layer 107 may be a high-k gate oxide, and the material thereof includes, but is not limited to, Al2O 3. Based on the above process, the in-situ deposition of the gate oxide dielectric layer 107 can be realized, and the in-situ deposition refers to that two different materials grow back and forth in the same cavity, but the two different materials do not need to be taken out of the cavity after the growth of one material is completed, the air is exposed, and then the two different materials are sent into other cavities for the growth of the other material. In many GaN transistors, the gate oxide dielectric layer and the top functional layer (e.g., nitride epitaxial layer) are typically deposited in different environments because of the requirements of the device fabrication process flow and because of the extensive ex-situ dielectric deposition tools. In addition, conventional device development or production is an outsourced epitaxial wafer, where the surface of the top functional layer (e.g., nitride epitaxial layer) is etched, cleaned and/or pretreated prior to deposition of the gate oxide dielectric layer, the latter two being typical operations that prevent severe impurity trapping at the interface (gate oxide dielectric layer/nitride interface) and the formation of defects that may adversely affect gate performance. The invention can solve the problems by in-situ deposition of the gate oxide dielectric layer. The invention can form a metal-oxide-semiconductor device structure by in-situ depositing the high-k gate oxide by utilizing, for example, a GaN epitaxial supplementary layer and then in-situ depositing the high-k gate oxide (the traditional gate oxide deposition is ex-situ deposition and the interface characteristic is not ideal).
The epitaxial supplemental layer 106 (e.g., GaN) ensures that the gate oxide dielectric layer 107 is grown without exposure to air after the epitaxial supplemental layer 106 is grown. In an example, the material of the epitaxial supplemental layer 106 is the same as the material of the top functional layer 105, for example, GaN is selected, the quality of GaN grown on GaN is better than the quality of the interface of the growth medium material on GaN and the grown material, that is, the quality of homoepitaxy growing the same material on the surface of the existing material is better than the quality of heteroepitaxy growing different materials, and the quality of in-situ deposition film formation is also better because the epitaxial supplemental layer 106/gate oxide dielectric layer 107 has no cavity in the middle and the surface is not exposed to air. The epitaxial supplementary layer 106 realizes the in-situ formation of the gate oxide dielectric layer 107/epitaxial supplementary layer 106 interface, greatly reduces the interface defects caused by the ectopic growth, and optimizes the device performance through the in-situ high-quality interface. The film forming quality and the formed interface quality of the gate oxide dielectric layer 107 are improved, and the device can have fewer positive fixed charges, lower leakage current and higher breakdown voltage.
In one example, the deposition chamber comprises a Metal Organic Chemical Vapor Deposition (MOCVD) chamber, and the epitaxial supplemental layer 106 and the gate oxide dielectric layer 107 are formed by in-situ deposition of metal organic chemical vapor deposition, the conventional ex-situ deposition is to perform surface cleaning treatment on the surface of an existing material and then perform gate oxide deposition by using a method generally known as a L D, but the interface is not 100% clean.
As an example, the deposition temperature of the epitaxial supplemental layer 106 is between 900 ℃ and 1000 ℃, for example, 920 ℃, 950 ℃, 980 ℃ may be selected.
By way of example, the deposition temperature of the gate oxide dielectric layer 107 is between 600 ℃ and 800 ℃, and for example, 650 ℃, 700 ℃, and 750 ℃ can be selected.
By way of example, the deposition pressure of the gate oxide dielectric layer 107 is between 80Torr and 100Torr, and may be selected from 90 Torr, 95 Torr and 100Torr, for example.
By way of example, the thickness of the gate oxide dielectric layer 107 is between 20nm and 50nm, and may be selected to be 30nm, 35nm or 40 nm.
As an example, the oxygen source of the gate oxide dielectric layer 107 includes oxygen gas, or ozone (O3), for example, when forming Al2O3 as the gate oxide dielectric layer, trimethyl aluminum (TMA) and oxygen gas (O2) are used as the gas source for preparation, and oxygen gas is used as the oxygen source, for example, compared to water as the oxygen source, for example, compared to the conventional formation of Al2O3 by a L D deposition (TMA, H2O as the gas source), O2 is used instead of H2O to avoid the effect of H-on the film formation quality, and improve the fixed charge defect.
As shown in fig. 7, as an example, after forming the gate oxide dielectric layer 107, the method further includes the steps of: forming a source opening and a drain opening on the gate dielectric layer 107, wherein the epitaxial supplement layer 106 is exposed from the source opening and the drain opening, forming a gate structure on the gate oxide dielectric layer 107, forming a source electrode 109 on the epitaxial supplement layer 106 corresponding to the source opening, and forming a source drain electrode 110 on the epitaxial supplement layer 106 corresponding to the drain opening. To further complete device fabrication. The ohmic contacts of the source and the drain are on the epitaxial supplement layer 106, i.e. the gate oxide medium in the source and drain regions needs to be etched away, and then the metal electrode is deposited to form ohmic contact with the epitaxial supplement layer 106. Optionally, the ohmic contact electrode may be Ta/Al/Ta, and then the ohmic contact electrode is annealed at a low temperature, for example, at 530 ℃ to 580 ℃ for 55s to 65s, in this example, the annealing temperature is 550 ℃ and the annealing time is 60s, so as to prevent the gate oxide from being damaged by the 850 ℃ high temperature annealing of the conventional Ti/Al/Ni/Au electrode. Optionally, after the deposition of the conventional source and drain metal electrodes is completed, laser annealing is used to realize good ohmic contact, so that the damage of the conventional high-temperature annealing to gate oxide is avoided. In addition, in an example, for a structure in which a barrier layer (e.g., an AlGaN layer) is formed, after the epitaxial supplemental layer 106 and the gate oxide dielectric layer 107 are formed, and after the source opening and the drain opening are formed, the barrier layer (the AlGaN layer) is etched to the surface of a channel layer (e.g., a GaN layer), and then a metal electrode is deposited, which is beneficial to better ohmic contact. In addition, a gate metal electrode is deposited on the gate oxide dielectric layer 107 to form a metal-oxide-semiconductor structure.
In addition, as shown in fig. 6, and as shown in fig. 1 to 4 and fig. 7, the present invention further provides a GaN device based on an in-situ passivation and oxidation process, where the GaN device is preferably prepared by the method for preparing a GaN device based on an in-situ passivation and oxidation process of the present invention, and of course, other preparation methods may also be used, and relevant structural features and beneficial effects may be referred to the description of the preparation method, and are not described herein again, and the GaN device includes:
a semiconductor substrate 100;
an epitaxial structure 101, the epitaxial structure 101 comprising a GaN channel layer 103, wherein the epitaxial structure 101 has a top functional layer 105 on an uppermost layer;
an epitaxial supplementary layer 106 formed on the surface of the top functional layer 105, wherein the material of the epitaxial supplementary layer 106 is the same as that of the top functional layer 105;
and the gate oxide dielectric layer 107 is formed on the epitaxial supplement layer 106, and the gate oxide dielectric layer 107 and the epitaxial supplement layer 106 are material layers which are subjected to in-situ deposition based on the same deposition chamber.
As an example, the top functional layer 105 includes the GaN channel layer 103 or a barrier layer 104 formed on the GaN channel layer 103.
As an example, the GaN device based on the in-situ passivation and oxidation process further includes a gate structure 108 formed on the gate oxide dielectric layer 107 and a source electrode 109 and a drain electrode 110 formed on the epitaxial supplement layer 106.
As an example, the oxygen source of the gate oxide dielectric layer 107 includes oxygen gas or ozone.
Illustratively, the thickness of the gate oxide dielectric layer 107 is between 20nm and 50 nm.
As an example, the top functional layer 105 comprises a GaN layer and the epitaxial supplemental layer 106 comprises a GaN layer.
As an example, when the top functional layer 105 is the barrier layer 104, the sum of the thicknesses of the barrier layer 104 and the epitaxial supplemental layer 106 is less than 30 nm.
As an example, the barrier layer 104 includes an AlGaN layer or an InAlN layer, and the epitaxial supplemental layer 106 includes an AlGaN layer or an InAlN layer, respectively.
As an example, when the top functional layer 105 is the GaN channel layer, the thickness of the epitaxial supplemental layer 106 is less than 10 nm.
In summary, according to the in-situ passivation and oxidation process-based GaN device and the preparation method thereof, the epitaxial supplement layer/gate oxide dielectric layer in-situ deposition is utilized to realize the in-situ high-quality interface of the epitaxial supplement layer/gate oxide dielectric layer through the deposition of the epitaxial supplement layer, the film quality of the gate oxide dielectric layer is improved, the interface defect is reduced, and the device performance is optimized. Less positive fixed charge, lower leakage current and higher breakdown voltage can be achieved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A preparation method of a GaN device based on in-situ passivation and oxidation processes is characterized by comprising the following steps:
providing a semiconductor substrate;
forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer, and the epitaxial structure is provided with a top functional layer positioned on the uppermost layer;
depositing an epitaxial supplementary layer on the surface of the top functional layer of the epitaxial structure in a deposition chamber, wherein the material of the epitaxial supplementary layer is the same as that of the top functional layer; and
and forming a gate oxide dielectric layer on the epitaxial supplement layer by in-situ deposition based on the same deposition chamber.
2. The method of claim 1, wherein the top functional layer comprises the GaN channel layer or a barrier layer formed on the GaN channel layer.
3. The method of claim 2, wherein when the top functional layer is the barrier layer, a sum of thicknesses of the barrier layer and the epitaxial supplemental layer is less than 30nm, the barrier layer comprises an AlGaN layer or an InAlN layer, and the epitaxial supplemental layer correspondingly comprises an AlGaN layer or an InAlN layer; and when the top functional layer is the GaN channel layer, the thickness of the epitaxial supplementary layer is less than 10 nm.
4. The method of claim 1, wherein a pretreatment process is performed on the surface of the top functional layer before the epitaxial supplemental layer is formed, and the pretreatment process comprises a process of ozone oxidation and acid reagent cleaning to treat the surface of the top functional layer.
5. The method of claim 4, wherein when the top functional layer is the barrier layer, a first predetermined thickness of the barrier layer is etched based on the pre-treatment process, and a sum of thicknesses of the barrier layer and the epitaxial supplemental layer is controlled to be less than 30nm based on the first predetermined thickness; and when the top functional layer is the GaN channel layer, etching off a second preset thickness of the GaN channel layer based on the pretreatment process, wherein the second preset thickness is between 1 and 5 nm.
6. The method of claim 1, wherein the deposition temperature of the epitaxial supplemental layer is between 900-1000 ℃; the deposition temperature of the gate oxide dielectric layer is between 600 ℃ and 800 ℃, and the deposition pressure of the gate oxide dielectric layer is between 80Torr and 100 Torr; the thickness of the gate oxide dielectric layer is between 20nm and 50 nm.
7. The method of claim 1, further comprising the step of, after forming the gate oxide dielectric layer: and forming a source electrode opening and a drain electrode opening on the gate dielectric layer, wherein the epitaxial supplement layer is exposed from the source electrode opening and the drain electrode opening, a gate structure is formed on the gate oxide dielectric layer, a source electrode is formed on the epitaxial supplement layer corresponding to the source electrode opening, and a source electrode and a drain electrode are formed on the epitaxial supplement layer corresponding to the drain electrode opening.
8. The method of any one of claims 1-7, wherein the deposition chamber comprises a MOCVD chamber, and the epitaxial supplemental layer and the gate oxide dielectric layer are formed by MOCVD in-situ deposition.
9. The method of claim 8, wherein the oxygen source of the gate oxide dielectric layer comprises oxygen or ozone.
10. A GaN device based on in-situ passivation and oxidation processes, the GaN device comprising:
a semiconductor substrate;
an epitaxial structure comprising a GaN channel layer, wherein the epitaxial structure has a top functional layer located at an uppermost layer;
the epitaxial supplementary layer is formed on the surface of the top functional layer, and the material of the epitaxial supplementary layer is the same as that of the top functional layer; and
and the gate oxide dielectric layer is formed on the epitaxial supplementary layer, and the gate oxide dielectric layer and the epitaxial supplementary layer are material layers subjected to in-situ deposition based on the same deposition chamber.
11. The in-situ passivation and oxidation process-based GaN device of claim 10, wherein the top functional layer comprises the GaN channel layer or a barrier layer formed on the GaN channel layer.
12. The in-situ passivation and oxidation process-based GaN device of claim 10, further comprising a gate structure formed on the gate oxide dielectric layer and source and drain electrodes formed on the epitaxial supplemental layer; the thickness of the gate oxide dielectric layer is between 20nm and 50 nm.
13. The in-situ passivation and oxidation process-based GaN device of claim 10, wherein when the top functional layer is the barrier layer, the sum of the thicknesses of the barrier layer and the epitaxial supplemental layer is less than 30nm, the barrier layer comprises an AlGaN layer or an InAlN layer, and the epitaxial supplemental layer correspondingly comprises an AlGaN layer or an InAlN layer; and when the top functional layer is the GaN channel layer, the thickness of the epitaxial supplementary layer is less than 10 nm.
14. The GaN device of any of claims 10-13 wherein the oxygen source of the gate oxide dielectric layer comprises oxygen or ozone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010556931.5A CN111463129B (en) | 2020-06-18 | 2020-06-18 | GaN device based on in-situ passivation and oxidation process and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010556931.5A CN111463129B (en) | 2020-06-18 | 2020-06-18 | GaN device based on in-situ passivation and oxidation process and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111463129A true CN111463129A (en) | 2020-07-28 |
| CN111463129B CN111463129B (en) | 2020-09-22 |
Family
ID=71683983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010556931.5A Active CN111463129B (en) | 2020-06-18 | 2020-06-18 | GaN device based on in-situ passivation and oxidation process and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111463129B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0975013A2 (en) * | 1998-07-24 | 2000-01-26 | Lucent Technologies Inc. | Method of manufacturing an oxide layer on a GaAs-based semiconductor body |
| US20150200286A1 (en) * | 2014-01-15 | 2015-07-16 | The Regents Of The University Of California | Metalorganic chemical vapor deposition of oxide dielectrics on n-polar iii-nitride semiconductors with high interface quality and tunable fixed interface charge |
| CN105655395A (en) * | 2015-01-27 | 2016-06-08 | 苏州捷芯威半导体有限公司 | Enhanced high electronic mobility transistor and manufacturing method thereof |
-
2020
- 2020-06-18 CN CN202010556931.5A patent/CN111463129B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0975013A2 (en) * | 1998-07-24 | 2000-01-26 | Lucent Technologies Inc. | Method of manufacturing an oxide layer on a GaAs-based semiconductor body |
| US20150200286A1 (en) * | 2014-01-15 | 2015-07-16 | The Regents Of The University Of California | Metalorganic chemical vapor deposition of oxide dielectrics on n-polar iii-nitride semiconductors with high interface quality and tunable fixed interface charge |
| CN105655395A (en) * | 2015-01-27 | 2016-06-08 | 苏州捷芯威半导体有限公司 | Enhanced high electronic mobility transistor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111463129B (en) | 2020-09-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7178121B2 (en) | Semiconductor device manufacturing method and use thereof | |
| TWI310990B (en) | Quantum well transistor using high dielectric constant dielectric layer | |
| Chung et al. | N-face GaN/AlGaN HEMTs fabricated through layer transfer technology | |
| JP6304899B2 (en) | III-N semiconductor device grown on a silicon substrate with a rare earth oxide gate dielectric | |
| JP2016139781A (en) | Enhancement high electron mobility transistor and method of manufacturing the same | |
| JP2013012735A (en) | Cmos compatible method for manufacturing hemt device and hemt device thereof | |
| CN104201104A (en) | Manufacturing method for gallium nitride-based enhanced device | |
| US6696306B2 (en) | Methods of fabricating layered structure and semiconductor device | |
| CN111834435A (en) | High electron mobility transistor | |
| CN114899227A (en) | Enhanced gallium nitride-based transistor and preparation method thereof | |
| WO2023045046A1 (en) | Gold-free ohmic contact electrode, semiconductor device, and radio-frequency device and manufacturing method therefor | |
| CN111430239B (en) | GaN device based on surface treatment and oxidation process and preparation method thereof | |
| KR100969608B1 (en) | The method for reducing a leakage current of the nitride compound semiconductor device | |
| CN117711940A (en) | Enhanced HEMT device structure and manufacturing method thereof | |
| CN111463129B (en) | GaN device based on in-situ passivation and oxidation process and preparation method thereof | |
| CN111430228A (en) | Preparation method of dielectric film with ultrahigh dielectric constant | |
| CN116092935A (en) | Manufacturing method of AlGaN/GaN HEMT device | |
| CN106571387A (en) | High K material-based stacked-gate AlGaN/GaN high-electron mobility MOS device | |
| CN112713188B (en) | GaN-based enhanced MIS-HEMT device and preparation method thereof | |
| CN113921617A (en) | Ga2O3Metal oxide semiconductor field effect transistor and preparation method thereof | |
| CN108695156B (en) | Method for improving III-nitride MIS-HEMT ohmic contact and MIS-HEMT device | |
| CN113921613B (en) | High voltage Ga of floating gate 2 O 3 Metal oxide semiconductor field effect transistor and preparation method thereof | |
| CN108417488B (en) | Composite insulation structure, transistor and manufacturing method of composite insulation structure and transistor | |
| CN111223927B (en) | GaN-diamond-Si semiconductor structure, device and preparation method | |
| CN112133757B (en) | Gate-controlled gallium oxide field effect transistor based on p-i-n structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |