CN111446223A - Data line protector - Google Patents
Data line protector Download PDFInfo
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- CN111446223A CN111446223A CN201910043927.6A CN201910043927A CN111446223A CN 111446223 A CN111446223 A CN 111446223A CN 201910043927 A CN201910043927 A CN 201910043927A CN 111446223 A CN111446223 A CN 111446223A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/66—Structural association with built-in electrical component
- H01R13/665—Structural association with built-in electrical component with built-in electronic circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a data line protector, comprising: the lead frame is provided with a chip substrate, an IC chip external port and an MOS chip external port; the MOS chip is fixed on the upper surface of the chip substrate and is provided with a first external bonding pad and an IC chip connecting bonding pad; the data line protection IC chip is fixed on the upper surface of the MOS chip and is provided with a second external bonding pad and an MOS chip connecting bonding pad; the external port of the IC chip is connected with the second external bonding pad, the external port of the MOS chip is connected with the first external bonding pad, and the IC chip connecting bonding pad is connected with the MOS chip connecting bonding pad. The data line protector integrates overcurrent, short circuit and overtemperature protection, has small volume, small internal resistance, high current conduction, high precision, low power consumption, low temperature rise, high reaction speed, stability and reliability, is vibration-proof, impact-resistant, damp-proof, pressure-resistant, ageing-resistant, high-low temperature-resistant, is not easily influenced by the environment, can be self-recovered after protection, has long quality guarantee period and long service life of device action times, and saves the production cost.
Description
Technical Field
The invention belongs to the field of semiconductor integrated packaging, and particularly relates to a data line protector.
Background
In the current big data era, smart phones, smart home appliances and intelligent threading are the development directions in the present and future, and the existing data line protection devices are greatly limited in the application field.
At present, no data line protection device integrating overcurrent and overtemperature protection is available. Known protection devices applied to data line protection mainly include PTC and Breaker. The PTC is a high-molecular heat-sensitive material, is greatly influenced by the environmental temperature, is slow in protection action time, is increased due to the change of internal resistance after multiple actions, is heated in a keeping state after the actions, has large leakage current, and generally keeps the action power at about 1.2W, thereby causing certain influence on the service life of a data line plug, and when the environmental temperature is higher, the keeping current of the PTC is reduced, and if the PTC is extruded by external force, the PTC cannot normally play a role in protection, so that the stability is reduced; breaker is a mechanical micro switch, and its is bulky, and it is afraid of powerful vibration in use, can not receive external force extrusion, and the through current is more than ten times when high temperature when the environment is at low temperature, can only play the guard action under high temperature environment, and the electric current and the difference in temperature of action are very big under high low temperature change environment, and stability is poor.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a data line protector, which integrates overcurrent and overtemperature protection, has a small size, small internal resistance, high current, high precision, low power consumption, low temperature rise, fast response speed, stability, reliability, vibration resistance, impact resistance, moisture resistance, pressure resistance, aging resistance, high and low temperature resistance, is not easily affected by the environment, can be self-recovered after protection, has a long shelf life, has a long device operation frequency life, and saves production cost.
To achieve the above and other related objects, the present invention provides a data line protector, comprising:
the lead frame is provided with a chip substrate, an IC chip external port and an MOS chip external port;
the MOS chip is fixed on the upper surface of the chip substrate and is provided with a first external bonding pad and an IC chip connecting bonding pad;
the data line protection IC chip is fixed on the upper surface of the MOS chip and is provided with a second external bonding pad and an MOS chip connecting bonding pad;
the IC chip external port is connected with the second external bonding pad, the MOS chip external port is connected with the first external bonding pad, and the IC chip connecting bonding pad is connected with the MOS chip connecting bonding pad.
Optionally, the MOS chip includes a dual MOS chip.
Optionally, the kind of the dual MOS chip includes a dual NMOS chip.
Optionally, the IC chip external port includes a negative electrode external port and an external control protection port, and the MOS chip external port includes a first source electrode external port and a second source electrode external port.
Optionally, the first source external port and the second source external port include at least one port connected to the outside.
Optionally, the first source external port and the negative external port are located on the left side of the chip substrate, and the second source external port and the external control protection port are located on the right side of the chip substrate.
Optionally, the first external connection pad includes a first source terminal pad and a second source terminal pad, and the IC chip connection pad includes: a third source terminal pad, a fourth source terminal pad, a first gate terminal pad, a second gate terminal pad, a first drain terminal pad.
Optionally, the first source terminal pad is located in a left region of the MOS chip, and the second source terminal pad is located in a right region of the MOS chip.
Optionally, the second external pad includes a negative terminal pad and an external control protection terminal pad, and the MOS chip connection pad includes: a third gate terminal pad, a fourth gate terminal pad, a first input terminal pad, a second drain terminal pad.
Optionally, the negative terminal pad is located in a left region of the data line protection IC chip.
Optionally, the negative terminal pad is connected to the negative external port, the first input terminal pad is connected to the third source terminal pad, the third gate terminal pad is connected to the first gate terminal pad, the fourth gate terminal pad is connected to the second gate terminal pad, the second input terminal pad is connected to the fourth source terminal pad, the second drain terminal pad is connected to the first drain terminal pad, and the external control protection terminal pad is connected to the external control protection port.
Optionally, the negative terminal pad is connected to the negative external port through a wire, the first input terminal pad is connected to the third source terminal pad through a wire, the third gate terminal pad is connected to the first gate terminal pad through a wire, the fourth gate terminal pad is connected to the second gate terminal pad through a wire, the second input terminal pad is connected to the fourth source terminal pad through a wire, the second drain terminal pad is connected to the first drain terminal pad through a wire, and the external control protection terminal pad is connected to the external control protection port through a wire.
Optionally, the first source terminal pad is connected to the first source external port, and the second source terminal pad is connected to the second source external port.
Optionally, the first source terminal pad and the first source external port are connected through a first metal strip, and the second source terminal pad and the second source external port are connected through a second metal strip.
Optionally, the species of the first metal strip and the second metal strip comprises a copper strip.
Optionally, the first metal strap and the second metal strap include a vertical portion and a horizontal portion, the vertical portion is connected to and integrally formed with the horizontal portion, the horizontal portion of the first metal strap is fixed to the first source terminal pad, the vertical portion of the first metal strap is fixed to the first source external port, the horizontal portion of the second metal strap is fixed to the second source terminal pad, and the vertical portion of the second metal strap is fixed to the second source external port.
Optionally, the horizontal portion of the first metal strap is fixed to the first source terminal pad by solder, the vertical portion of the first metal strap is fixed to the first source external port by solder, the horizontal portion of the second metal strap is fixed to the second source terminal pad by solder, and the vertical portion of the second metal strap is fixed to the second source external port by solder.
Optionally, the MOS chip is fixed to the upper surface of the chip substrate by solder.
Optionally, the data line protection IC chip is fixed to the upper surface of the MOS chip by an insulating and heat-insulating adhesive.
Optionally, the data line protector further comprises a quad flat non-leaded package structure.
As described above, the present invention provides a data line protector, which has the following effects:
the data line protector integrates overcurrent, short circuit and overtemperature protection, has small volume, small internal resistance, high current conduction, high precision, low power consumption, low temperature rise, high reaction speed, stability and reliability, is vibration-proof, impact-resistant, damp-proof, pressure-resistant, ageing-resistant, high-low temperature-resistant, is not easily influenced by the environment, can be self-recovered after protection, has long quality guarantee period and long service life of device action times, and saves the production cost.
Furthermore, the first source terminal bonding pad is connected with the first source external port through a first metal strip, and the second source terminal bonding pad is connected with the second source external port through a second metal strip, so that the large flow is ensured to pass through.
The data line protection IC chip is fixed in the upper surface of MOS chip makes the device volume reduce 50%, and the metal wire shortens and has reduced the line loss, and the volume reduces and has reduced the encapsulation cost, has improved stability and interference killing feature simultaneously.
Drawings
Fig. 1 is a schematic top view of the data line protector according to the present invention.
Fig. 2 is a schematic view of a data line protector according to the present invention.
Description of the element reference numerals
101 MOS chip
102 first drain terminal pad
103 first source terminal pad
104 second source terminal pad
105 third source terminal pad
106 fourth source terminal pad
107 first gate terminal pad
108 second gate terminal pad
109 chip substrate
110 negative pole external connection port
111 external control protection port
112 first source external connection port
113 second source external connection port
114 first metal strip
115 second metal strip
116 insulating and heat-insulating glue
117-121 solder
122 data line protection IC chip
123 first input terminal pad
124 third gate terminal pad
125 fourth gate terminal pad
126 second input terminal pad
127 negative terminal pad
128 second drain terminal pad
129 external control protection terminal bonding pad
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
As shown in fig. 1 to 2, the present embodiment provides a data line protector, including: a lead frame, a MOS chip 101, a data line protection IC chip 122, a wire, and a metal tape.
The lead frame has a chip substrate 109, an IC chip external port, and a MOS chip external port.
And port substrates are arranged on the lower surfaces of the external port of the IC chip and the external port of the MOS chip.
The kind of the chip substrate 109 and the port substrate includes a copper substrate.
The external ports of the IC chip comprise a negative external port 110 and an external control protection port 111, and the external ports of the MOS chip comprise a first source external port 112 and a second source external port 113.
The external negative port 110 is connected to a negative electrode, the external first source port 112 and the external second source port 113 are connected to a positive power supply of an external data line or a positive data line plug, so as to transmit power, and the external control protection port 111 is used for inputting a low potential turn-off control circuit from the outside.
The first source external port 112 and the second source external port 113 include at least 1 port connected to the outside.
In this embodiment, the first source external port 112 and the second source external port 113 have 3 ports connected to the outside.
The first source external port 112 and the negative external port 110 are located on the left side of the chip substrate 109, and the second source external port 113 and the external control protection port 111 are located on the right side of the chip substrate 109.
The MOS chip 101 is fixed to the upper surface of the chip substrate 109, and the MOS chip 101 has a first external bonding pad and an IC chip bonding pad.
The MOS chip 101 is fixed to the upper surface of the chip substrate 109 by solder.
As an example, the MOS chip 101 includes a dual MOS chip. The kind of the double MOS chip comprises a double NMOS chip.
In this embodiment, the MOS chip 101 is a dual NMOS chip.
The first external connection pad includes a first source terminal pad 103 and a second source terminal pad 104, and the IC chip connection pad includes: a third source terminal pad 105, a fourth source terminal pad 106, a first gate terminal pad 107, a second gate terminal pad 108, a first drain terminal pad 102.
The first source terminal bonding pad 103, the second source terminal bonding pad 104, the third source terminal bonding pad 105, and the fourth source terminal bonding pad 106 are connected to the source of the MOS chip 101, the first gate terminal bonding pad 107 and the second gate terminal bonding pad 108 are connected to the gate of the MOS chip 101, and the first drain terminal bonding pad 102 is connected to the drain of the MOS chip 101.
The first source terminal pad 103 is located in a left region of the MOS chip 101, and the second source terminal pad 104 is located in a right region of the MOS chip 101.
The data line protection IC chip 122 is fixed to the upper surface of the MOS chip 101, and the data line protection IC chip 122 has a second external pad and a connection pad of the MOS chip 101.
The data line protection IC chip 122 is fixed to the upper surface of the MOS chip 101 by an insulating adhesive 116.
The second external bonding pad comprises a negative terminal bonding pad 127 and an external control protection terminal bonding pad 129, and the MOS chip 101 connection bonding pad comprises: a third gate terminal pad 124, a fourth gate terminal pad 125, a first input terminal pad 123, a second input terminal pad 126, a second drain terminal pad 128. The negative terminal pad 127 is located at a left region of the data line protection IC chip 122.
The data line protection IC chip 122 is fixed to the upper surface of the MOS chip 101, so that the device size is reduced by 50%, the wire loss is reduced by shortening the metal line, the packaging cost is reduced by reducing the size, and the stability and the anti-interference capability are improved.
The IC chip external port is connected with the second external bonding pad, the MOS chip external port is connected with the first external bonding pad, and the IC chip connecting bonding pad is connected with the MOS chip 101 connecting bonding pad.
The negative terminal pad 127 is connected to the negative external port 110, the first input terminal pad 123 is connected to the third source terminal pad 105, the third gate terminal pad 124 is connected to the first gate terminal pad 107, the fourth gate terminal pad 125 is connected to the second gate terminal pad 108, the second input terminal pad 126 is connected to the fourth source terminal pad 106, the second drain terminal pad 128 is connected to the first drain terminal pad 102, and the external control protection terminal pad 129 is connected to the external control protection port 111.
The negative terminal pad 127 is connected with the negative external port 110 through a metal wire, the first input terminal pad 123 is connected with the third source terminal pad 105 through a metal wire, the third gate terminal pad 124 is connected with the first gate terminal pad 107 through a metal wire, the fourth gate terminal pad 125 is connected with the second gate terminal pad 108 through a metal wire, the second input terminal pad 126 is connected with the fourth source terminal pad 106 through a metal wire, the second drain terminal pad 128 is connected with the first drain terminal pad 102 through a metal wire, and the external control protection terminal pad 129 is connected with the external control protection port 111 through a metal wire.
The first source terminal pad 103 is connected to the first source external port 112, and the second source terminal pad 104 is connected to the second source external port 113. The first source terminal pad 103 and the first source external port 112 are connected by a first metal strap 114, and the second source terminal pad 104 and the second source external port 113 are connected by a second metal strap 115. The species of the first metal strip 114 and the second metal strip 115 comprise copper strips.
The first source terminal pad 103 is connected to the first source external port 112 through a first metal strap 114, the second source terminal pad 104 is connected to the second source external port 113 through a second metal strap 115, and the first metal strap 114 and the second metal strap 115 have larger cross-sectional areas, so that the resistance value is effectively reduced, and a large flow can be realized.
The first metal strap 114 and the second metal strap 115 include a vertical portion and a horizontal portion, the vertical portion is connected with the horizontal portion and integrally formed, the horizontal portion of the first metal strap 114 is fixed to the first source terminal pad 103, the vertical portion of the first metal strap 114 is fixed to the first source external port 112, the horizontal portion of the second metal strap 115 is fixed to the second source terminal pad 104, and the vertical portion of the second metal strap 115 is fixed to the second source external port 113.
The horizontal portion of the first metal strap 114 is fixed to the first source terminal pad 103 by solder 119, the vertical portion of the first metal strap 114 is fixed to the first source external port 112 by solder 117, the horizontal portion of the second metal strap 115 is fixed to the second source terminal pad 104 by solder 120, and the vertical portion of the second metal strap 115 is fixed to the second source external port 113 by solder 118.
The data line protector further comprises a square flat pin-free packaging structure.
In summary, the present invention provides a data line protector, which has the following functions: the data line protector integrates overcurrent, short circuit and overtemperature protection, has small volume, small internal resistance, high current conduction, high precision, low power consumption, low temperature rise, high reaction speed, stability and reliability, is vibration-proof, impact-resistant, damp-proof, pressure-resistant, ageing-resistant, high-low temperature-resistant, is not easily influenced by the environment, can be self-recovered after protection, has long quality guarantee period and long service life of device action times, and saves the production cost. Further, the first source terminal pad 103 and the first source external port 112 are connected by a first metal strap 114, and the second source terminal pad 104 and the second source external port 113 are connected by a second metal strap 115, so as to ensure a large flow rate. The data line protection IC chip 122 is fixed to the upper surface of the MOS chip 101, so that the device size is reduced by 50%, the wire loss is reduced by shortening the metal line, the packaging cost is reduced by reducing the size, and the stability and the anti-interference capability are improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (20)
1. A data line protector, comprising:
the lead frame is provided with a chip substrate, an IC chip external port and an MOS chip external port;
the MOS chip is fixed on the upper surface of the chip substrate and is provided with a first external bonding pad and an IC chip connecting bonding pad;
the data line protection IC chip is fixed on the upper surface of the MOS chip and is provided with a second external bonding pad and an MOS chip connecting bonding pad;
the IC chip external port is connected with the second external bonding pad, the MOS chip external port is connected with the first external bonding pad, and the IC chip connecting bonding pad is connected with the MOS chip connecting bonding pad.
2. The data line protector of claim 1, wherein: the MOS chip comprises a double MOS chip.
3. The data line protector of claim 2, wherein: the kind of the double MOS chip comprises a double NMOS chip.
4. The data line protector of claim 2, wherein: the external port of the IC chip comprises a negative electrode external port and an external control protection port, and the external port of the MOS chip comprises a first source electrode external port and a second source electrode external port.
5. The data line protector of claim 4, wherein: the first source external port and the second source external port comprise at least one port connected with the outside.
6. The data line protector of claim 4, wherein: the first source electrode external port and the negative electrode external port are located on the left side of the chip substrate, and the second source electrode external port and the external control protection port are located on the right side of the chip substrate.
7. The data line protector of claim 4, wherein: the first external connection pad includes a first source terminal pad and a second source terminal pad, and the IC chip connection pad includes: a third source terminal pad, a fourth source terminal pad, a first gate terminal pad, a second gate terminal pad, a first drain terminal pad.
8. The data line protector of claim 7, wherein: the first source terminal bonding pad is located in the left side area of the MOS chip, and the second source terminal bonding pad is located in the right side area of the MOS chip.
9. The data line protector of claim 7, wherein: the second external bonding pad comprises a negative terminal bonding pad and an external control protection terminal bonding pad, and the MOS chip connecting bonding pad comprises: a third gate terminal pad, a fourth gate terminal pad, a first input terminal pad, a second drain terminal pad.
10. The data line protector of claim 9, wherein: the negative terminal pad is located in a left region of the data line protection IC chip.
11. The data line protector of claim 9, wherein: the negative terminal pad is connected with the negative external port, the first input terminal pad is connected with the third source terminal pad, the third gate terminal pad is connected with the first gate terminal pad, the fourth gate terminal pad is connected with the second gate terminal pad, the second input terminal pad is connected with the fourth source terminal pad, the second drain terminal pad is connected with the first drain terminal pad, and the external control protection terminal pad is connected with the external control protection port.
12. The data line protector of claim 11, wherein: the negative terminal pad is connected with the negative external port through a metal wire, the first input terminal pad is connected with the third source terminal pad through a metal wire, the third gate terminal pad is connected with the first gate terminal pad through a metal wire, the fourth gate terminal pad is connected with the second gate terminal pad through a metal wire, the second input terminal pad is connected with the fourth source terminal pad through a metal wire, the second drain terminal pad is connected with the first drain terminal pad through a metal wire, and the external control protection terminal pad is connected with the external control protection port through a metal wire.
13. The data line protector of claim 9, wherein: the first source terminal bonding pad is connected with the first source external port, and the second source terminal bonding pad is connected with the second source external port.
14. The data line protector of claim 13, wherein: the first source terminal bonding pad is connected with the first source external port through a first metal strip, and the second source terminal bonding pad is connected with the second source external port through a second metal strip.
15. The data line protector of claim 14, wherein: the species of the first metal strip and the second metal strip comprise copper strips.
16. The data line protector of claim 14, wherein: the first metal strap and the second metal strap comprise a vertical part and a horizontal part, the vertical part is connected with the horizontal part and is integrally formed, the horizontal part end of the first metal strap is fixed on the first source terminal bonding pad, the vertical part end of the first metal strap is fixed on the first source external port, the horizontal part end of the second metal strap is fixed on the second source terminal bonding pad, and the vertical part end of the second metal strap is fixed on the second source external port.
17. The data line protector of claim 16, wherein: the horizontal portion end of the first metal strip is fixed to the first source terminal bonding pad through soldering tin, the vertical portion end of the first metal strip is fixed to the first source external connection port through soldering tin, the horizontal portion end of the second metal strip is fixed to the second source terminal bonding pad through soldering tin, and the vertical portion end of the second metal strip is fixed to the second source external connection port through soldering tin.
18. The data line protector of claim 1, wherein: the MOS chip is fixed on the upper surface of the chip substrate through soldering tin.
19. The data line protector of claim 1, wherein: the data line protection IC chip is fixed on the upper surface of the MOS chip through insulating and heat-insulating glue.
20. The data line protector of claim 1, wherein: the data line protector further comprises a square flat pin-free packaging structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910043927.6A CN111446223A (en) | 2019-01-17 | 2019-01-17 | Data line protector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910043927.6A CN111446223A (en) | 2019-01-17 | 2019-01-17 | Data line protector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111446223A true CN111446223A (en) | 2020-07-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910043927.6A Pending CN111446223A (en) | 2019-01-17 | 2019-01-17 | Data line protector |
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| Country | Link |
|---|---|
| CN (1) | CN111446223A (en) |
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| US5596474A (en) * | 1994-09-28 | 1997-01-21 | Nittetsu Semiconductor Co., Ltd. | Power protection circuitry for a semiconductor integrated circuit |
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| US20110090605A1 (en) * | 2000-06-22 | 2011-04-21 | Renesas Technology Corp. | Semiconductor integrated circuit |
| US20110108998A1 (en) * | 2005-01-05 | 2011-05-12 | Alpha & Omega Semiconductor Incorporated | Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package |
| CN203859110U (en) * | 2013-02-28 | 2014-10-01 | 半导体元件工业有限责任公司 | Double marker plate heap type pipe core packaging part and semiconductor packaging part |
| CN107768368A (en) * | 2016-08-23 | 2018-03-06 | 万国半导体(开曼)股份有限公司 | The ESD protections of USB c-type on-load switches |
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2019
- 2019-01-17 CN CN201910043927.6A patent/CN111446223A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596474A (en) * | 1994-09-28 | 1997-01-21 | Nittetsu Semiconductor Co., Ltd. | Power protection circuitry for a semiconductor integrated circuit |
| US20110090605A1 (en) * | 2000-06-22 | 2011-04-21 | Renesas Technology Corp. | Semiconductor integrated circuit |
| US20110108998A1 (en) * | 2005-01-05 | 2011-05-12 | Alpha & Omega Semiconductor Incorporated | Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package |
| CN101663749A (en) * | 2007-11-21 | 2010-03-03 | 万国半导体股份有限公司 | Stacked-die package for battery power management |
| CN203859110U (en) * | 2013-02-28 | 2014-10-01 | 半导体元件工业有限责任公司 | Double marker plate heap type pipe core packaging part and semiconductor packaging part |
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Application publication date: 20200724 |