CN111445875A - Pixel data signal configuration system and display panel - Google Patents
Pixel data signal configuration system and display panel Download PDFInfo
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- CN111445875A CN111445875A CN202010322822.7A CN202010322822A CN111445875A CN 111445875 A CN111445875 A CN 111445875A CN 202010322822 A CN202010322822 A CN 202010322822A CN 111445875 A CN111445875 A CN 111445875A
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- 125000004122 cyclic group Chemical group 0.000 claims abstract description 41
- 230000001360 synchronised effect Effects 0.000 claims abstract description 10
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000012937 correction Methods 0.000 claims description 6
- 239000004973 liquid crystal related substance Substances 0.000 claims description 6
- 238000004891 communication Methods 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 abstract description 11
- 230000005540 biological transmission Effects 0.000 abstract description 11
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- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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Abstract
The application discloses a pixel data signal configuration system, which comprises a source driver and a time schedule controller; the time schedule controller can obtain the first configuration data in the source driver through the synchronous serial bus, generate and compare corresponding cyclic redundancy codes according to the configuration data before and after transmission, can correct the first configuration data, avoid the source driver from outputting wrong data signals, solve the problem of abnormal picture display, and further improve the display reliability.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a pixel data signal configuration system and a display panel.
Background
The liquid crystal display panel makes liquid crystal molecules form different angles of rotation by a driving voltage output by a Source Driver IC, and displays different pictures by matching with other optical components, and the configuration parameters required to be matched by the Source Driver IC in different display panels are different, and the configuration parameters may include the number of output channels, PO L (Polarity) inversion mode, horizontal display Polarity mode, transmission direction, TP (latch signal) width, and the like, which are important design parameters for picture display, and after being determined as optimal parameter DATA through a large number of debugging verifications in the design stage, the configuration parameters are included in DATA (DATA) signals by a PCBA (Printed Circuit Board) peripheral Circuit, and are sent to the Source Driver by a Timing Controller (TCON) to set the configuration DATA of the Source Driver, so as to match the requirements of the liquid crystal panel.
With the increasing demand of people for display effect, the resolution and refresh rate of display panels are also increasing, and the required data transmission frequency is also increasing, and the industry gradually adopts the P2P (point to point) protocol to meet the transmission demand of high-specification panels. Configuration parameters of the Source Driver IC are contained in data signals transmitted based on the P2P protocol, and are set by the TCON output to the Source Driver IC based on the agreed P2P protocol. However, on the transmission path, these configuration parameters are often subjected to abnormal interference or abnormal signal input from the outside, so that there may be a case where the configuration parameters used in storage in the source driver and the configuration parameters output in the timing controller are inconsistent. These inconsistencies may cause errors in the data signals output by the source driver, which may cause abnormal display of the image.
Disclosure of Invention
The application provides a pixel data signal configuration system, which solves the problem that in the process of transmitting configuration parameters to a source driver by a time schedule controller, the configuration parameters are changed due to interference, so that data signals output by the source driver are wrong, and further, abnormal picture display is caused.
In a first aspect, the present application provides a pixel data signal configuration system, which includes a source driver and a timing controller; the source driver is used for outputting a corresponding data signal according to image data containing first configuration data so as to drive the display panel to display images; and a timing controller connected to the source driver, for transmitting image data including second configuration data to the source driver through a point-to-point communication line, and acquiring first configuration data in the source driver through a synchronous serial bus; the time schedule controller generates and compares corresponding first cyclic redundancy codes and second cyclic redundancy codes according to the first configuration data and the second configuration data; when the first cyclic redundancy code is inconsistent with the second cyclic redundancy code, the timing controller retransmits the second configuration data to the source driver to correct the first configuration data in the source driver.
Based on the first aspect, in a first implementation manner of the first aspect, the timing controller includes an obtaining module, a generating module, a comparing module, and a timing control module; the acquisition module is connected with the source driver and used for acquiring first configuration data through a synchronous serial bus; the generating module is connected with the obtaining module and used for generating a first cyclic redundancy code and a second cyclic redundancy code according to the first configuration data and the second configuration data; the comparison module is connected with the generation module and used for checking whether the first cyclic redundancy code is consistent with the second cyclic redundancy code or not and outputting a corresponding correction instruction when the first cyclic redundancy code is inconsistent with the second cyclic redundancy code; and the time sequence control module is connected with the generation module and the comparison module and used for retransmitting the second configuration data to the source driver according to the correction instruction.
In a second implementation form of the first aspect, based on the first implementation form of the first aspect, the source driver includes a plurality of sequentially numbered source driving subunits; the source driving subunit is connected with the time sequence control module and the acquisition module; the time sequence control module respectively and simultaneously transmits second configuration data to the source driving subunit; the acquisition module acquires the first configuration data in time sharing and sequence according to the serial numbers.
Based on the second implementation manner of the first aspect, in a third implementation manner of the first aspect, the source driving subunit includes a receiving module, a logic control module, a shift register module, a data latch module, a digital-to-analog conversion module, and an output buffer; the receiving module is connected with the time sequence control module and used for generating corresponding first configuration data, clock signals and data latching signals according to the received image data; the logic control module is connected with the receiving module and the obtaining module and used for storing and generating a corresponding logic control signal according to the first configuration data; the shift register module is connected with the receiving module and the logic control module and is used for generating a plurality of shift signals which are arranged in sequence according to the clock signal and the logic control signal; the data latch module is connected with the receiving module and the shift register module and used for temporarily storing the shift signal according to the data latch signal; the digital-to-analog conversion module is connected with the data latch module and is used for converting the shift signal into a corresponding analog voltage signal according to the gray scale signal; and the output buffer is connected with the digital-to-analog conversion module and used for outputting corresponding data signals according to the analog voltage signals.
In a fourth implementation form of the first aspect, in the first implementation form of the first aspect, the timing controller further comprises a timing controller; the timing controller is connected with the acquisition module and the time sequence control module and is used for controlling the acquisition module to acquire the first configuration data at N-frame time intervals.
In a fifth implementation form of the first aspect, based on the third implementation form of the first aspect, the logic control module comprises a register for storing the first configuration data; the register is connected with the acquisition module.
In a sixth implementation form of the first aspect, based on the fourth implementation form of the first aspect, the N-frame time interval is a positive integer frame time not less than 1.
Based on any one of the embodiments described above, in a seventh embodiment of the first aspect, the timing controller does not perform the retransmission operation when the first cyclic redundancy code and the second cyclic redundancy code coincide.
In a second aspect, the present application provides a display panel comprising the pixel data signal configuration system of any of the above embodiments.
In a first embodiment of the second aspect, the display panel is a liquid crystal display panel.
According to the pixel data signal configuration system, the time schedule controller can acquire the first configuration data in the source driver through the synchronous serial bus, and generates and compares the corresponding cyclic redundancy codes according to the configuration data before and after transmission, so that the first configuration data can be corrected, the source driver is prevented from outputting wrong data signals, the problem of abnormal picture display is solved, and the display reliability is improved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a pixel data signal configuration system according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of the timing controller shown in fig. 1.
Fig. 3 is a schematic structural diagram of the source driver shown in fig. 1.
Fig. 4 is a schematic structural diagram of the source driving subunit shown in fig. 3.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1, the present embodiment provides a pixel data signal configuration system, which includes a source driver 20 and a timing controller 10; the timing controller 10 transmits image data, which includes configuration data called second configuration data in the timing controller 10, to the source driver 20 through the point-to-point communication line P2P, the configuration data is output from the timing controller 10, transmitted to the source driver 20 through the point-to-point communication line P2P, and stored in the source driver 20, called first configuration data, and at this time, the first configuration data is transmitted and stored, which may be interfered, causing the first configuration data to be inconsistent with the second configuration data, and causing abnormal screen display if the source driver 20 outputs a corresponding digital signal to drive the display panel for image display with the first configuration data. In view of this, the timing controller 10 in this embodiment forms another transmission channel with the source driver 20 through the synchronous serial bus I2C, the timing controller 10 can obtain the first configuration data in the source driver 20 through the transmission channel, the timing controller 10 generates the corresponding first and second cyclic redundancy codes according to the obtained first and second configuration data, and compares the first and second cyclic redundancy codes, when the first and second cyclic redundancy codes are not consistent, it indicates that the second configuration data is interfered or damaged in the transmission and/or storage process, the first configuration data will cause the output of the wrong data signal, and thus cause the display to be abnormal, in order to avoid this, the timing controller 10 will retransmit the second configuration data to the source driver 20, to correct the first configuration data in the source driver 20. This can prevent the source driver 20 from outputting an erroneous data signal, and solve the problem of abnormal picture display, thereby improving display reliability.
It should be noted that the image data may be transmitted, but not limited to, once per frame time.
As shown in fig. 2, in one embodiment, the timing controller 10 includes an obtaining module 11, a generating module 12, a comparing module 13, and a timing control module 14; the obtaining module 11 is connected to the source driver 20 through the synchronous serial bus I2C, and can obtain the first configuration data from the source driver 20; the obtaining module 11 outputs the obtained first configuration data to the generating module 12, meanwhile, the second configuration data in the timing controller 10 is also transmitted to the generating module 12, the generating module 12 generates corresponding first and second cyclic redundancy codes according to the first and second configuration data, and outputs the first and second cyclic redundancy codes to the comparing module 13, the comparing module 13 checks the first and second cyclic redundancy codes to check whether the two are consistent, when the first and second cyclic redundancy codes are not consistent, the comparing module 13 outputs a corresponding correction instruction to the timing control module 14, and the timing control module 14 retransmits the second configuration data to the source driver 20 according to the correction instruction to correct the first configuration data in the source driver 20. It is understood that the timing control module 14 outputs the second configuration data, and the generation module 12 receives and generates the second cyclic redundancy code according to the second configuration data; the first cyclic redundancy code and the second cyclic redundancy code are cyclic redundancy codes generated based on a cyclic redundancy check algorithm.
As shown in fig. 3, in one embodiment, the source driver 20 includes a plurality of sequentially numbered source driving subunits 21; each source drive subunit 21 outputs a data signal for a corresponding column of sub-pixels; the timing control module 14 transmits the image data to each source driving subunit 21, and the timing control module 14 simultaneously transmits the second configuration data to the source driving subunits 21, respectively; the obtaining module 11 is connected to each source driving subunit 21 through the synchronous serial bus I2C, and the obtaining module 11 sequentially obtains the first configuration data in time division according to the serial numbers. It is understood that the source driving subunit 21 can be, but is not limited to, a source driving integrated circuit.
As shown in fig. 4, in one embodiment, the source driving subunit 21 includes a receiving module 211, a logic control module 212, a shift register module 213, a data latch module 214, a digital-to-analog conversion module 215, and an output buffer 216; a receiving module 211, connected to the timing control module 14, for generating corresponding first configuration data, clock signal and data latch signal according to the received image data; the logic control module 212 is connected with the receiving module 211 and the obtaining module 11, and is configured to store and generate a corresponding logic control signal according to the first configuration data; a shift register module 213, connected to the receiving module 211 and the logic control module 212, for generating a plurality of shift signals arranged in sequence according to the clock signal and the logic control signal; a data latch module 214 connected to the receiving module 211 and the shift register module 213, for temporarily storing the shift signal according to the data latch signal; a digital-to-analog conversion module 215, connected to the data latch module 214, for converting the shift signal into a corresponding analog voltage signal according to the gray scale signal; and an output buffer 216 connected to the digital-to-analog conversion module 215, for outputting a corresponding data signal according to the analog voltage signal.
In one embodiment, the timing controller 10 further comprises a timing controller; the timing controller is connected to the timing control module 14, the timing controller and the timing control module share a clock signal, the timing controller can count by taking the display time of a frame as a time unit, and when the timing requirement of the timing controller is met, the timing controller controls the acquisition module 11 to acquire the first configuration data. It can be understood that the timing requirement may be, but is not limited to, an N-frame time interval, and the N-frame time interval may be, but is not limited to, a positive integer frame time not less than 1, and may also be a 0-frame time, that is, the timing requirement is obtained in real time, so that whether the first configuration data has interference or not can be found at the first time, and the correction is performed, so as to reduce the output error of the data signal; of course, it may be 2 frames, 3 frames or even more, which may reduce the frequency of acquiring the first configuration data.
In one embodiment, the logic control module 212 includes a register for storing first configuration data; the register is connected to the acquisition module 11. It will be appreciated that the first configuration data has a fixed memory location in the register at which the retrieval module 11 can locate and retrieve data based on the addressing.
In one embodiment, when the first cyclic redundancy code and the second cyclic redundancy code are consistent, it indicates that the second configuration data is not interfered or damaged during the transmission and storage process, and is the same as the first configuration data, and does not cause an erroneous data signal output, and the timing controller 10 may not perform the operation of retransmitting the second configuration data to the source driver 20.
In one embodiment, the present application provides a display panel comprising the pixel data signal arrangement system of any of the above embodiments.
It can be understood that, in the pixel data signal configuration system provided in the present application, the timing controller 10 can obtain the first configuration data in the source driver 20 through the synchronous serial bus I2C, and generate and compare the corresponding cyclic redundancy codes according to the configuration data before and after transmission, so as to correct the first configuration data, avoid the source driver 20 outputting an erroneous data signal, solve the problem of abnormal picture display, and further improve the display reliability. However, the display panel in this embodiment includes such a pixel data signal configuration system, so the display panel in this embodiment can also avoid the source driver 20 outputting an erroneous data signal, solve the problem of abnormal picture display, and improve the display reliability.
In one embodiment, the display panel may be, but is not limited to, a liquid crystal display panel, and may also be a self-luminous display panel, such as an O L ED display panel or a L ED display panel.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The pixel data signal configuration system and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied in the present application to explain the principles and embodiments of the present application, and the description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A pixel data signal arrangement system, comprising:
the source driver is used for outputting a corresponding data signal according to image data containing first configuration data so as to drive the display panel to display images; and
a timing controller connected to the source driver, for transmitting the image data including second configuration data to the source driver through a point-to-point communication line, and acquiring the first configuration data in the source driver through a synchronous serial bus;
the time schedule controller generates and compares corresponding first cyclic redundancy codes and second cyclic redundancy codes according to the first configuration data and the second configuration data; when the first cyclic redundancy code is inconsistent with the second cyclic redundancy code, the timing controller retransmits the second configuration data to the source driver to correct the first configuration data in the source driver.
2. The pixel data signal configuration system according to claim 1, wherein the timing controller comprises:
the acquisition module is connected with the source driver and used for acquiring the first configuration data through a synchronous serial bus;
a generating module, connected to the obtaining module, configured to generate the first cyclic redundancy code and the second cyclic redundancy code according to the first configuration data and the second configuration data;
the comparison module is connected with the generation module and used for checking whether the first cyclic redundancy code is consistent with the second cyclic redundancy code or not and outputting a corresponding correction instruction when the first cyclic redundancy code is inconsistent with the second cyclic redundancy code; and
and the time sequence control module is connected with the generating module and the comparing module and is used for retransmitting the second configuration data to the source driver according to the correcting instruction.
3. The pixel-data signal configuration system of claim 2, wherein the source driver comprises a plurality of sequentially numbered source drive subunits; the source driving subunit is connected with the time sequence control module and the acquisition module; the time sequence control module respectively and simultaneously transmits the second configuration data to the source driving subunit; the acquisition module acquires the first configuration data in time-sharing sequence according to the serial numbers.
4. The pixel-data signal configuration system of claim 3, wherein the source driving subunit comprises:
the receiving module is connected with the time sequence control module and used for generating corresponding first configuration data, clock signals and data latching signals according to the received image data;
the logic control module is connected with the receiving module and the acquiring module and used for storing and generating a corresponding logic control signal according to the first configuration data;
the shift register module is connected with the receiving module and the logic control module and is used for generating a plurality of shift signals which are arranged in sequence according to the clock signal and the logic control signal;
the data latch module is connected with the receiving module and the shift register module and used for temporarily storing the shift signal according to the data latch signal;
the digital-to-analog conversion module is connected with the data latch module and used for converting the shift signal into a corresponding analog voltage signal according to the gray scale signal; and
and the output buffer is connected with the digital-to-analog conversion module and used for outputting the corresponding data signal according to the analog voltage signal.
5. The pixel data signal configuration system according to claim 2, wherein the timing controller further comprises a timing controller;
the timing controller is connected with the acquisition module and the time sequence control module and is used for controlling the acquisition module to acquire the first configuration data at N-frame time intervals.
6. The pixel-data signal configuration system of claim 4, wherein the logic control module comprises a register for storing the first configuration data; the register is connected with the acquisition module.
7. The pixel-data signal configuration system of claim 5, wherein the N-frame time interval is a positive integer frame time not less than 1.
8. The pixel-data signal arrangement system according to any one of claims 1 to 7, wherein the timing controller does not perform a retransmission operation when the first cyclic redundancy code is identical to the second cyclic redundancy code.
9. A display panel comprising the pixel data signal arrangement system according to any one of claims 1 to 8.
10. The display panel according to claim 9, wherein the display panel is a liquid crystal display panel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010322822.7A CN111445875A (en) | 2020-04-22 | 2020-04-22 | Pixel data signal configuration system and display panel |
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| CN202010322822.7A CN111445875A (en) | 2020-04-22 | 2020-04-22 | Pixel data signal configuration system and display panel |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005140900A (en) * | 2003-11-05 | 2005-06-02 | Nec Access Technica Ltd | Interfacing method of image display panel |
| CN101197114A (en) * | 2006-12-04 | 2008-06-11 | 奇景光电股份有限公司 | Method of transmitting data from timing controller to source driving device in LCD |
| CN103680374A (en) * | 2012-09-26 | 2014-03-26 | 联咏科技股份有限公司 | Panel display device |
| CN104036753A (en) * | 2013-03-05 | 2014-09-10 | 三星电子株式会社 | Display interface, method of operating same, and device including same |
| CN104464675A (en) * | 2014-10-24 | 2015-03-25 | 友达光电股份有限公司 | Power management method and power management device |
| CN106098017A (en) * | 2016-08-25 | 2016-11-09 | 深圳市华星光电技术有限公司 | A kind of driving method reducing electromagnetic interference and driving means |
| CN109036317A (en) * | 2018-09-10 | 2018-12-18 | 惠科股份有限公司 | Display device and driving method |
| US20190235950A1 (en) * | 2018-01-30 | 2019-08-01 | Japan Display Inc. | Display and display system |
-
2020
- 2020-04-22 CN CN202010322822.7A patent/CN111445875A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005140900A (en) * | 2003-11-05 | 2005-06-02 | Nec Access Technica Ltd | Interfacing method of image display panel |
| CN101197114A (en) * | 2006-12-04 | 2008-06-11 | 奇景光电股份有限公司 | Method of transmitting data from timing controller to source driving device in LCD |
| CN103680374A (en) * | 2012-09-26 | 2014-03-26 | 联咏科技股份有限公司 | Panel display device |
| CN104036753A (en) * | 2013-03-05 | 2014-09-10 | 三星电子株式会社 | Display interface, method of operating same, and device including same |
| CN104464675A (en) * | 2014-10-24 | 2015-03-25 | 友达光电股份有限公司 | Power management method and power management device |
| CN106098017A (en) * | 2016-08-25 | 2016-11-09 | 深圳市华星光电技术有限公司 | A kind of driving method reducing electromagnetic interference and driving means |
| US20190235950A1 (en) * | 2018-01-30 | 2019-08-01 | Japan Display Inc. | Display and display system |
| CN109036317A (en) * | 2018-09-10 | 2018-12-18 | 惠科股份有限公司 | Display device and driving method |
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