CN111444121A - Air cannon missile-borne acceleration data acquisition system and acquisition method - Google Patents
Air cannon missile-borne acceleration data acquisition system and acquisition method Download PDFInfo
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- CN111444121A CN111444121A CN201910040418.8A CN201910040418A CN111444121A CN 111444121 A CN111444121 A CN 111444121A CN 201910040418 A CN201910040418 A CN 201910040418A CN 111444121 A CN111444121 A CN 111444121A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention belongs to the field of missile-borne data recording, and particularly relates to an air cannon missile-borne acceleration data acquisition system and an air cannon missile-borne acceleration data acquisition method. The system comprises: the acquisition and storage module: the device is used for acquiring acceleration data of the on-missile acceleration sensor, converting the acquired acceleration data into digital signals and storing the digital signals obtained through conversion; a triggering module: the data acquisition and storage module is used for controlling the data storage; a control module: the time sequence control module is used for data transmission, acquisition and storage; a communication module: the device is used for programming programs and serial port communication; a power supply module: the voltage-reducing and voltage-stabilizing circuit is used for carrying out voltage-reducing and voltage-stabilizing operation on the input of an external power supply and providing required working voltage for other modules of the acquisition system. The invention uses the asynchronous fifo high-speed memory as the memory chip in the acquisition and storage module, meets the requirement of the analog-to-digital converter on the storage rate, can read the data after the experiment is finished, and is greatly convenient for reading the data.
Description
Technical Field
The invention belongs to the field of missile-borne data recording, and particularly relates to an air cannon missile-borne acceleration data acquisition system and an air cannon missile-borne acceleration data acquisition method.
Background
The air cannon is the most common experimental device for checking the overload resistance of the initiating explosive device. In a conventional air cannon, the magnitude of the overload acceleration peak is determined by a copper column compression method. The method has large experimental error, and the spectrogram of the overload acceleration in the bullet landing process cannot be obtained. Therefore, when the air cannon is used for testing the high overload resistance of the initiating explosive device, the acquisition of acceleration data in the target shooting process is particularly important.
The dynamic testing method of the acceleration signal in the process of the bullet landing target has various methods, and the method mainly comprises two methods, namely a lead method and a bullet loading storage testing method. The lead method is to connect the acceleration sensor to a signal conditioning instrument and a data acquisition system, and the test method has the problems of easy breakage of a signal wire, heavy instrument, long preparation time and the like. Storage testing techniques may solve the above-described problems.
Aiming at a missile-borne storage test method, the design of a cannon launching high overload signal storage test system of Zhou Rui Jing adopts an stm32 built-in analog-to-digital converter, the sampling rate of the system is 10KHz, and the requirement of a bullet target landing process on the sampling rate cannot be met. The patent of ' a missile-borne platform data acquisition and storage system and method ' applied and disclosed by Shanghai technical and physical research institute of Chinese academy of sciences ' adopts ping-pong cache technology, and the cache method is complex in operation and can be completed only by at least two memory chips. In the 'high-precision missile-borne pressure data acquisition system based on the FPGA', the Van Jun Jian takes the FPGA as a control core, and the FPGA is complex in design and expensive to process.
Disclosure of Invention
The invention aims to provide an air cannon missile-borne acceleration data acquisition system and an air cannon missile-borne acceleration data acquisition method.
The technical solution for realizing the purpose of the invention is as follows:
an air cannon missile-borne acceleration data acquisition system, the system comprising:
the acquisition and storage module: the device is used for acquiring acceleration data of the on-missile acceleration sensor, converting the acquired acceleration data into digital signals and storing the digital signals obtained through conversion;
a triggering module: the data acquisition and storage module is used for controlling the data storage;
a control module: the time sequence control module is used for data transmission, acquisition and storage;
a communication module: the device is used for programming programs and serial port communication;
a power supply module: the voltage-reducing and voltage-stabilizing circuit is used for carrying out voltage-reducing and voltage-stabilizing operation on the input of an external power supply and providing required working voltage for other modules of the acquisition system.
Furthermore, the acquisition and storage module comprises an analog-to-digital converter and a fifo high-speed memory, the analog-to-digital converter converts acquired acceleration data into digital signals, and the fifo high-speed memory is provided with an independent read-write clock input end and is used for storing the digital signals.
Further, the trigger module comprises a voltage comparator, a unidirectional thyristor and an inverter; the rear end of the voltage comparator is connected with a unidirectional thyristor, the rear end of the unidirectional thyristor is connected with an inverter, and the rear end of the inverter is connected with a fifo high-speed memory;
the unidirectional thyristor is used as a semi-controllable switch, after the unidirectional thyristor is turned on for the first time, the gate pole G port loses control function, the gate pole G is connected with the output end OUT of the voltage comparator, and when the voltage of the acceleration sensor is more than 0.2V, the unidirectional thyristor is turned on, and the output end of the unidirectional thyristor outputs high level; the inverter converts a high level to a low level.
Furthermore, the control module comprises a control chip, the back end of the fifo high-speed memory is connected with the control chip, the back end of the control chip is connected with the communication module, and the control chip is stm32 series.
Further, the control chip is a control chip STM32F103C8T6, the voltage comparator is L MH6702, the inverter is SN74AHC1G04, and the fifo high-speed memory is IDT72V 285.
Furthermore, the rear end of the communication module is connected with a computer, the communication module comprises a serial communication module, and the first function of the serial communication module is to write a program written on the computer into a control chip; the second function of the serial port communication module is to transmit the digital quantity stored in the fifo high-speed memory to the computer in a serial port communication mode.
Furthermore, the communication module further comprises a USB-to-serial port chip, the USB-to-serial port chip is connected with the control chip in a manner that a serial output port TXD of the USB-to-serial port chip (11) is connected with a PA9 port of the control chip, a serial input port RXD of the USB-to-serial port chip is connected with a PA10 port of the control chip, a DTR # port of the USB-to-serial port chip is connected with a RESET port of the control chip, and an RTS # port of the USB-to-serial port chip is connected with a BOOT0 port of the control chip.
Further, the USB to serial port chip is CH 340G.
Further, the power module comprises a voltage stabilizing chip L M7805, a voltage stabilizing chip L M117 and a voltage stabilizing chip L T1931, wherein the voltage stabilizing chip L M7805 stabilizes +9V voltage at +5V to supply power to the positive end of the analog-to-digital converter, the unidirectional thyristor and the voltage comparator, the voltage stabilizing chip L T1931 converts +5V voltage into-5V voltage to supply power to the negative end of the voltage comparator, and the voltage stabilizing chip L M117 stabilizes +5V voltage at 3.3V to supply power to the fifo high-speed memory and the control chip.
The method for acquiring the acceleration by using the system comprises the steps that in the process that an air cannon bounces on a target, data of an acceleration sensor is acquired through an analog-to-digital converter, and when the acceleration reaches a threshold value set by a trigger module, the trigger module controls a fifo high-speed memory to start to store the data acquired by the analog-to-digital converter; after the test is finished, the data in the fifo high-speed memory is read by utilizing the serial port communication function of the communication module, so that the data can be further processed.
Compared with the prior art, the invention has the following remarkable advantages:
(1) in the invention, the acquisition and storage module utilizes an asynchronous fifo high-speed memory as a storage chip, because the memory has high storage rate, the requirement of an analog-to-digital converter on the storage rate is met, and the data acquisition and storage rate of the system reaches the effect of 10 MHZ; because the memory is internally provided with the independent writing special area and the independent reading special area, the function that the read-write operation of the acceleration data in the fifo high-speed memory can be separately carried out is realized, the overload acceleration data can be stored in the target shooting process of the air cannon, the data can be read after the experiment is finished, and the data reading is greatly facilitated.
(2) The triggering mode of the invention selects hardware triggering, one path of signal of the acceleration sensor is accessed into the triggering module, and after the acceleration signal reaches the preset threshold value, the triggering module controls the asynchronous fifo high-speed memory to start data storage; the gate pole end of the thyristor in the trigger module is connected with the output end of the voltage comparator, and the phenomenon of false triggering in the working process can be prevented due to the semi-controllable performance of the thyristor.
(3) The serial port communication module selects a USB-to-serial port chip CH340G, and because the chip can replace a standard serial port by a USB interface, the problem that a notebook computer lacks a serial port is solved, and the reading and the processing of data after an experiment are greatly facilitated.
(4) The invention selects stm32 as a control chip, and the chip system has the advantages of low power consumption, small volume and low price.
The present invention is described in further detail below with reference to the attached drawing figures.
Drawings
Fig. 1 is a schematic diagram of the general structure of the missile-borne data acquisition system of the present invention.
FIG. 2 is a schematic diagram of the power module circuit of the overall missile-borne data acquisition system of the present invention.
Fig. 3 is a schematic circuit diagram of a control module of the missile-borne data acquisition system of the present invention, wherein fig. 3(a) is a main system circuit diagram of the control module, and fig. 3(b) is a power supply circuit diagram of the control module.
Fig. 4 is a schematic circuit diagram of the trigger module of the overall missile-borne data acquisition system of the present invention.
Fig. 5 is a schematic circuit diagram of the data acquisition and storage module of the overall missile-borne data acquisition system of the present invention.
Fig. 6 is a schematic circuit diagram of the communication module of the overall missile-borne data acquisition system of the present invention.
Description of reference numerals:
the USB interface comprises a 1-voltage stabilizing chip L M7805, a 2-voltage stabilizing chip L M1117, a 3-voltage stabilizing chip L T1931, a 4-control chip, a 5-control chip power supply part, a 6-voltage comparator, a 7-unidirectional thyristor, an 8-phase inverter, a 9-analog-to-digital converter, a 10-fifo high-speed memory, an 11-serial-to-USB chip and a 12-USB jack.
Detailed Description
The invention provides an air cannon missile-borne data testing system, which comprises:
the trigger module is used for controlling the fifo memory in the acquisition and storage module to store data, and comprises a voltage comparator, a thyristor and a phase inverter;
the acquisition and storage module is used for acquiring acceleration data of the on-board sensor, converting the acquired acceleration data into digital signals and storing the converted digital signals in the memory, and comprises an AD (analog-to-digital) converter and a fifo memory;
the control module is used for data transmission and timing control of the fifo high-speed memory and the AD analog-to-digital converter, and comprises a control chip stm32f103c8t 6;
and the communication module is used for programming the program and communicating with the serial port. The programming program is to program a program written on a computer into a control chip. The serial communication is to transmit the digital quantity stored in the memory to the computer by means of serial communication and to realize the programming function of the control chip. The communication module comprises a USB to serial port chip CH 340G. The serial port communication module is arranged on an independent printed circuit board, when the printed circuit board is designed, 4 ports of PA9, PA10, RESET and BOOT0 of a control chip stm32f103c8t6 are respectively connected with 4 bus bars, and 4 ports of TXD, RXD, DTR #, RTS # of a USB serial port chip CH340G are respectively connected with 4 bus bars. The USB interface of the communication module is inserted into the USB interface of the PC upper computer, and 4 pins of the communication module are inserted into 4 pins of the control system, so that the serial port communication function can be realized.
And the power supply module is used for inputting an external power supply to perform voltage reduction and stabilization operation and providing required working voltage for each module of the missile-borne data acquisition system, and comprises a voltage stabilization chip.
Fig. 1 is a system block diagram of a missile-borne data acquisition system of the present invention. The hardware device of the present invention includes: the device comprises a power module, a trigger module, a data acquisition and storage module, a communication module and a control module.
The power supply module comprises voltage stabilizing chips L M7805, L T1931 and L M117, wherein the L M7805 voltage stabilizing chip stabilizes +9V to +5V and supplies power to an analog-digital converter AD9240, a unidirectional thyristor SCR and an integrated operational amplifier L MH6702 positive terminal, the L T1931 voltage stabilizing chip converts the +5V voltage to-5V voltage and supplies power to an integrated operational amplifier L MH6702 negative terminal, and the L M117 voltage stabilizing chip stabilizes the +5V voltage to 3.3V and supplies power to a fifo high-speed memory IDT72V285 and a control chip stm32f103c8T 6.
Fig. 3 is a schematic diagram of a control module circuit according to an embodiment of the present invention. The control module comprises a control chip stm32f103c8t 6. The STM32F103C8T6 is a 32-bit microcontroller based on ARM Cortex-M kernel STM32 series, the working voltage is 3.3V, the size is small, the power consumption is low, and the method is suitable for pop-up application.
Fig. 4 is a schematic diagram of a circuit of the trigger module according to an embodiment of the present invention, in which the trigger module includes an integrated operational amplifier L MH6702, a unidirectional thyristor SCR, and an inverter sn74ahcig04, the integrated operational amplifier L MH6702 serves as a voltage comparator, the output terminal OUT outputs a high level when the sensor voltage is greater than 0.2V, and the output terminal OUT outputs a low level when the sensor voltage is less than 0.8V, the unidirectional thyristor SCR serves as a semi-controllable switch, and the gate G port loses control function after the first turn-on, and the gate G is connected to the output terminal OUT of the integrated operational amplifier, and the thyristor is turned on when the sensor voltage is greater than 0.2V, and the output terminal outputs a high level, so that a false trigger phenomenon during data acquisition is effectively avoided by using the semi-controllable performance of the unidirectional thyristor, and data can be written into the SN 04 only when the write enable port fifo-WEN of the fifo 74AHCIG04 is a low level, so that the output port of the unidirectional thyristor is changed to a low level, and the output port of the high-speed thyristor SCR is changed to a low level, and the inverter sfik-SN 04 is connected to achieve a high-speed storage function.
Fig. 5 is a schematic diagram of a circuit of the data acquisition and storage module according to an embodiment of the present invention, the data acquisition and storage module includes an analog-to-digital converter AD9240 and a Fifo high-speed memory IDT72v285, the analog-to-digital converter AD9240 is a 14-BIT analog-to-digital converter manufactured by american AD company and operating with a single power supply of 10MHz, the chip has an extremely high sampling rate and conversion rate, is suitable for high-speed data acquisition, has a compact internal structure, a high integration level, and a small size, and can greatly reduce the area of a circuit printing plate, the Fifo high-speed memory IDT72V285 is a Fifo (first in first out) high-speed memory chip manufactured by american IDT company, has a capacity of 64K 18BIT, and a data storage rate of up to 100MHz, and thus completely meets the requirement of the analog-to-data storage rate of the analog-to-digital converter AD9240, the Fifo high-speed memory SN74V 285 has an asynchronous read-write-read-write function, has an independent read-write-read clock input port, data write and read-read operations of the data are greatly convenient for data writing and reading, data from the write-read, writing and read-read operations of the Fifo AD chip, the Fifo AD converter AD9240, the Fifo high-speed memory IDT 74V283 is connected with a high-speed memory chip connected by a power supply port, a power supply control module AD-write port, a power supply module AD-3V-write port, a chip connected with a 10V-14V-write port, a chip, a
FWFT/SI、
Q0、Q1、Q2、Q3、Q4、Q5、Q6、Q7、Q8、Q9、Q10、Q11、Q12、Q13、
The ports are respectively connected with the ports of PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA11, PA12, PA13, PA14, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14 and PB15 of the control chip stm32f103c8t 6.
Fig. 6 is a schematic circuit diagram of the communication module according to the embodiment of the present invention. The communication module comprises a USB to serial port chip CH 340G. The USB serial-to-serial port chip CH340G is connected to the control chip stm32f103c8t6 in a manner that a serial output port TXD of the USB serial-to-serial port chip CH340G is connected to a PA9 port of the control chip stm32f103c8t6, a serial input port RXD of the USB serial-to-serial port chip CH340G is connected to a PA10 port of the control chip stm32f103c8t6, a DTR # port of the USB serial-to-serial port chip CH340G is connected to a RESET port of the control chip stm32f103c8t6, and an RTS # port of the USB serial-to-serial port chip CH340G is connected to a BOOT0 port of the control chip stm32f103c8t 6. In order to reduce the volume of the printed circuit board, the serial port communication module is arranged on an independent printed circuit board. When designing a printed circuit board, 4 ports of PA9, PA10, RESET and BOOT0 of a control chip stm32f103c8t6 are respectively connected with 4 bus bars, and 4 ports of TXD, RXD, DTR #, RTS # of a USB serial-to-serial port chip CH340G are respectively connected with 4 bus bars. The USB interface of the communication module is inserted into the USB interface of the PC upper computer, and 4 pins of the communication module are inserted into 4 pins of the control system, so that the serial port communication function can be realized.
The working process of the air cannon missile-borne data acquisition system is as follows: in the process that the air cannon shoots a target, the data of the acceleration sensor is collected through the analog-digital converter, and when the acceleration reaches a threshold value set by the trigger module, the trigger module controls the fifo high-speed memory to start to store the data collected by the analog-digital converter. After the test is finished, the data in the fifo high-speed memory is read by utilizing the serial port communication function of the communication module, so that the data can be further processed.
Claims (10)
1. An air cannon missile-borne acceleration data acquisition system, characterized in that the system comprises:
the acquisition and storage module: the device is used for acquiring acceleration data of the on-missile acceleration sensor, converting the acquired acceleration data into digital signals and storing the digital signals obtained through conversion;
a triggering module: the data acquisition and storage module is used for controlling the data storage;
a control module: the time sequence control module is used for data transmission, acquisition and storage;
a communication module: the device is used for programming programs and serial port communication;
a power supply module: the voltage-reducing and voltage-stabilizing circuit is used for carrying out voltage-reducing and voltage-stabilizing operation on the input of an external power supply and providing required working voltage for other modules of the acquisition system.
2. The system according to claim 1, characterized in that the acquisition and storage module comprises an analog-to-digital converter (9) and a fifo high-speed memory (10), the analog-to-digital converter (9) converting the acquired acceleration data into digital signals, the fifo high-speed memory (10) having a separate read-write clock input for storing the digital signals.
3. The system according to claim 2, characterized in that the triggering module comprises a voltage comparator (6), a unidirectional thyristor (7) and an inverter (8); the rear end of the voltage comparator (6) is connected with the unidirectional thyristor (7), the rear end of the unidirectional thyristor (7) is connected with the inverter (8), and the rear end of the inverter (8) is connected with the fifo high-speed memory;
the unidirectional thyristor (7) is used as a semi-controllable switch, after the unidirectional thyristor is turned on for the first time, the gate pole G port loses control function, the gate pole G is connected with the output end OUT of the voltage comparator (6), when the voltage of the acceleration sensor is more than 0.2V, the unidirectional thyristor (7) is turned on, and the output end of the unidirectional thyristor outputs high level; the inverter (8) converts a high level to a low level.
4. The system according to claim 3, wherein the control module comprises a control chip (4), the fifo high-speed memory (10) is connected with the control chip (4) at the back end, the communication module is connected with the control chip (4) at the back end, and the control chip (4) is of stm32 series.
5. The system according to claim 4, characterized in that the control chip (4) is a control chip STM32F103C8T6, the voltage comparator (6) is L MH6702, the inverter (8) is SN74AHC1G04, and the fifo high speed memory (10) is an IDT72V 285.
6. The system according to claim 4, characterized in that the communication module is connected with the computer at the back end, the communication module comprises a serial communication module, and the first function of the serial communication module is to burn a program written on the computer into the control chip (4); the second function of the serial port communication module is to transmit the digital quantity stored in the fifo high-speed memory (10) to a computer by means of serial port communication.
7. The system according to claim 6, wherein the communication module further comprises a USB to serial port chip (11), the USB to serial port chip (11) is connected to the control chip (4) in such a manner that a serial output port TXD of the USB to serial port chip (11) is connected to a PA9 port of the control chip, a serial input port RXD of the USB to serial port chip is connected to a PA10 port of the control chip, a DTR # port of the USB to serial port chip is connected to a RESET port of the control chip, and an RTS # port of the USB to serial port chip is connected to a BOOT0 port of the control chip.
8. The system of claim 7, wherein the USB to serial port chip (11) is CH 340G.
9. The system of claim 7, wherein the power module comprises a voltage regulation chip L M7805(1), a voltage regulation chip L M117(2), and a voltage regulation chip L T1931(3), the voltage regulation chip L M7805(1) stabilizes +9V to +5V for supplying power to the positive terminal of the analog-to-digital converter (9), the one-way thyristor (7), and the voltage comparator (6), the voltage regulation chip L T1931(3) converts +5V to-5V for supplying power to the negative terminal of the voltage comparator (6), and the voltage regulation chip L M117(2) stabilizes +5V to 3.3V for supplying power to the fifo high speed memory (10) and the control chip (5).
10. A method for acquiring acceleration by using the system of any one of claims 1-9, wherein during the process of shooting the target by the air cannon, the data of the acceleration sensor is acquired by the analog-digital converter (9), and when the acceleration reaches the threshold value set by the trigger module, the trigger module controls the fifo high-speed memory (10) to start storing the data acquired by the analog-digital converter (9); after the test is finished, the data in the fifo high-speed memory (9) is read by utilizing the serial port communication function of the communication module, so that the further data processing is realized.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102736541A (en) * | 2012-06-19 | 2012-10-17 | 北京航空航天大学 | Device for acquiring rocket-borne data of solid-liquid power sounding rocket |
| US20170248634A1 (en) * | 2016-02-29 | 2017-08-31 | Keysight Technologies, Inc. | Measurement system that stores pre- and post-qualification signal data |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102736541A (en) * | 2012-06-19 | 2012-10-17 | 北京航空航天大学 | Device for acquiring rocket-borne data of solid-liquid power sounding rocket |
| US20170248634A1 (en) * | 2016-02-29 | 2017-08-31 | Keysight Technologies, Inc. | Measurement system that stores pre- and post-qualification signal data |
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