CN112395218B - SPI-NAND Flash memory chip with DDR high transmission interface and operation method - Google Patents

Abstract

The invention discloses an SPI-NAND Flash memory chip with a high transmission interface, which comprises an SPI command logic control unit, an MCU digital logic unit, a NAND Flash memory unit and DQS pins; the MCU digital logic unit comprises a DDR Ping buffer and a DDR Pong buffer; the NAND Flash storage unit comprises a static random access memory and a NAND Flash memory, wherein the static random access memory comprises a data buffer and a register; the DQS pin exchanges signals with the SPI command logic control unit, the MCU digital logic unit exchanges signals with the NAND Flash storage unit, and the MCU digital logic unit is internally provided with a DDR mode to realize that the DQS pin reads data of the NAND Flash storage unit; according to the SPI command issued by the SPI command logic control unit, loading data into the data buffer, starting the DDR command to start DQS as a synchronizing signal Clock, and reading the data through the Clock and DQS signals.

Description

SPI-NAND Flash memory chip with DDR high transmission interface and operation method

Technical Field

The invention belongs to the technical field of memory chips, and particularly relates to a novel SPI-NAND Flash memory chip with a DDR high transmission interface.

Background

In order to meet the requirement of high-speed transmission, the current SPI-NAND Flash chip has a clock frequency of about 104Mhz to 120Mhz, and the four-channel Data throughput is about 480Mbit/S, so that the maximum throughput can be improved by 2 times to 960Mbit/S by referring to the mode base of NV-DDR2 (Double Data Rate) in Open NAND Flash Interface Specification and adding the mode base into SPI-NAND Flash.

In the Synchronous (Synchronous) mode of operation, the current SPI-NAND Flash chip has 4Bit I/O as the highest channel and 8 Bit I/O as the highest channel TSOP SLC Parallel NAND Flash, so the overall throughput is 2 times different.

SPI-NAND is a standard element applied to various system platforms piece by piece at present, the current SPI-NAND Flash market is all applied to products with small capacity, the supported capacity is 4GB capacity at maximum, the used Flash is SLC (Single-level cell) specification, the requirements of the supported platforms are wider and wider, the requirements of the market on the application are increased from small capacity to medium-high capacity, and the requirements are higher in increasing transmission rate, if the requirements of customers are to be supported, the following problems are to be solved:

1. taking the current standard component as the element packaging specification of the WSON8, an MLC (Multi-level cell) Flash chip must be used for supporting medium and high capacity, and MLC NAND Flash Die Size (chip size) cannot be packaged in the specification of the WSON8 due to capacity increase;

2. the use of DDR2 specifications will increase the transmission throughput by a factor of 2, but the current WSON8 cannot support the DDR2 specifications because the number of buses is only 8 pins, but the number of buses needs to be modified if the control lines required for DDR2 needs to be increased.

Disclosure of Invention

The invention aims to: in order to solve the problems pointed out in the prior art, the invention provides a novel SPI-NAND Flash memory chip with a DDR high transmission interface and an operation method.

The technical scheme is as follows: a novel SPI-NAND Flash memory chip with high transmission interface, comprising: the SPI command logic control unit, the MCU digital logic unit, the NAND Flash storage unit and the DQS pin can be used for issuing an SPI command; the MCU digital logic unit comprises a DDR Ping buffer and a DDR Pong buffer; the NAND Flash storage unit comprises a static random access memory and a NAND Flash memory, wherein the static random access memory comprises a data buffer and a register; the DQS pin exchanges signals with the SPI command logic control unit, the MCU digital logic unit exchanges signals with the NAND Flash storage unit, the MCU digital logic unit is internally provided with a DDR mode, and the DQS pin is used for reading data of the NAND Flash storage unit, in particular the DQS pin is used for reading data of a register; loading data into a data buffer according to an SPI command issued by an SPI command logic control unit; the MCU digital logic unit starts DQS signal to be synchronous signal Clock, realizes data reading through synchronous signal Clock and DQS signal, comprising:

when the DDR mode is started, 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is the falling edge, the 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is the rising edge, the DDR Ping buffer and the DDR Pong buffer alternately exchange data with the DQS pin, when the DQS pin finishes reading 1Byte data, the 2 Byte data are preloaded into the register synchronously, and when the last Byte data is read, the DDR mode is closed.

Furthermore, the static random access memory adopts ARM High-Speed Single-Port SRAM.

Further, 2 Byte data are preloaded into 4 registers whose contents are high 4Bits and low 4Bits.

Further, the MCU digital logic unit further includes a counter, wherein when the DDR mode is turned on, the counter is 0, and when the DQS pin finishes reading 1Byte data, the counter is added with 2 until the value of the counter is equal to the Page Size of the NAND flash memory, the DDR mode is automatically turned off.

Furthermore, the SPI-NAND Flash storage chip is of a BGA packaging structure.

The invention also discloses an operation method of the novel SPI-NAND Flash memory chip with the high transmission interface, which comprises the following steps:

step 1: reading data in a data buffer according to the SPI command;

step 2: entering DDR mode, initially count=0, taking 2 Byte data stored in the data buffer and preloading the data into a register;

step 3: when the DQS time sequence is the falling edge, 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is the rising edge, the DDR Ping buffer and the DDR Pong buffer alternately exchange data with the DQS pin, and when the DQS pin finishes reading 1Byte data, 2 Byte data are preloaded synchronously; count=count+2;

step 4: judging whether the Page Size of the Count and the Page Size of the NAND flash memory are equal, if so, ending the DDR mode, otherwise, turning to the step 3.

Further, in the DDR mode, if other SPI commands exist, the DDR mode is automatically turned off.

The beneficial effects are that: the invention adopts DDR transmission mode, through which the transmission speed can be increased by 2 times, and when facing the requirement of SPI-NAND Flash with large capacity, pages can be amplified, so that the transmission is particularly required to be accelerated to meet the requirement of an application end product, and NV-DDR2 is the best method for improving the current SPI-NAND Flash chip.

Drawings

FIG. 1 is a diagram of SPI-NADN Flash overall architecture and pin definition;

FIG. 2 is a diagram of a standard SPI-NAND WSON8 package pin definition;

FIG. 3 is a schematic diagram of a TFBGA package;

FIG. 4 is a waveform diagram of SPI-NAND 4Bit Mode;

FIG. 5 is a waveform diagram after adding DDR Mode;

FIG. 6 is a schematic flow diagram of an operation Enable DDR mode;

FIG. 7 is a workflow diagram of a novel SPI-NAND Flash memory chip;

FIG. 8 is a waveform diagram after adding Data Mask PreLoad time sequence;

FIG. 9 is a basic block diagram and content schematic of NAND Flash;

FIG. 10 is a schematic diagram of a novel SPI-NAND Flash memory chip frame.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

Because SPI-NAND Flash belongs to passive memory chip, there is strict operation command to read and write data in the present operation mode, in order to meet the demand of increasing transmission speed, NV-DDR2 technology is used, DDR mode is added to increase 2 times of reading speed based on the present SPI-NAND Flash memory chip, it is applied to speed up reading data, 1 Clock is used as transmission unit, and it is reduced to half Clock. The SPI-NAND Flash memory chip is now described as follows:

as shown in fig. 1 and 10, a novel SPI-NAND Flash memory chip with a high transmission interface includes: the SPI command logic control unit, the MCU digital logic unit, the NAND Flash storage unit and the DQS pin can be used for issuing an SPI command; the MCU digital logic unit comprises a DDR Ping buffer and a DDR Pong buffer; the NAND Flash storage unit comprises a static random access memory and a NAND Flash memory, wherein the static random access memory comprises a data buffer and a register; the DQS pin exchanges signals with the SPI command logic control unit, the MCU digital logic unit exchanges signals with the NAND Flash storage unit, and the MCU digital logic unit is internally provided with a DDR mode to realize that the DQS pin reads data of the NAND Flash storage unit; loading NAND Flash data into a data buffer according to an SPI command issued by an SPI command logic control unit; when the DDR mode is started, 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is the falling edge, the 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is the rising edge, data exchange is alternately carried out on the DQS pin through the DDR Ping buffer and the DDR Pong buffer, after the DQS pin finishes reading 1Byte data, the 2 Byte data are preloaded into the register synchronously, and when the DQS time sequence finishes reading the last Byte data, the DDR mode is closed.

To meet the demand for increasing transmission speed, static Random Access Memories (SRAM) in chips have been updated to support high-speed transmission designs: comprising the following steps: because DDR 108Mhz transmission is supported, ARM High-Speed Single-Port SRAM is adopted, and the working frequency is 200Mhz and is higher than the transmission Speed of an external frequency. The NAND Flash data is loaded into a data Buffer Cache Buffer by using an SPI command, the storage position of the data Buffer Cache Buffer is the SRAM storage space, then a DDR mode is started, at the moment, 2 Byte data of the SRAM are preloaded into 4 Register areas by hardware, the content of the Register areas is high 4Bits and low 4Bits, the reason for using the 2 Byte is mainly to use a Ping Pond mode for an alternating mode, the reason is that after DQS finishes reading 1Byte, the data is directly pre-read into the Register areas, and after the last Byte is read, the DDR mode is automatically closed.

The DQS signal is used to accurately distinguish each transmission period in one clock period and is convenient for a receiver to accurately receive data, so that after the DDR mode is started, a chip can generate DQS signals and transmit data simultaneously after finishing the preparation of pre-reading data, data Mask PreLoad time sequence is used in the design of the inside of hardware to ensure continuous transmission quality, referring to FIG. 8, when the DQS time sequence is a falling edge, the data is preloaded to a Register, the Ping Pong double-Bit mode is used in the hardware design, and in a 4Bit SPI transmission interface, a Bit group is split into high 4Bit and low 4Bit through the Register.

In this embodiment, a Counter is used to implement a read function for automatically ending the DDR mode, where the read mode is implemented by taking a Page of the NAND Flash as a unit (Page), fig. 9 is a basic structure diagram and content of the NAND Flash, when the DDR mode is enabled, the Counter is set to 0, when the Active DQS completes transmission, the Counter is added to 2, and when the Counter is equal to the Page Size, the DDR mode is automatically turned off, and the process flow chart is shown in fig. 7.

In order to solve the problem of transmission errors caused by the fact that erroneous data can be intercepted due to voltage fluctuation in the transmission process, SPI-NAND Flash I/O needs to support high-speed signal processing.

As shown in fig. 1, in order to increase the DDR mode, a new pin DQS is required as a DDR mode synchronization pin, and as shown in the standard SPI-NAND WSON8 package pin definition diagram of fig. 2, it is known that the above chip cannot be satisfied by using the WSON8 package, so that the TFBGA package of fig. 3 is required, and the ESD and high-speed anti-noise configuration is enhanced in the pins of the package. The ESD function is configured by providing a corresponding packaging technology and customized parts by a packaging factory, and in the DDR mode, the present embodiment selects a BGA package, which has the following characteristics:

1. the number of I/O pins is increased, but the distance between the pins is far greater than that of QFP packaging mode, so that the yield is improved.

2. Although the power consumption of the BGA increases, the electrothermal performance can be improved because the controlled collapse chip method is adopted for soldering.

3. The signal transmission delay is small, and the adaptation frequency is greatly improved.

4. The assembly can be performed by coplanar welding, and the reliability is greatly improved.

With the voltage change on the I/O data transfer, a small amount of current is required to charge the parasitic capacitance. At high speed transmission, the voltage of the signal line changes rapidly, and this additional charging current may be considerable, thus reducing the current flowing in the data line. This reduction in current causes a slight change in the impedance of the data line, affecting the total amount of power it delivers. If the power transfer loss is too high, the signal integrity of the data line is degraded, and a higher junction capacitance is selected to address the signal integrity on the transmission in order to support high frequency transmission.

Referring to fig. 7, the operation method of the novel SPI-NAND Flash memory chip includes the following steps:

step 1: reading data in a data buffer according to the SPI command;

step 2: entering a DDR mode, wherein count=0, and preloading 2 Byte data stored in a data buffer into a register;

step 3: when the DQS time sequence is the falling edge, 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is the rising edge, data exchange is alternately carried out on the DQS pin through the DDR Ping buffer and the DDR Pong buffer, and when the DQS pin finishes reading 1Byte data, 2 Byte data are preloaded into the register synchronously; count=count+2;

step 4: judging whether the Page Size of the Count and the Page Size of the NAND flash memory are equal, if so, ending the DDR mode, otherwise, turning to the step 3.

In DDR mode, if there are other SPI commands, the DDR mode is automatically turned off.

FIG. 4 shows SPI-NAND 4Bit Mode waveforms, from which 2 Clock signals are required to transmit 1Byte of data, while FIG. 5 shows 1 Clock signal after adding DDR Mode. FIG. 6 is a flow chart of an operation enabling DDR mode, wherein the DDR mode is required to be started by a device through an SPI-NAND Flash command, after the command is received by a main control end of the SPI-NAND Flash, internal Firmware software starts internal DQS Clock Register to inform hardware to start DQS Clock, the device end needs to align Clock to receive data, and after the last Byte is continuously read, DDR is cut off by internal HW to finish DDR reading.

Claims (6)

1. An SPI-NAND Flash memory chip with high transmission interface, which is characterized in that: comprising the following steps: the SPI command logic control unit, the MCU digital logic unit, the NAND Flash storage unit and the DQS pin can be used for issuing an SPI command; the MCU digital logic unit comprises a DDR Ping buffer and a DDR Pong buffer; the NAND Flash storage unit comprises a static random access memory and a NAND Flash memory, wherein the static random access memory comprises a data buffer and a register; the DQS pin exchanges signals with the SPI command logic control unit, the MCU digital logic unit exchanges signals with the NAND Flash storage unit, and the MCU digital logic unit is internally provided with a DDR mode to realize that the DQS pin reads data of a register; loading data into a data buffer according to an SPI command issued by an SPI command logic control unit; the MCU digital logic unit starts DQS signal to be synchronous signal Clock, realizes data reading through synchronous signal Clock and DQS signal, comprising:

when the DDR mode is started, 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is the falling edge, the 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is the rising edge, the DDR Ping buffer and the DDR Pong buffer alternately exchange data with the DQS pin, when the DQS pin finishes reading 1Byte data, the 2 Byte data are preloaded into the register synchronously, and when the last Byte data is read, the DDR mode is closed.

2. The SPI-NAND Flash memory chip with high transmission interface of claim 1, wherein: the static random access memory adopts ARM High-Speed Single-Port SRAM.

3. The SPI-NAND Flash memory chip with high transmission interface of claim 1, wherein: 2 Byte data are preloaded into 4 registers whose contents are high 4Bits and low 4Bits.

4. The SPI-NAND Flash memory chip with high transmission interface of claim 1, wherein: the MCU digital logic unit also comprises a counter, wherein the counter is 0 when the DDR mode is started, and is added with 2 after the DQS pin finishes reading 1Byte data until the value of the counter is equal to the Page Size of the NAND flash memory, and the DDR mode is automatically closed.

5. The SPI-NAND Flash memory chip with high transmission interface of claim 1, wherein: the SPI-NAND Flash storage chip is of a BGA packaging structure.

6. A method of operating an SPI-NAND Flash memory chip with a high transmission interface according to any one of claims 1 to 5, characterized by: the method comprises the following steps:

step 1: reading data in a data buffer according to the SPI command;

step 2: entering DDR mode, initially count=0, taking 2 Byte data stored in the data buffer and preloading the data into a register;

step 3: when the DQS time sequence is the falling edge, 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is the rising edge, the DDR Ping buffer and the DDR Pong buffer alternately exchange data with the DQS pin, and when the DQS pin finishes reading 1Byte data, 2 Byte data are preloaded synchronously; count=count+2;

step 4: judging whether the Page Size of the Count and the Page Size of the NAND flash memory are equal, if so, ending the DDR mode, otherwise, turning to the step 3.