CN112395218A - Novel SPI-NAND Flash memory chip with DDR high transmission interface and operation method - Google Patents
Novel SPI-NAND Flash memory chip with DDR high transmission interface and operation method Download PDFInfo
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- CN112395218A CN112395218A CN202011177835.6A CN202011177835A CN112395218A CN 112395218 A CN112395218 A CN 112395218A CN 202011177835 A CN202011177835 A CN 202011177835A CN 112395218 A CN112395218 A CN 112395218A
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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- G06F15/00—Digital computers in general; Data processing equipment in general
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- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
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Abstract
The invention discloses a novel SPI-NAND Flash memory chip with a high transmission interface, which comprises: the system comprises an SPI command logic control unit, an MCU digital logic unit, an NAND Flash storage unit and a DQS pin, wherein the SPI command logic control unit can be used for issuing SPI commands; the MCU digital logic unit comprises a DDR Ping buffer and a DDR Pong buffer; the NAND Flash storage unit comprises a static random access memory and a NAND Flash memory, and the static random access memory comprises a data buffer and a register; the DQS pin exchanges signals with the SPI command logic control unit, the MCU digital logic unit exchanges signals with the NAND Flash storage unit, and a DDR mode is built in the MCU digital logic unit to realize that the DQS pin reads data of the NAND Flash storage unit; and loading the data into a data buffer according to an SPI command issued by the SPI command logic control unit, starting up the DQS by a DDR command to serve as a synchronous signal Clock, and reading the data through the Clock and the DQS.
Description
Technical Field
The invention belongs to the technical field of memory chips, and particularly relates to a novel SPI-NAND Flash memory chip with a DDR high transmission interface.
Background
At present, the clock frequency of an SPI-NAND Flash chip is about 104Mhz to 120Mhz, the four-channel Data throughput is about 480Mbit/S, and in order to meet the requirement of high-speed transmission, the SPI-NAND Flash chip is added to the SPI-NAND Flash according to the mode basis of NV-DDR2(Double Data Rate) in Open NAND Flash Interface Specification, so that the maximum throughput can be improved by 2 times to 960 Mbit/S.
Under the operation mode of a Synchronous (synchronization) mode, the highest channel of the prior SPI-NAND Flash chip is I/O4 Bit, and the highest channel of the TSOP SLC Parallel NAND Flash is I/O8 Bit, so that the overall throughput has 2 times of difference.
The SPI-NAND is a standard element that is applied to each system platform one by one, the SPI-NAND Flash market is applied to products with small capacity, the supported capacity is 4GB capacity at most, and the used flashes are all in SLC (Single-level cell) specification, because the supported platforms are more and more extensive, the application demand in the market is also increased from the small capacity demand to the medium-high capacity, and there is a higher demand for increasing the transmission rate, and if the demand of the customer is to be supported, the following problems need to be solved:
1. with the current standard as the element packaging specification of the WSON8, if medium and high capacity is to be supported, an MLC (Multi-level cell) Flash chip is required, and the MLC NAND Flash Die Size (chip Size) cannot be packaged in the specification of the WSON8 due to the increase of capacity;
2. the specification using DDR2 can increase the transmission throughput by 2 times, but the current WSON8 cannot support the DDR2 specification because the number of buses is only 8 pins, but if the control lines required by DDR2 need to be increased, the number of buses needs to be modified.
Disclosure of Invention
The purpose of the invention is as follows: in order to solve the problems pointed out in the prior art, the invention provides a novel SPI-NAND Flash memory chip with a DDR high transmission interface and an operation method.
The technical scheme is as follows: a novel SPI-NAND Flash memory chip with high transmission interface comprises: the system comprises an SPI command logic control unit, an MCU digital logic unit, an NAND Flash storage unit and a DQS pin, wherein the SPI command logic control unit can be used for issuing SPI commands; the MCU digital logic unit comprises a DDR Ping buffer and a DDR Pong buffer; the NAND Flash storage unit comprises a static random access memory and a NAND Flash memory, and the static random access memory comprises a data buffer and a register; the DQS pin exchanges signals with the SPI command logic control unit, the MCU digital logic unit exchanges signals with the NAND Flash storage unit, and a DDR mode is built in the MCU digital logic unit to realize that the DQS pin reads data of the NAND Flash storage unit, in particular to realize that the DQS pin reads data of a register; loading data into a data buffer according to an SPI command issued by an SPI command logic control unit; MCU digital logic unit starts DQS signal and does synchronizing signal Clock, realizes data reading through synchronizing signal Clock and DQS signal, includes:
when the DDR mode is started, 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is a falling edge, the 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is a rising edge, the DDR Ping buffer and the DDR Pong buffer alternately exchange data with the DQS pin, when the DQS pin finishes reading 1Byte data, the 2 Byte data are synchronously preloaded into the register, and when the last Byte data is read, the DDR mode is closed.
Furthermore, the static random access memory adopts an ARM High-Speed Single-Port SRAM.
Further, 2 Byte data are preloaded into 4 registers, whose contents are high 4Bits and low 4 Bits.
Furthermore, the MCU digital logic unit also comprises a counter, when the DDR mode is started, the counter is 0, when the DQS pin finishes reading 1Byte data, the counter is increased by 2, and the DDR mode is automatically closed until the numerical value of the counter is equal to the Page Size of the NAND flash memory.
Furthermore, the SPI-NAND Flash memory chip is of a BGA packaging structure.
The invention also discloses an operation method of the novel SPI-NAND Flash memory chip with the high transmission interface, which comprises the following steps:
step 1: reading the data in the data buffer according to the SPI command;
step 2: entering DDR mode, initial Count is 0, taking 2 Byte data stored in data buffer to preload to register;
and step 3: when the DQS time sequence is a falling edge, preloading 2 Byte data stored in a data buffer into a register, when the DQS time sequence is a rising edge, alternately exchanging data with a DQS pin by a DDR Ping buffer and a DDR Pong buffer, and after the DQS pin finishes reading 1Byte data, synchronously finishing preloading 2 Byte data into the register; count + 2;
and 4, step 4: and judging whether the Count is equal to the Page Size of the NAND flash memory, if so, ending the DDR mode, otherwise, turning to the step 3.
Further, in the DDR mode, if there is another SPI command, the DDR mode is automatically turned off.
Has the advantages that: the invention adopts DDR transmission mode, through this mode, can increase the transmission speed of 2 times, and face the requirement of SPI-NAND Flash of the large capacity, the Page (Page) will be enlarged, therefore will require accelerating in particular in transmission in order to accord with the requirement on the products of application end, and NV-DDR2 will be the best method to improve the present SPI-NAND Flash chip.
Drawings
FIG. 1 is a diagram of the SPI-NADN Flash overall architecture and pin definition;
FIG. 2 is a diagram of a standard SPI-NAND WSON8 package footprint definition;
FIG. 3 is a schematic view of a TFBGA package;
FIG. 4 is a waveform diagram of SPI-NAND 4Bit Mode;
FIG. 5 is a waveform diagram after the new DDR Mode is added;
FIG. 6 is a schematic diagram illustrating a DDR mode operation;
FIG. 7 is a flowchart of the operation of the novel SPI-NAND Flash memory chip;
FIG. 8 is a waveform diagram after increasing the Data Mask Preload timing;
FIG. 9 is a diagram of a basic structure and contents of a NAND Flash;
FIG. 10 is a diagram of a novel SPI-NAND Flash memory chip frame.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Since SPI-NAND Flash belongs to passive memory chip, in current operation mode, there is strict operation command to do read-write data method, in order to meet the requirement of increasing transmission speed, NV-DDR2 technique is used, DDR mode is added on the basis of existing SPI-NAND Flash memory chip to increase 2 times of reading speed, it is applied to accelerating reading data, 1 Clock is used as transmission unit, and is reduced to half Clock as transmission unit. The SPI-NAND Flash memory chip will now be described as follows:
as shown in fig. 1 and 10, a novel SPI-NAND Flash memory chip with a high transmission interface includes: the system comprises an SPI command logic control unit, an MCU digital logic unit, an NAND Flash storage unit and a DQS pin, wherein the SPI command logic control unit can be used for issuing SPI commands; the MCU digital logic unit comprises a DDR Ping buffer and a DDR Pong buffer; the NAND Flash storage unit comprises a static random access memory and a NAND Flash memory, and the static random access memory comprises a data buffer and a register; the DQS pin exchanges signals with the SPI command logic control unit, the MCU digital logic unit exchanges signals with the NAND Flash storage unit, and a DDR mode is built in the MCU digital logic unit to realize that the DQS pin reads data of the NAND Flash storage unit; loading the NAND Flash data into a data buffer according to an SPI command issued by an SPI command logic control unit; when the DDR mode is started, 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is a falling edge, the 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is a rising edge, data exchange is alternately carried out with the DQS pin through the DDR Ping buffer and the DDR Pong buffer, when the DQS pin finishes reading 1Byte data, the 2 Byte data are synchronously preloaded into the register, and when the last Byte data is read, the DDR mode is closed.
To meet the demand for increased transmission speed, the Static Random Access Memory (SRAM) in the chip is also upgraded to support high-speed transmission: the method comprises the following steps: because DDR 108Mhz transmission is supported, an ARM High-Speed Single-Port SRAM is adopted, the working frequency is 200Mhz, and the transmission Speed is higher than that of external frequency. Loading NAND Flash data into a data Buffer Cache Buffer by using an SPI command, wherein the storage position of the data Buffer Cache Buffer is an SRAM storage space, and then starting a DDR mode, at the moment, firstly preloading 2 Byte data of the SRAM into 4 Register registers by hardware, wherein the contents of the Register registers are high 4Bits and low 4Bits, and the reason for using 2 bytes is mainly to use a Ping Pond mode as an alternate mode, the reason is that the data can be directly pre-read to the Register registers after the DQS finishes reading 1Byte, and the DDR mode can be automatically closed after the last Byte is read.
The DQS signal is used for accurately distinguishing each transmission period in a clock period and facilitating a receiver to accurately receive Data, so that after a DDR mode is started, a chip generates the DQS signal and simultaneously transmits Data after completing prepared pre-reading of the Data, in order to ensure continuous transmission quality, a Data Mask PreLoad time sequence is used in the internal design of hardware, referring to FIG. 8, when the DQS time sequence is a falling edge, the Data is preloaded to a Register, and a Ping Pong double-Bit mode is adopted in the hardware design, and in a 4Bit SPI transmission interface, a byte is split into a high 4Bit and a low 4Bit through the Register.
In this embodiment, a Counter is used to implement a reading function for automatically ending the DDR mode, where the reading mode is Page unit (Page) of NAND Flash, fig. 9 is a basic structure diagram and content of NAND Flash, when the DDR mode is enabled, the Counter is set to 0, when Active DQS completes transmission, the Counter is increased by 2, when the Counter equals Page Size, the DDR mode is automatically turned off, and a process flow chart thereof refers to fig. 7.
In order to solve the problem that errors in transmission are caused by the fact that erroneous data can be intercepted due to voltage fluctuation in the transmission process, the SPI-NAND Flash I/O needs to be capable of supporting high-speed signal processing.
As shown in fig. 1, in order to add DDR mode, a new pin DQS is required to be added as a DDR mode synchronization pin, and as can be seen from the pin definition diagram of the standard SPI-NAND WSON8 package shown in fig. 2, the above chip cannot be satisfied by using WSON8 package, so the TFBGA package shown in fig. 3 needs to be used, and ESD and high-speed anti-interference configuration are enhanced in the packaged pins. The ESD function needs to be configured by a package factory providing a corresponding package technology and a customized portion, and in the DDR mode, the embodiment uses a BGA package, which has the following characteristics:
1. although the number of the I/O pins is increased, the distance between the pins is far larger than that of a QFP packaging mode, and the yield is improved.
2. Although the power consumption of the BGA is increased, the electrothermal performance can be improved since the controlled collapse wafer bonding is used.
3. The signal transmission delay is small, and the adaptive frequency is greatly improved.
4. The assembly can be performed by coplanar welding, and the reliability is greatly improved.
As the voltage on the I/O data transfer changes, a small amount of current is required to charge the parasitic capacitance. In high speed transmission, the voltage of the signal line changes rapidly, and this extra charging current may be considerable, thereby reducing the current flowing in the data line. This reduction in current causes a slight change in the impedance of the data line, affecting the amount of power it transmits. If the power transmission loss is too high, the signal integrity of the data line will be degraded, and to support high frequency transmission, a higher junction capacitance is used to solve the signal integrity on transmission.
Referring to fig. 7, the operation method of the novel SPI-NAND Flash memory chip includes the following steps:
step 1: reading the data in the data buffer according to the SPI command;
step 2: entering into DDR starting mode, Count equals to 0, and preloading the 2 Byte data stored in the data buffer to the register;
and step 3: when the DQS time sequence is a falling edge, preloading 2 Byte data stored in a data buffer into a register, when the DQS time sequence is a rising edge, alternately exchanging data with a DQS pin through a DDR Ping buffer and a DDR Pong buffer, and after the DQS pin finishes reading 1Byte data, synchronously finishing preloading 2 Byte data into the register; count + 2;
and 4, step 4: and judging whether the Count is equal to the Page Size of the NAND flash memory, if so, ending the DDR mode, otherwise, turning to the step 3.
When in DDR mode, if there are other SPI commands, DDR mode is automatically closed.
FIG. 4 is a waveform diagram of SPI-NAND 4Bit Mode, wherein 2 Clocks are required for transmitting 1Byte of data from the waveform diagram, while FIG. 5 is a waveform diagram of 1 Clocks required for transmitting 1Byte of data after adding DDR Mode. Fig. 6 is a flowchart illustrating the DDR mode operation, where the DDR mode is used by the device side to start the DDR mode through the SPI-NAND Flash command, and after the main control side of the SPI-NAND Flash receives the command, the internal Firmware software starts the internal DQS Clock Register to notify the hardware to turn on the DQS Clock, and the device side needs to align with the Clock to receive data, and after the last Byte is continuously read, the DDR is cut off by the internal HW, thereby completing the DDR read mode.
Claims (7)
1. A novel SPI-NAND Flash memory chip with high transmission interface is characterized in that: the method comprises the following steps: the system comprises an SPI command logic control unit, an MCU digital logic unit, an NAND Flash storage unit and a DQS pin, wherein the SPI command logic control unit can be used for issuing SPI commands; the MCU digital logic unit comprises a DDR Ping buffer and a DDR Pong buffer; the NAND Flash storage unit comprises a static random access memory and a NAND Flash memory, and the static random access memory comprises a data buffer and a register; the DQS pin exchanges signals with the SPI command logic control unit, the MCU digital logic unit exchanges signals with the NAND Flash storage unit, and a DDR mode is built in the MCU digital logic unit to realize that the DQS pin reads data of the register; loading data into a data buffer according to an SPI command issued by an SPI command logic control unit; MCU digital logic unit starts DQS signal and does synchronizing signal Clock, realizes data reading through synchronizing signal Clock and DQS signal, includes:
when the DDR mode is started, 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is a falling edge, the 2 Byte data stored in the data buffer are preloaded into the register, when the DQS time sequence is a rising edge, the DDR Ping buffer and the DDR Pong buffer alternately exchange data with the DQS pin, when the DQS pin finishes reading 1Byte data, the 2 Byte data are synchronously preloaded into the register, and when the last Byte data is read, the DDR mode is closed.
2. The novel SPI-NAND Flash memory chip with high transmission interface according to claim 1, wherein: the static random access memory adopts an ARM High-Speed Single-Port SRAM.
3. The novel SPI-NAND Flash memory chip with high transmission interface according to claim 1, wherein: the 2 Byte data are preloaded into 4 registers whose contents are high 4Bits and low 4 Bits.
4. The novel SPI-NAND Flash memory chip with high transmission interface according to claim 1, wherein: the MCU digital logic unit also comprises a counter, when the DDR mode is started, the counter is 0, when the DQS pin finishes reading 1Byte data, the counter is increased by 2, and the DDR mode is automatically closed until the numerical value of the counter is equal to the Page Size of the NAND flash memory.
5. The novel SPI-NAND Flash memory chip with high transmission interface according to claim 1, wherein: the SPI-NAND Flash memory chip is of a BGA packaging structure.
6. An operation method of a novel SPI-NAND Flash memory chip with a high transmission interface is characterized in that: the method comprises the following steps:
step 1: reading the data in the data buffer according to the SPI command;
step 2: entering DDR mode, initial Count is 0, taking 2 Byte data stored in data buffer to preload to register;
and step 3: when the DQS time sequence is a falling edge, preloading 2 Byte data stored in a data buffer into a register, when the DQS time sequence is a rising edge, alternately exchanging data with a DQS pin by a DDR Ping buffer and a DDR Pong buffer, and after the DQS pin finishes reading 1Byte data, synchronously finishing preloading 2 Byte data into the register; count + 2;
and 4, step 4: and judging whether the Count is equal to the Page Size of the NAND flash memory, if so, ending the DDR mode, otherwise, turning to the step 3.
7. The operating method of the novel SPI-NAND Flash memory chip with high transmission interface according to claim 6, characterized in that: when in DDR mode, if there are other SPI commands, DDR mode is automatically closed.
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Cited By (1)
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| CN114036096A (en) * | 2021-11-04 | 2022-02-11 | 珠海一微半导体股份有限公司 | Read controller based on bus interface |
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