CN111431579A - Low-delay VDE satellite-borne downlink digital signal processing system based on FPGA - Google Patents
Low-delay VDE satellite-borne downlink digital signal processing system based on FPGA Download PDFInfo
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- H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
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- H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
- H04L1/0016—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy involving special memory structures, e.g. look-up tables
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Abstract
The invention provides a low-delay VDE satellite-borne downlink digital signal processing system based on an FPGA, which is characterized by comprising the following components: the system comprises a data blocking and high-speed forwarding module, a high-efficiency blocking Turbo coding and scrambling processing module and a multi-bandwidth general modulation transmitting processing module; according to the invention, through the low-delay digital signal processing method and module design based on the VDE communication protocol mechanism, the sending delay of the VDE modulation signal is greatly reduced, the occupation of FPGA resources is reduced, and the method can be applied to a VDE satellite-borne downlink digital signal processing scene.
Description
Technical Field
The invention relates to a signal processing technology, in particular to a low-delay VDE (vertical double-diffused emitter) satellite-borne downlink digital signal processing system based on an FPGA (field programmable gate array), which is suitable for low-delay processing scenes of downlink digital signals in different satellite-borne VDE frame formats.
Background
With the development of maritime communication technology, in order to solve the bottleneck that the existing ship AIS communication system has serious time slot conflict and low communication rate in some areas, the international navigation mark organization (IA L A) proposes a VDE communication system of a ship, and a communication link between a satellite and the ship is added in the VDE system so as to meet different requirements of offshore and offshore ships and lay a foundation for future complex and multifunctional maritime communication applications.
The satellite-borne VDE communication equipment is limited by the limited size and long transmission distance of the equipment, and has high requirements on low delay in receiving and transmitting signals. When a digital signal to be sent comes from a downlink transmitting end of the satellite-borne VDE, a CRC (cyclic redundancy check) code needs to be added, turbo coding is carried out, scrambling codes are added, mapping modulation is carried out, and then the digital signal is sent to a back end for processing according to corresponding frequencies of different frame formats. In the process, since data needs to be buffered and forwarded, transmission delay is difficult to avoid, and a low-delay design needs to be implemented to ensure the validity and accuracy of signals transmitted by the satellite-borne VDE communication equipment.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a low-delay VDE satellite-borne downlink digital signal processing system based on an FPGA. The technical scheme of the invention is as follows:
a low-delay VDE satellite-borne downlink digital signal processing system based on FPGA comprises: the system comprises a data blocking and high-speed forwarding module, a high-efficiency blocking Turbo coding and scrambling processing module and a multi-bandwidth general modulation transmitting processing module;
the data blocking and high-speed forwarding module is used for receiving the VDE satellite-borne downlink digital signal and performing operations of CRC (cyclic redundancy check) code addition, blocking processing and high-speed forwarding on the VDE satellite-borne downlink digital signal; if the VDE satellite-borne downlink digital signal is a short-bit frame format signal, the VDE satellite-borne downlink digital signal is directly forwarded to a high-efficiency block Turbo coding and scrambling processing module for subsequent processing without block processing; if the VDE satellite-borne downlink digital signal is an ultra-long bit frame format signal, block processing is carried out and the signal is forwarded to a high-efficiency block Turbo coding and scrambling processing module for subsequent processing;
the high-efficiency block Turbo coding and scrambling processing module is used for carrying out Turbo coding, punching and scrambling processing on the input short bit frame format signals or the super-long bit frame format signals which are finished in a block mode, and forwarding the signals to the multi-bandwidth general modulation transmitting processing module for subsequent processing;
the multi-bandwidth general modulation transmission processing module is used for identifying different frame formats of the input VDE satellite-borne downlink digital signals, carrying out modulation transmission processing according to corresponding transmission frequencies according to different modulation modes required by the frame formats, including BPSK, QPSK, 1/4 pi QpSK, 8PSK and 16 QAM.
Optionally, the data blocking and high-speed forwarding module further includes: the device comprises a first control state machine, a 16bits FIFO buffer, a 16bit to 1bit serial conversion unit and a frame head extraction and CRC check code splicing unit; wherein:
the first control state machine is used for performing read-write control on the 16bits sFIFO buffer and performing state control on the 16-bit to 1-bit serial conversion unit and the frame header extraction and CRC (cyclic redundancy check) code splicing unit; the state control is specifically as follows:
controlling the data reading state of the serial conversion unit from 16bits to 1bit according to the data length;
finishing frame header information extraction and starting CRC (cyclic redundancy check) when frame data start, and finishing CRC to generate a CRC code when data end;
meanwhile, the first control state machine carries out blocking processing according to the length of a data frame and generates a blocking mark pulse, and the blocking mark pulse is sent to the high-efficiency blocking Turbo coding and scrambling processing module and used as a starting mark bit of a blocking signal;
the 16bits FIFO buffer is used for receiving a VDE satellite-borne downlink digital signal entering in a parallel 16bits form, buffering the input 16bits parallel signal flow and sending the 16 bits-to-1 bit serial conversion unit; the 16-bit sFIFO buffer is provided with a data writing clock, and the interior of the FPGA provides high-power clock input for the 16-bit sFIFO buffer;
a 16-bit to 1-bit serial conversion unit for converting the cached 16-bit parallel signals into 1-bit high-speed serial data and sending the 1-bit high-speed serial data to the frame header extraction and CRC check code splicing unit;
the frame head extraction and CRC check code splicing unit is used for receiving the 1-bit high-speed serial data sent by the 16-bit to 1-bit serial conversion unit and processing the data as follows, judging frame head information at the beginning of frame data, wherein the frame head information comprises a frame starting synchronization bit and a frame format code L inkID, generating required parameters according to L inkID when a subsequent module processes the data conveniently, and generating a CRC check code of a data stream at the same time so as to check the integrity of the data when a signal is received;
and the frame header extraction and CRC check code splicing unit sends the processed signal stream to the high-efficiency block Turbo coding and scrambling processing module.
Optionally, the efficient block Turbo coding and scrambling processing module further includes: the device comprises a block judgment and parameter selection unit, a turbo coding unit, a second control state machine, a scrambling code adding unit and a coding and punching unit; wherein:
the block judgment and parameter selection unit is used for judging whether the signal stream input by the data block and high-speed forwarding module is subjected to block processing according to the block marking pulse provided by the ultra-long frame block marking pulse output unit, and generating parameter information required by turbo coding according to the frame format coding L inkID judged by the frame header, wherein the parameter information comprises the frame length, the block length and the coding rate;
a turbo coding unit for realizing turbo coding of different signal streams according to the parameters generated by the block judgment and parameter selection unit; the FPGA internal high-speed data processing clock provides high-power clock input for the turbo coding unit; the turbo coding unit inputs the processed signal stream into the coding and puncturing unit;
a second control state machine for judging whether the turbo coded signal stream is an effective enabling gap and finishing signal scrambling;
the scrambling adding unit is used for carrying out signal scrambling processing on the signal stream input into the coding and puncturing unit under the control of a second control state machine;
and the coding and punching unit is used for selectively outputting corresponding coding information to the next-stage multi-bandwidth universal modulation and emission processing module according to the frame length, the block length and the coding code rate in the parameters generated by the block judgment and parameter selection unit after turbo coding.
Optionally, the multi-bandwidth general modulation transmission processing module further includes: a third control state machine, a parameter generating unit, a sampling pulse generating unit, an FIFO buffer unit and a general modulator; wherein:
the FIFO buffer unit is used for buffering the signal stream sent by the high-efficiency block Turbo coding and scrambling processing module; the interior of the FPGA provides high-power clock input for the FIFO cache unit;
the parameter generating unit is used for generating required parameters according to frame header judgment information sent by the high-efficiency block Turbo coding and scrambling processing module and sending the parameters to the sampling pulse generating unit and the third control state machine, wherein the parameters at least comprise L inkID synchronous heads, modulation modes, sampling pulse frequency control words and auxiliary counter parameters required by signal receiving;
the sampling pulse generating unit is used for generating sampling pulses required by modulation signal output under the driving of a high-power clock provided in the FPGA according to the sampling pulse frequency control word provided by the parameter generating unit and respectively sending the sampling pulses to the third control state machine and the general modulator;
the third control state machine is used for controlling the FIFO buffer unit to read and transmitting a signal stream to be input into a corresponding general modulator for modulation output according to the parameters generated by the parameter generating unit under the enabling of the sampling pulses provided by the sampling pulse generating unit;
and the general modulator is used for selecting different internal modulators according to modulation mode parameters and finally outputting modulation signals under the enabling of the sampling pulses provided by the sampling pulse generating unit, and the internal modulators at least comprise BPSK, QPSK, 1/4 pi QPSK, 8PSK and 16 QAM.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a low-delay VDE satellite-borne downlink digital signal processing method based on an FPGA (field programmable gate array), which aims at the problem of downlink data processing delay of satellite-borne VDE communication equipment, combines a VDE communication protocol, and adopts a design method of serial-parallel conversion, block processing and storage, high-power clock forwarding, pipelined rapid turbo coding, punching and scrambling and multi-bandwidth universal modulation transmission processing, so that the transmission delay of the satellite-borne VDE downlink digital signal is reduced as much as possible, the resource occupation is reduced, and the digital signal processing capability of the satellite-borne VDE communication equipment is improved.
The data blocking and high-speed forwarding module performs serial-parallel conversion, blocking processing and storage on the ultra-long bit VDE satellite-borne downlink digital signals, and forwards the signals at high speed by taking a block as a unit and using a high-power clock so as to greatly reduce the delay of code modulation.
The high-efficiency block Turbo coding and scrambling processing module performs pipelined fast Turbo coding, punching and scrambling processing on the block parallel data of the downlink digital signal by utilizing a high-power clock through close control of block data.
The multi-bandwidth general modulation transmitting processing module can realize the common frequency mixing, filtering and interpolation design as much as possible according to the enabling pulse generated by different frame formats, and modulate the signals with different signal bandwidths so as to realize low resource occupation and low delay processing.
The efficient block Turbo coding and scrambling processing module can realize the universal design of all 1/2, 3/4, 1/4, 2/3 and 5/6 code rate punching specified by the VDE standard in the FPGA through the control of the second state machine, and the punching and scrambling are fused together, so that the memory consumption of the storage after punching required by the conventional design is reduced.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a block diagram of a low latency VDE satellite-borne downstream digital signal processing system based on FPGA in an embodiment of the present invention;
FIG. 2 is a schematic diagram of an internal structure of a data partitioning and high-speed forwarding module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the internal structure of an efficient block Turbo coding and scrambling module according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an internal structure of a multi-bandwidth general modulation transmission processing module according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Referring to fig. 1, the embodiment discloses a low-latency VDE satellite-borne downlink digital signal processing system based on an FPGA, which includes: the system comprises a data block and high-speed forwarding module, a high-efficiency block Turbo coding and scrambling processing module and a multi-bandwidth general modulation transmitting processing module.
The VDE satellite-borne downlink digital signal is a frame format signal with the number of 24. Preprocessing before sending the satellite-borne VDE downlink digital signals is a linear processing flow, and the satellite-borne VDE downlink digital signals to be sent enter a data partitioning and high-speed forwarding module in a parallel 16-bits mode.
The data blocking and high-speed forwarding module is used for receiving the VDE satellite-borne downlink digital signal and performing operations of CRC (cyclic redundancy check) code addition, blocking processing and high-speed forwarding on the VDE satellite-borne downlink digital signal; if the VDE satellite-borne downlink digital signal is a short-bit frame format signal, the VDE satellite-borne downlink digital signal is directly forwarded to a high-efficiency block Turbo coding and scrambling processing module for subsequent processing without block processing; if the VDE satellite-borne downlink digital signal is an ultra-long bit frame format signal, block processing is carried out and the signal is forwarded to a high-efficiency block Turbo coding and scrambling processing module for subsequent processing;
the high-efficiency block Turbo coding and scrambling processing module is used for carrying out Turbo coding, punching and scrambling processing on the input short bit frame format signals or the super-long bit frame format signals which are finished in a block mode, and forwarding the signals to the multi-bandwidth general modulation transmitting processing module for subsequent processing;
the multi-bandwidth general modulation transmission processing module is used for identifying different frame formats of the input VDE satellite-borne downlink digital signals, carrying out modulation transmission processing according to corresponding transmission frequencies according to different modulation modes required by the frame formats, including BPSK, QPSK, 1/4 pi QPSK, 8PSK and 16 QAM.
As shown in fig. 2, the data blocking and high-speed forwarding module further includes: the device comprises a first control state machine, a 16bits FIFO buffer, a 16bit to 1bit serial conversion unit and a frame head extraction and CRC check code splicing unit; wherein:
the first control state machine is used for performing read-write control on the 16bits sFIFO buffer and performing state control on the 16-bit to 1-bit serial conversion unit and the frame header extraction and CRC (cyclic redundancy check) code splicing unit; the state control is specifically as follows:
controlling the data reading state of the serial conversion unit from 16bits to 1bit according to the data length;
finishing frame header information extraction and starting CRC (cyclic redundancy check) when frame data start, and finishing CRC to generate a CRC code when data end;
meanwhile, the first control state machine carries out blocking processing according to the length of a data frame and generates a blocking mark pulse, and the blocking mark pulse is sent to the high-efficiency blocking Turbo coding and scrambling processing module and used as a starting mark bit of a blocking signal;
the 16bits FIFO buffer is used for receiving a VDE satellite-borne downlink digital signal entering in a parallel 16bits form, buffering the input 16bits parallel signal flow and sending the 16 bits-to-1 bit serial conversion unit; the 16-bit sFIFO buffer is provided with a data writing clock, and the interior of the FPGA provides high-power clock input for the 16-bit sFIFO buffer;
a 16-bit to 1-bit serial conversion unit for converting the cached 16-bit parallel signals into 1-bit high-speed serial data and sending the 1-bit high-speed serial data to the frame header extraction and CRC check code splicing unit;
the frame head extraction and CRC check code splicing unit is used for receiving the 1-bit high-speed serial data sent by the 16-bit to 1-bit serial conversion unit and processing the data as follows, judging frame head information at the beginning of frame data, wherein the frame head information comprises a frame starting synchronization bit and a frame format code L inkID, generating required parameters according to L inkID when a subsequent module processes the data conveniently, and generating a CRC check code of a data stream at the same time so as to check the integrity of the data when a signal is received;
and the frame header extraction and CRC check code splicing unit sends the processed signal stream to the high-efficiency block Turbo coding and scrambling processing module.
It should be noted that: after the signal flow enters the data blocking and high-speed forwarding module, the signal is firstly buffered through a 16bits FIFO buffer so as to carry out UTC time synchronization control in a VDE protocol. The parallel 16-bit data is read by the high-power clock provided in the FPGA for processing, so that the data processing efficiency can be greatly improved, and the data downlink delay is reduced. In order to further reduce data delay, CRC check code addition, turbo coding, scrambling and the like are carried out, and all the data are processed in 16-bit parallel. And the first control state machine is used for controlling the Turbo coding and scrambling processing module and entering the next stage of high-efficiency block Turbo coding and scrambling processing module together with the digital signal.
As shown in fig. 3, the high efficiency block Turbo coding and scrambling processing module further comprises: the device comprises a block judgment and parameter selection unit, a turbo coding unit, a second control state machine, a scrambling code adding unit and a coding and punching unit; wherein:
the block judgment and parameter selection unit is used for judging whether the signal stream input by the data block and high-speed forwarding module is subjected to block processing according to the block marking pulse provided by the ultra-long frame block marking pulse output unit, and generating parameter information required by turbo coding according to the frame format coding L inkID judged by the frame header, wherein the parameter information comprises the frame length, the block length and the coding rate;
a turbo coding unit for realizing turbo coding of different signal streams according to the parameters generated by the block judgment and parameter selection unit; the FPGA internal high-speed data processing clock provides high-power clock input for the turbo coding unit; the turbo coding unit inputs the processed signal stream into the coding and puncturing unit;
the second control state machine is used for judging whether the turbo-coded signal stream effectively enables the gap and finishes signal scrambling;
the scrambling adding unit is used for carrying out signal scrambling processing on the signal stream input into the coding and puncturing unit under the control of a second control state machine;
and the coding and punching unit is used for selectively outputting corresponding coding information to the next-stage multi-bandwidth universal modulation and emission processing module according to the frame length, the block length and the coding code rate in the parameters generated by the block judgment and parameter selection unit after turbo coding.
It should be noted that: after the signal stream enters the high-efficiency block Turbo coding and scrambling processing module, corresponding parameters such as coding code rate, block length and the like are selected according to different signal frame formats, then the pipelined block Turbo coding is carried out, and the signal output delay of the block coding is the time required by outputting the signal length of one block and is far shorter than the whole block coding delay. The universal design of all 1/2, 3/4, 1/4, 2/3 and 5/6 code rate puncturing specified by VDE standards can be realized in the FPGA through state machine control, and then puncturing and scrambling processing are carried out under the control of a second control state machine. The second control state machine is divided into an initial state, a punching code rate judgment jumping state (a state of jumping to the next level of the corresponding code rate), and a punching signal output state. The data signal is enabled to be the punching gap of low level during punching, and the punching gap generated by coding punching is far longer than the time required by scrambling, so that scrambling processing can be realized by using the punching gap, the signal delay generated by cache scrambling in the conventional design is greatly reduced, and simultaneously the resource occupation is reduced. According to the VDE standard protocol, during scrambling processing, for some frame format signals, a sign bit 0 needs to be added at a certain data length of each interval of the digital signal, for example, for a digital signal with a frame format number of 24, 4 bits 0 need to be added at 32 sign bits, that is, 96 bits, and the processed signal is output to the next stage of multi-bandwidth general modulation transmission processing module.
As shown in fig. 4, the multi-bandwidth general modulation transmission processing module further includes: a third control state machine, a parameter generating unit, a sampling pulse generating unit, an FIFO buffer unit and a general modulator; wherein:
the FIFO buffer unit is used for buffering the signal stream sent by the high-efficiency block Turbo coding and scrambling processing module; the interior of the FPGA provides high-power clock input for the FIFO cache unit;
the parameter generating unit is used for generating required parameters according to frame header judgment information sent by the high-efficiency block Turbo coding and scrambling processing module and sending the parameters to the sampling pulse generating unit and the third control state machine, wherein the parameters at least comprise L inkID synchronous heads, modulation modes, sampling pulse frequency control words and auxiliary counter parameters required by signal receiving;
the sampling pulse generating unit is used for generating sampling pulses required by modulation signal output under the driving of a high-power clock provided in the FPGA according to the sampling pulse frequency control word provided by the parameter generating unit and respectively sending the sampling pulses to the third control state machine and the general modulator;
the third control state machine is used for controlling the FIFO buffer unit to read and transmitting a signal stream to be input into a corresponding general modulator for modulation output according to the parameters generated by the parameter generating unit under the enabling of the sampling pulses provided by the sampling pulse generating unit;
and the general modulator is used for selecting different internal modulators according to modulation mode parameters and finally outputting modulation signals under the enabling of the sampling pulses provided by the sampling pulse generating unit, and the internal modulators at least comprise BPSK, QPSK, 1/4 pi QPSK, 8PSK and 16 QAM.
It should be noted that: the output frequency of the modulation signal is far lower than the data clock frequency and the high-power clock frequency, and the data signal is cached by the high-power clock for realizing the frequency output of the modulation signal specified by the VDE protocol. The module can generate required parameters such as sampling pulse frequency, modulation mode, symbol length, preamble code and the like according to different signal frame formats, and the state machine is divided into an initial waiting state, a preamble code sending state, a data reading and sending state, a data sending ending waiting state and a data sending ending state. The third control state machine reads the digital signal buffered in the FIFO and sends it to the general-purpose modulator, enabled with the pulse signal. The general modulator adopts single-rate constellation mapping according to different frame formats, then interpolates 16 times of FIR filter baseband signals, wherein different bandwidths correspond to different filter interpolation multiples, the filter output is interpolated by CIC, and then the filter output is sent to the general up-converter for up-conversion processing. QPSK, 1/4 pi QPSK, 8PSK and 16QAM modulation modes with different bandwidths required by the VDE protocol are realized.
The overall signal processing flow scheme of the low-delay VDE satellite-borne downlink digital signal processing system based on the FPGA meets the delay requirement required by the VDE standard protocol requirement and the hardware requirement of minimum satellite resource occupation.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (4)
1. A low-delay VDE satellite-borne downlink digital signal processing system based on FPGA is characterized by comprising: the system comprises a data blocking and high-speed forwarding module, a high-efficiency blocking Turbo coding and scrambling processing module and a multi-bandwidth general modulation transmitting processing module;
the data blocking and high-speed forwarding module is used for receiving the VDE satellite-borne downlink digital signal and performing operations of CRC (cyclic redundancy check) code addition, blocking processing and high-speed forwarding on the VDE satellite-borne downlink digital signal; if the VDE satellite-borne downlink digital signal is a short-bit frame format signal, the VDE satellite-borne downlink digital signal is directly forwarded to a high-efficiency block Turbo coding and scrambling processing module for subsequent processing without block processing; if the VDE satellite-borne downlink digital signal is an ultra-long bit frame format signal, block processing is carried out and the signal is forwarded to a high-efficiency block Turbo coding and scrambling processing module for subsequent processing;
the high-efficiency block Turbo coding and scrambling processing module is used for carrying out Turbo coding, punching and scrambling processing on the input short bit frame format signals or the super-long bit frame format signals which are finished in a block mode, and forwarding the signals to the multi-bandwidth general modulation transmitting processing module for subsequent processing;
the multi-bandwidth general modulation transmission processing module is used for identifying different frame formats of the input VDE satellite-borne downlink digital signals, carrying out modulation transmission processing according to corresponding transmission frequencies according to different modulation modes required by the frame formats, including BPSK, QPSK, 1/4 pi QPSK, 8PSK and 16 QAM.
2. The system of claim 1, wherein the data blocking and high-speed forwarding module further comprises: the device comprises a first control state machine, a 16bits FIFO buffer, a 16bit to 1bit serial conversion unit and a frame head extraction and CRC check code splicing unit; wherein:
the first control state machine is used for performing read-write control on the 16bits sFIFO buffer and performing state control on the 16-bit to 1-bit serial conversion unit and the frame header extraction and CRC (cyclic redundancy check) code splicing unit; the state control is specifically as follows:
controlling the data reading state of the serial conversion unit from 16bits to 1bit according to the data length;
finishing frame header information extraction and starting CRC (cyclic redundancy check) when frame data start, and finishing CRC to generate a CRC code when data end;
meanwhile, the first control state machine carries out blocking processing according to the length of a data frame and generates a blocking mark pulse, and the blocking mark pulse is sent to the high-efficiency blocking Turbo coding and scrambling processing module and used as a starting mark bit of a blocking signal;
the 16bits FIFO buffer is used for receiving a VDE satellite-borne downlink digital signal entering in a parallel 16bits form, buffering the input 16bits parallel signal flow and sending the 16 bits-to-1 bit serial conversion unit; the 16-bit sFIFO buffer is provided with a data writing clock, and the interior of the FPGA provides high-power clock input for the 16-bit sFIFO buffer;
a 16-bit to 1-bit serial conversion unit for converting the cached 16-bit parallel signals into 1-bit high-speed serial data and sending the 1-bit high-speed serial data to the frame header extraction and CRC check code splicing unit;
the frame head extraction and CRC check code splicing unit is used for receiving the 1-bit high-speed serial data sent by the 16-bit to 1-bit serial conversion unit and processing the data as follows, judging frame head information at the beginning of frame data, wherein the frame head information comprises a frame starting synchronization bit and a frame format code L inkID, generating required parameters according to L inkID when a subsequent module processes the data conveniently, and generating a CRC check code of a data stream at the same time so as to check the integrity of the data when a signal is received;
and the frame header extraction and CRC check code splicing unit sends the processed signal stream to the high-efficiency block Turbo coding and scrambling processing module.
3. The system of claim 2, wherein the high efficiency block Turbo coding and scrambling processing module further comprises: the device comprises a block judgment and parameter selection unit, a turbo coding unit, a second control state machine, a scrambling code adding unit and a coding and punching unit; wherein:
the block judgment and parameter selection unit is used for judging whether the signal stream input by the data block and high-speed forwarding module is subjected to block processing according to the block marking pulse provided by the ultra-long frame block marking pulse output unit, and generating parameter information required by turbo coding according to the frame format coding L inkID judged by the frame header, wherein the parameter information comprises the frame length, the block length and the coding rate;
a turbo coding unit for realizing turbo coding of different signal streams according to the parameters generated by the block judgment and parameter selection unit; the FPGA internal high-speed data processing clock provides high-power clock input for the turbo coding unit; the turbo coding unit inputs the processed signal stream into the coding and puncturing unit;
a second control state machine for judging whether the turbo coded signal stream is an effective enabling gap and finishing signal scrambling;
the scrambling adding unit is used for carrying out signal scrambling processing on the signal stream input into the coding and puncturing unit under the control of a second control state machine;
and the coding and punching unit is used for selectively outputting corresponding coding information to the next-stage multi-bandwidth universal modulation and emission processing module according to the frame length, the block length and the coding code rate in the parameters generated by the block judgment and parameter selection unit after turbo coding.
4. The system of claim 3, wherein the multi-bandwidth universal modulation transmit processing module further comprises: a third control state machine, a parameter generating unit, a sampling pulse generating unit, an FIFO buffer unit and a general modulator; wherein:
the FIFO buffer unit is used for buffering the signal stream sent by the high-efficiency block Turbo coding and scrambling processing module; the interior of the FPGA provides high-power clock input for the FIFO cache unit;
the parameter generating unit is used for generating required parameters according to frame header judgment information sent by the high-efficiency block Turbo coding and scrambling processing module and sending the parameters to the sampling pulse generating unit and the third control state machine, wherein the parameters at least comprise L inkID synchronous heads, modulation modes, sampling pulse frequency control words and auxiliary counter parameters required by signal receiving;
the sampling pulse generating unit is used for generating sampling pulses required by modulation signal output under the driving of a high-power clock provided in the FPGA according to the sampling pulse frequency control word provided by the parameter generating unit and respectively sending the sampling pulses to the third control state machine and the general modulator;
the third control state machine is used for controlling the FIFO buffer unit to read and transmitting a signal stream to be input into a corresponding general modulator for modulation output according to the parameters generated by the parameter generating unit under the enabling of the sampling pulses provided by the sampling pulse generating unit;
and the general modulator is used for selecting different internal modulators according to modulation mode parameters and finally outputting modulation signals under the enabling of the sampling pulses provided by the sampling pulse generating unit, and the internal modulators at least comprise BPSK, QPSK, 1/4 pi QPSK, 8PSK and 16 QAM.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115085745A (en) * | 2022-04-27 | 2022-09-20 | 北京理工大学 | VDE-TER-based digital diversity communication system |
| CN116015551A (en) * | 2022-12-28 | 2023-04-25 | 上海大学 | Signal separation method and device and electronic equipment |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113794670B (en) * | 2021-09-18 | 2023-08-22 | 上海航天电子通讯设备研究所 | Demodulation system of 16QAM signal in VDES |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010072570A1 (en) * | 2008-12-23 | 2010-07-01 | Secutanta Gmbh | Method for sending and receiving a data block |
| EP3128707A1 (en) * | 2015-08-07 | 2017-02-08 | Harris Corporation | Co-channel spatial separation using matched doppler filtering |
| CN206272651U (en) * | 2016-11-30 | 2017-06-20 | 成都国蓉科技有限公司 | A kind of modulator for VDE systems |
| CN206341240U (en) * | 2016-11-30 | 2017-07-18 | 成都国蓉科技有限公司 | A kind of demodulator for VDE systems |
| CN109710564A (en) * | 2018-11-27 | 2019-05-03 | 上海航天电子通讯设备研究所 | The large-scale wireless reconfiguration system of FPGA configurator based on VDES communication equipment |
| CN110351354A (en) * | 2019-07-04 | 2019-10-18 | 江苏运满舱科技有限公司 | The watercraft remote monitoring system communicated based on VDES and S-band |
| CN110380748A (en) * | 2019-07-25 | 2019-10-25 | 东南大学 | A kind of scrambled signals generation method |
| CN110581714A (en) * | 2019-09-17 | 2019-12-17 | 上海航天计算机技术研究所 | satellite full-duplex VDES system radio frequency receiver |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100389549C (en) * | 2002-06-11 | 2008-05-21 | 上海贝尔有限公司 | Downgoing baseband processing unit of WCDMA system |
| FR3002069A1 (en) * | 2013-02-13 | 2014-08-15 | France Telecom | METHOD AND DEVICE FOR PREDICTING PERFORMANCE OF A COMMUNICATION SYSTEM ON A TRANSMISSION CHANNEL |
| CN107204825B (en) * | 2016-03-16 | 2019-07-12 | 华为技术有限公司 | Data transmission method for uplink, data receiver method, sending ending equipment and receiving device |
| KR20180059274A (en) * | 2016-11-25 | 2018-06-04 | (주)지엠티 | Beamforming antenna control method for improve transmitting/receiving performance in tdma based wireless communication system, and wireless communication apparatus for performing the same |
-
2020
- 2020-03-18 CN CN202010193819.XA patent/CN111431579A/en active Pending
- 2020-11-30 CN CN202011377783.7A patent/CN112532306B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010072570A1 (en) * | 2008-12-23 | 2010-07-01 | Secutanta Gmbh | Method for sending and receiving a data block |
| EP3128707A1 (en) * | 2015-08-07 | 2017-02-08 | Harris Corporation | Co-channel spatial separation using matched doppler filtering |
| CN206272651U (en) * | 2016-11-30 | 2017-06-20 | 成都国蓉科技有限公司 | A kind of modulator for VDE systems |
| CN206341240U (en) * | 2016-11-30 | 2017-07-18 | 成都国蓉科技有限公司 | A kind of demodulator for VDE systems |
| CN109710564A (en) * | 2018-11-27 | 2019-05-03 | 上海航天电子通讯设备研究所 | The large-scale wireless reconfiguration system of FPGA configurator based on VDES communication equipment |
| CN110351354A (en) * | 2019-07-04 | 2019-10-18 | 江苏运满舱科技有限公司 | The watercraft remote monitoring system communicated based on VDES and S-band |
| CN110380748A (en) * | 2019-07-25 | 2019-10-25 | 东南大学 | A kind of scrambled signals generation method |
| CN110581714A (en) * | 2019-09-17 | 2019-12-17 | 上海航天计算机技术研究所 | satellite full-duplex VDES system radio frequency receiver |
Non-Patent Citations (4)
| Title |
|---|
| SYNCTECHNO INC., KOREAN REGISTER OF SHIPPING: "Interworking with VHF Data Exchange System", 《3GPP TSG-SA WG1 MEETING #82 S1-181115》 * |
| 向前: "星载高速数传的射频通道线性化技术研究", 《中国优秀硕士论文电子期刊网》 * |
| 王辉: "星载数字调制解调器设计", 《中国优秀硕士论文电子期刊网》 * |
| 魏文武: "VDE-SAT上下行链路信道估计的研究与仿真", 《中国优秀硕士论文电子期刊网》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115085745A (en) * | 2022-04-27 | 2022-09-20 | 北京理工大学 | VDE-TER-based digital diversity communication system |
| CN115085745B (en) * | 2022-04-27 | 2023-08-08 | 北京理工大学 | Digital diversity communication system based on VDE-TER |
| CN116015551A (en) * | 2022-12-28 | 2023-04-25 | 上海大学 | Signal separation method and device and electronic equipment |
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