CN114710234A - Multi-user data multiplexing super-frame coding modulation method - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000012545 processing Methods 0.000 claims abstract description 62
- 238000003780 insertion Methods 0.000 claims abstract description 54
- 230000037431 insertion Effects 0.000 claims abstract description 54
- 238000009432 framing Methods 0.000 claims abstract description 46
- 238000004891 communication Methods 0.000 claims abstract description 24
- 238000004422 calculation algorithm Methods 0.000 claims abstract description 23
- 238000012544 monitoring process Methods 0.000 claims abstract description 7
- 238000013507 mapping Methods 0.000 claims description 34
- 238000001914 filtration Methods 0.000 claims description 22
- 230000005540 biological transmission Effects 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 18
- 230000011664 signaling Effects 0.000 claims description 16
- 238000005070 sampling Methods 0.000 claims description 12
- 238000007493 shaping process Methods 0.000 claims description 12
- 230000004044 response Effects 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims description 5
- 230000010363 phase shift Effects 0.000 claims description 5
- 230000003139 buffering effect Effects 0.000 claims description 4
- 238000004364 calculation method Methods 0.000 claims description 4
- 239000000969 carrier Substances 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 5
- 238000005520 cutting process Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 230000000875 corresponding effect Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 238000010295 mobile communication Methods 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000006855 networking Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
The multi-user data multiplexing superframe frame coding modulation method disclosed by the invention has the advantages of high parallelism, high data throughput and easiness in cutting and expanding. The invention is realized by the following technical scheme: service data of a plurality of users are respectively input into a superframe framing coding modulator through a service data income interface of a satellite or a ground communication network, and data short frames of the plurality of users are digitally multiplexed to form a superframe; after the data is cached, a superframe processing module completes null frame insertion, command insertion, LDPC coding, superframe head insertion, superframe tail insertion and symbol scrambling in sequence under the control of a superframe circulation state of a superframe framing processing control state machine according to monitoring parameters, and is multiplexed together in sequence according to a certain speed series in an FPGA device according to a time division multiplexing basic principle, parallel code phase generation signals are sent to an orthogonal modulator, and orthogonal modulation is carried out on parallel carrier generation signals by using a modulation algorithm to generate digital intermediate frequency modulation signals.
Description
Technical Field
The present invention belongs to the field of physical layer framing of coding, modulator and multi-user multiplexing. The method is mainly applied to the field of satellite communication networks, and provides a multi-user data multiplexing superframe framing coding modulation method for satellite communication networks.
Technical Field
With the development of technologies such as space-based network (broadband networking between satellites) planning, high-resolution satellite reconnaissance, high-resolution satellite remote sensing, 5G mobile communication broadband millimeter wave communication and the like at home and abroad, a wireless broadband high-speed data rate transmission technology becomes a necessary enabling technology. The wireless high-speed communication technology is one of core technologies in the field of satellite communication, and the superframe framing technology is one of key technologies for a plurality of users of a satellite communication network to share satellite services. Data is transmitted over a network in very small units called frames (frames), which are made up of several parts, different parts performing different functions. The frames are shaped by a special software called network driver and then sent via a network card onto the network cable, through the network cable to their destination machine, the reverse process being performed at one end of the destination machine. The ethernet card of the receiving end machine captures these frames and tells the operating system that the frame has arrived and then stores it.
With the rapid development of internet technology, the demand of people for communication bandwidth is gradually increased. In broadband communication, satellite broadband mobile communication can provide a wider-coverage and seamless communication mode for the internet. At present, the transmission of satellite broadband mobile communication is facing the challenges of factors such as weather and the number of users increasing dramatically, and therefore, adaptive coded modulation technology needs to be applied to the satellite broadband mobile communication system. At present, the transmission rate of a relay satellite system reaches 600Mbps, the speed requirement of a civil high-resolution remote sensing satellite reaches 1.5Gbps, and the data transmission rate of a third generation satellite (TDRS-M/N) reaches 1.2 Gbps. Japanese ultra high speed Internet satellite provides two-way communication up to 1.2 Gbps. The backbone transmission link transmission requirement of the space-based network under study reaches several Gbps. For FDD mode, since downlink and uplink use different frequencies, all subframes on downlink frequency are used for downlink, and all subframes on uplink frequency are naturally used for uplink. The length of the uplink pilot time slot vUpPTS is 160chips and 125us, the length of the downlink pilot time slot vDwPTS is 96chips and occupies 75us, the total length of the v subframe is 6400chips and occupies 5ms, and the obtained chip rate is 1.28 Mcps. The multiframes used to convey control information consist of 51 base frames, which in turn make up a superframe, which may be 1326 TDMA base frames of 51X26 or 26X 51. LTE is divided into two different duplex modes, the most direct difference being the impact on the air interface radio frame structure, because FDD uses frequency to distinguish uplink and downlink, its unidirectional resources are continuous in time; TDD uses time to distinguish uplink and downlink, and its resources in one direction are discontinuous in time, and a guard time interval is needed to avoid interference between transmission and reception in both directions, so LTE designs respective frame structures for FDD and TDD, respectively. In order for the receiver to properly accept and check the transmitted frames, the sender must encapsulate the packets submitted by the network layer into frames, called framing, according to certain rules. The most common framing methods currently used are bit stuffing and violation coding. Generally, the maximum data that can be transmitted by a data link layer in an ethernet environment is 1518 bytes, some network cards may send some extra-long frames when a fault occurs, but such frames are generally discarded by intermediate devices or network cards capturing data packets, and a packet capture tool generally cannot normally display the frames. A very long frame format specifically designed for gigabit Ethernet varies in length from 9000 bytes to 64000 bytes. The super-long frame is generally applied more in the storage environment of the internal network. Assuming that a server sends a large number of super-long data packets in a short time, the IP identifiers of the super-long data packets are close to each other, when the server passes through a switch, the switch needs to convert the super-long data packets, one super-long data packet is converted into a plurality of conventional data packets, and when the switch performs the conversion, the switch needs to re-allocate IP identifiers to the converted conventional data packets (the IP identifier of the first data packet after the conversion is the IP identifier of the super-long data packet before the conversion, and the IP identifiers of the subsequent data packets are increased one by one). By comparing the IP identifications of the data packets, the server can set the corresponding IP identifications to be values which do not have conflict after conversion when the server generates the overlong data packets. In recent digital communications, the amount of information transmitted, such as digitized video, is large, and therefore, kbit/sec or kbps and Mbit/sec or Mbps are written in units of kilobits per second or megabits per second, respectively, in many cases. The amount of information transmitted through a channel per unit time is called the bit transfer rate, which is the unit of bits per second (b/s), referred to as bit rate (bitrate). Bit rate is often used in the field of communications as a synonym for connection speed, transmission speed, channel capacity, maximum throughput and digital bandwidth capacity. The higher the bit rate, the larger the data that is transmitted. Under the sub-frame, it is further subdivided into time slots. The slot and subcarrier spacing are strongly correlated: the smaller the subcarrier spacing, the longer the time slot, whereas the larger the subcarrier spacing, the shorter the time slot. Under the most popular 30KHz sub-carrier, a sub-frame contains 2 slots, each of which is 0.5 milliseconds in duration. Each slot contains 14 OFDM symbols. The symbol is the minimum unit of the time domain, and each symbol can carry different numbers of bits according to different modulation modes. The modulation is used to map the encoded data (a random combination of a series of 0's and 1's) to the smallest unit of the frame structure described above: on an OFDM symbol. The modulated signal can be transmitted out finally. Coding is a process on the last step of modulation, namely, redundancy is added on the basis of original data to be transmitted, and the redundancy is used for performing functions of error detection, error correction and the like. After coding, data to be transmitted is increased, and in order to represent the amount of redundant data increased by coding, the concept of code rate is introduced. The code rate is the number of bits before encoding/the number of bits after encoding.
There are two types of satellite communications, one of which is that of satellite television, such as the DVB standard, using hybrid multi-layer coding of BICM, QAM/PSK and orthogonal frequency division multiplexing OFDM, using long LDPC codes. The other is deep space satellite communication, which uses PPM, BICM-ID and LDPC code, or serial convolution turbo code. Based on the mixed multi-level coding (MLC) and Bit Interleaved Coded Modulation (BICM) scheme of the LDPC code, the perimeter of a ring is the number of edges contained in the ring, the ring with shorter perimeter influences the decoding performance, the existence of the short ring can lead the decoding to repeat iteration, influence the decoding efficiency and slow the decoding convergence speed, and compared with the traditional BICM scheme, the scheme can achieve better error rate performance and lower complexity. In a high-speed moving scene supported by B5G/6G, such as a high-speed train, V2V, a drone, satellite communication, etc., high-speed moving may generate a large doppler shift, and at this time, orthogonality between OFDM subcarriers may be seriously damaged, resulting in a rapid performance degradation. And the traditional coding algorithm has the problems of large calculation amount and incapability of keeping up with the real-time coding speed.
The wireless network needs to increase the network speed and mainly depends on the following 4 weapons: frequency bandwidth, frame structure, modulation coding, multiple input multiple output, MIMO. MIMO relies mainly on simultaneous transmission of multiple different data paths over the air to increase network speed by a factor of two. Downlink MIMO depends on the number of transmit antennas at the base station and the number of receive antennas at the handset. The LDPC code is a linear block code defined by a check matrix H with N-K rows and N columns, where N is a codeword length (code length for short), K is an information bit length, M is N-K, which is generally called a check bit length, and a corresponding code rate R is K/N. The H matrix consists of elements 0 or 1, each row of which represents a check equation. The number of the check nodes is N-K in the Tanner graph; each column represents one information bit, is called as variable node in the Tanner graph, and has N total; the non-zero elements in the H matrix represent the connection relationships between the check nodes of the row in which they are located and the variable nodes of the column in which they are located, which are called edges in the Tanner graph. Generally, at least 1 key frame per second of video needs to be used. Increasing the number of critical frames improves quality, but increases both bandwidth and network load. It should be noted that there is a limit to improve the image quality by increasing the GOP value, and when a scene switch occurs, the h.264 encoder automatically enforces to insert an I frame, and the actual GOP value is shortened. On the other hand, in a GOP, P, B frames are predicted from an I frame, and when the image quality of the I frame is poor, the image quality of the P, B frames following the GOP will be affected, and the GOP value cannot be set too large until the next GOP begins. Meanwhile, since P, B frames are more complex than I frames, too many P, B frames affect coding efficiency, which decreases coding efficiency. In addition, an excessively long GOP affects the response speed of the Seek operation, since P, B frames are predicted from the previous I or P frame, the Seek operation needs to be directly positioned, when decoding a certain P or B frame, the I frame and the previous N predicted frames in the GOP need to be decoded first, and the longer the GOP value is, the more predicted frames need to be decoded, and the longer Seek response time is. Combining the two fields as a frame to be coded (frame mode), or respectively coding the two fields (field mode) or combining the two fields as a frame, but the difference is that two vertically adjacent macro blocks in the frame are combined into a macro block pair to be coded; due to the fact that the number of video frames is large, splicing errors are large easily caused when video sequences are spliced, and time consumption is large. In the parallel pipeline type, the following problems occur in h.264 decoding, and the consumed time of each functional part is different, which depends on the actual code stream data, and the throughput of processing data depends on the most time-consuming part. If the throughput-only problem is that the pipeline can be optimized by adopting a buffering mode (once a core finishes the task of one frame, the task result is buffered, and if the previous step of the next frame is finished, the next frame processing is started immediately), however, the problem is that in the prediction processing, the inter macro block part needs to be subjected to motion compensation, namely, the other frames need to be relied on, which means that the processing of the current frame can be started after the frame relied on by the inter macro block part is completely decoded, and thus the parallel method of the pipeline type is complicated. The extension of parallelism is limited. Due to the above disadvantages, this implementation is not generally adopted in h.264 parallel decoder implementations. In h.264, the B Frame can be used as a reference Frame, in which case the Frame-level parallel algorithm cannot be performed. One solution is to specify B frames as no reference frames during encoding (actually x264 does not use B frames as reference frames when parallel encoding is turned on), but this encoding method will result in increased code stream. The number of slices in a frame is determined by the encoder and is generally not too large. Most of h.264 videos on the network have one slice in one frame, which causes the effect of the slice-level parallel algorithm to be lost. Although the slices are independent, the slice boundary can be exceeded in deblocking filtering (which is optional in encoding), and deblocking filtering must be performed according to a normal video sequence order, which reduces the speed of the slice-level parallel algorithm. The main disadvantage of using multiple slice coding is that the video rate increases. Generally, a frame has only one slice, if the number of slices in a frame is increased, the obvious influence is that slice boundaries are increased, and the slice boundaries cannot be crossed during intra-inter prediction of a macro block. In addition, the increased number of slices means that there are more slice _ headers and start codes. The basic structure of the FPGA in the prior art is developed very rapidly, and various structures are formed. The FPGA is divided into a fine-grained FPGA and a coarse-grained FPGA according to the size of the logic function block. The logic function block of the fine-grained FPGA is small. However, the multi-frame splicing method and the analog implementation method adopted in the prior art have the disadvantages that the multi-frame splicing method needs to be combined with a modulation and demodulation technology, a sub-band is pre-allocated to each user, and each user monopolizes the sub-band, so that the transmission capability of a line cannot be fully utilized. The analog implementation method has the disadvantages that only a simple frame structure can be spliced, the digital multiplexing cannot be performed to form a superframe and a complex superframe structure, and the method has poor performance, low frequency spectrum efficiency and time efficiency, complex and huge equipment and is not suitable for satellite-ground high-speed broadband application.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and aims to provide a multi-user data multiplexing superframe frame coding modulation method which is flexible, convenient, high in stability, low in resource consumption, high in data throughput, capable of solving the contradiction between high-speed implementation and high complexity, between parallel implementation and high resource consumption and capable of effectively supporting multiple modes.
The above object of the present invention can be achieved by the following measures, a superframe framing coding modulation method of a multi-user data multiplexing superframe frame coding modulation method of a satellite-ground wireless digital transmitter has the following technical characteristics: a plurality of users share a transmission line resource, service data of the users are respectively input to a superframe framing coding modulator of a satellite wireless digital transmitter or a gateway station wireless digital transmitter through a satellite or ground communication network service data income interface, data short frames of the users are digitally multiplexed to form a superframe according to different requirements of Qos, instantaneity, transmission rate, error code performance and the like, and multi-user ultralong frame framing multiplexed data stream information is sent to a superframe data buffer for buffering; after the data is cached, a superframe processing module completes empty frame insertion, command insertion, LDPC coding, superframe head insertion, superframe tail insertion and symbol scrambling in sequence under the control of a superframe cycle state of a superframe framing processing control state machine according to monitoring parameters, full-digital parallel pipeline structure superframe framing coding is realized in an FPGA device, a superframe framing coding modulator is multiplexed together in sequence according to a certain speed series according to different modulation mode requirements and according to a time division multiplexing basic principle, and the data is sent to a high-speed digital-to-analog converter DA to complete digital-to-analog conversion and is combined into a high-speed digital code stream after modulation symbol mapping, symbol interpolation and shaping filtering, digital intermediate frequency orthogonal modulation and superframe processing are completed; storing the superframe in a superframe data buffer, and then sequentially performing by a data bit width conversion module: the method comprises the steps of carrying out symbol mapping in an 8PSK (phase shift keying), QPSK (phase shift keying) or BPSK (binary phase shift keying) modulation mode, sending a parallel code phase generation signal to an orthogonal modulator through a symbol interpolation and shaping filtering module, carrying out orthogonal modulation on a parallel carrier generation signal by using a modulation algorithm to generate a digital intermediate frequency modulation signal, outputting a modulation signal of a parallel low-voltage differential signal LVDS (low voltage differential signaling) to a high-speed analog-to-digital converter DA (digital to analog converter) after orthogonal debugging, and outputting the intermediate frequency modulation signal.
Compared with the prior art, the invention has the following beneficial effects
The invention adopts the business data of the user to be input through the interface and cached in the data buffer; the generation of the superframe is sequentially completed under the control of a superframe circulating state machine: null frame insertion (as needed), command insertion, LDPC encoding, superframe header insertion (as needed), superframe tail insertion (as needed), symbol scrambling. After the superframe processing is finished, the data is buffered, and is sent to a high-speed DA after symbol mapping, symbol interpolation and shaping filtering and orthogonal modulation are carried out according to different modulation mode requirements. The full digital scheme optimizes the realization structure on the whole by the algorithm processing of the transmitter, and derives the high-efficiency parallel flow realization structure by deducing the parallelization realization algorithm of the traditional algorithm. It can be known that various modulation, coding, scrambling, code pattern coding, differential coding and data frame structures which are commonly used at present are supported, the output intermediate frequency can be set at will under the condition that the DAC sampling rate is divided by 2.5, and the theoretical value of the modulation rate can reach 4.8Gbps under the condition that a 150MHz FPGA clock is adopted (for example, a higher modulation rate can be obtained by adopting a higher FPGA clock, and the 200MHz clock is 6.4 Gbps). The method has the advantages of strong support function, flexible (configurable and reconfigurable) equipment, resource saving, high parallelism, good optimization on the realization structure, large data processing throughput, low system complexity and low resource consumption.
The invention adopts the data of an LDPC code block with excellent characteristics which can approach to the Shannon limit as the basic signal processing granularity, provides control information by counting the code block number obtained by the LDPC code block, and decides according to the code block number: the method has the advantages of simple description, higher flexibility, lower error code character, parallel operation realization, low decoding complexity, suitability for hardware realization, high throughput and great potential of high-speed decoding, can still effectively decode under the condition of longer code length, and the computation amount cannot be increased sharply due to the increase of the code length. The coding gain higher than that of the linear block code can be obtained under the same complexity; the transmission efficiency of the system can be improved, the problem of huge decoding calculation complexity of the block code in long code is solved, and the application of long code blocks becomes possible. The physical layer superframe frame structure with the length of 17958400 symbols can be formed by inserting superframe structures before and after the current LDPC code block to fill contents and different combinations of a superframe header, the LDPC code block, a data subframe, subframe filling and a frame tail. The encoding formats of 1/2, 3/4 and 7/8 with the frame length of 1008 bytes can be realized through LDPC, the byte number of the user load in 1008 byte code words of 1/2, 3/4 and 7/8 code rate encoders is 493 bytes, 743 bytes and 871 bytes respectively, because the LDPC encoder adopts an encoder with the input and the output of 16bit wide, the required throughput can be realized by adopting a single encoder, and FPGA logic resources are saved.
Firstly, storing service data input with 32bit width in a cache, reading out the service data from the cache according to 8bit width, performing superframe framing processing, storing the data after superframe framing in a data cache, reading out 24bit, 16bit and 8bit widths respectively according to different modulation modes, sending the data to a symbol mapping module for modulation constellation mapping, sending 8-path parallel 8bit width data to a symbol interpolation and forming filtering module by a symbol mapper, performing symbol interpolation up-sampling and baseband forming filtering, sending 40-path parallel 12bit width data to an orthogonal modulator for modulation, and generating 40-path parallel 12bit width orthogonal carrier signals sin and cos by a generator of a parallel carrier; and after orthogonal debugging, outputting 4 paths of parallel 12-bit-width LVDS modulation signals to a high-speed DA. The LDPC coding method adopts a full-digital parallel pipeline algorithm structure, supports various modulation modes such as 8PSK, QPSK, OQPSK and BPSK, and supports LDPC coding of various modes. The method supports a plurality of modulation and coding modes, and compared with the traditional method which adopts a multi-frame splicing method and a simulation implementation method, the method has the advantages of optimized algorithm structure, easy cutting and expanding of physical layer superframe framing, optimized algorithm and implementation structure, small complexity, low resource consumption and better performance.
The invention starts from the overall design, and takes a command generation and response state machine as a control scheduling center and a complex data flow control manager for superframe generation; the super frame data required before and after each LDPC code block formed by the super frame is controlled by the super frame data, the super frame is sent according to the LDPC code block, and the insertion content of the super frame is controlled to be added in front of or behind the LDPC code block according to the requirement of the super frame; the superframe data buffer is managed, and the data streams of the former superframe framing and the latter modulator are ensured to flow in and out without errors. The frame splitting and combining processing with reasonable structure realizes the conversion of the parallelism of 8-bit width and 32-bit width, can be expanded into various different interface width modes, and has universality. To achieve the necessary data bit width conversion between block coding and successive coding,
the invention decomposes the baseband bit data of each constellation point into parallel 1, 2 and 3 paths by scrambling of three modulation modes of BPSK, QPSK and 8PSK, then scrambles the parallel branches by respectively adopting the same PN, and combines the parallel branches into one path for output after scrambling; PN codes for scrambling are respectively parallelly generated by 8 bits to interpolate 40 paths of parallel symbols, so that the technology is simplified, the symbol interpolation of any oversampling multiple can be supported, and the interpolation parallelism can be easily reduced and increased by 32 paths, 40 paths, 48 paths and the like in the parallel paths in the engineering project according to the adopted DA sampling rate. Because the intermediate frequency carrier frequency, the modulation rate and the like are completely parameterized, the frequency value of the intermediate frequency carrier frequency under the DA sampling rate divided by 2.5 times can be set at will by controlling corresponding parameters, and the modulation bit rate under 4.8Gbps is continuously variable according to bit stepping. The engineering project can adopt intermediate frequency carrier frequencies of 600MHz, 720MHz, 1.2GHz, 1.5GHz and the like, and can modulate the application range of 5 Mbps-2 Gbps bit rate. The physical layer superframe frame structure, the superframe frame head, the superframe tail and the data subframe, including signaling, frame counting and tail filling of the data subframe, can be utilized to flexibly support multiplexing and aggregation of satellite multi-user data;
2) the data of an LDPC code block is used as the basic signal processing granularity, the LDPC code block is counted and command numbers are provided to control whether a super frame structure is inserted before and after the current LDPC code block and the content needs to be filled, such as a super frame head, a super frame tail, signaling, data subframe tail filling, scrambling initial phase reset time and the like; 3) the LDPC adopts an encoding format of 1/2, 3/4 and 7/8 code rates with the frame length of 1008 bytes; 4) the scrambling mode adopts a symbol scrambling mode that a plurality of bits of each symbol are scrambled in parallel by adopting the same PN code; 5) the complex data flow control mode adopts a parallel, pipelining and complex state machine to manage the superframe data buffer, and ensures that the data flows of the superframe framing in the front and the modulator in the rear can flow in and out without errors; 6) the carrier generation, symbol interpolation and orthogonal modulation algorithm adopt a 32-path parallel pipeline algorithm to realize a structure, support multiple modulation modes such as BPSK, QPSK, 8PSK and the like, and the maximum modulation rate reaches 1200 Mbps. The core of the invention is that: the LDPC code blocks are used as the basic granularity of signal processing, the processing content of each superframe processing module is controlled through the LDPC code block number in the frame structure, rich logic resources of FPGA are utilized, and a highly parallel superframe processing, modulation, interpolation, coding structure and algorithm are adopted, so that a high-speed data processing task with high throughput and a gigabit level is broken through; the technical problems that the intermediate frequency and the symbol rate are continuously variable in a large range, the parallelism is easy to cut and expand and the like are solved. The invention has wide application prospect in the broadband communication field of satellite communication network, space measurement and control, remote sensing, aviation, data link and the like, and has been applied in the actual engineering system.
The invention transmits through the high-speed wireless broadband link, the advantage of carrying on the multi-frame splicing method on the figure is flexible and convenient, the stability is high, can form the complicated superframe structure; the transmitter is suitable for the fields of space measurement and control, space-based networking, high-resolution satellite remote sensing, ground-air broadband communication, unmanned aerial vehicle broadband communication, military broadband data links and the like. The method can be applied to transmitters of high-speed communication networks and data chains among satellites, between satellites and between the ground, between the ground and the air.
Drawings
In order that the invention may be more clearly understood, it will now be described by way of example with reference to the accompanying drawings, in which:
FIG. 1 is a block diagram of a multi-user data multiplexing superframe frame code modulation system according to the present invention;
fig. 2 is a schematic diagram of the superframe protocol structure of the present invention;
fig. 3 is a schematic diagram of superframe processing according to the present invention; realizing a structure diagram;
FIG. 4 is a schematic diagram of the parallel scrambling principle of the present invention; realizing a structure diagram;
fig. 5 is a state transition diagram of the command generation and response state machine of the present invention controlled by the superframe framing process of fig. 1.
Detailed Description
See fig. 1. According to the invention, a plurality of users share a transmission line resource, the service data of the users are respectively input to a superframe framing coding modulator of a satellite wireless digital transmitter or a gateway station wireless digital transmitter through a satellite or ground communication network service data receiving interface, the data short frames of the users are digitally multiplexed to form a superframe according to different requirements of Qos, instantaneity, transmission rate, error code performance and the like, and multi-user ultralong frame framing multiplexing data stream information is sent to a superframe data buffer for buffering; after the data is cached, a superframe processing module completes empty frame insertion, command insertion, LDPC coding, superframe head insertion, superframe tail insertion and symbol scrambling in sequence under the control of a superframe cycle state of a superframe framing processing control state machine according to monitoring parameters, full-digital parallel pipeline structure superframe framing coding is realized in an FPGA device, a superframe framing coding modulator is multiplexed together in sequence according to a certain speed series according to different modulation mode requirements and according to a time division multiplexing basic principle, and the data is sent to a high-speed digital-to-analog converter DA to complete digital-to-analog conversion and is combined into a high-speed digital code stream after modulation symbol mapping, symbol interpolation and shaping filtering, digital intermediate frequency orthogonal modulation and superframe processing are completed; storing the superframe in a superframe data buffer, and then sequentially performing by a data bit width conversion module: the 8PSK or QPSK or BPSK modulation mode symbol mapping is realized, parallel code phase generation signals are sent to an orthogonal modulator through a symbol interpolation and shaping filtering module, orthogonal modulation is carried out on parallel carrier generation signals through a modulation algorithm to generate digital intermediate frequency modulation signals, data after orthogonal debugging are output, modulation signals of parallel low-voltage differential signals LVDS are sent to a high-speed analog-to-digital converter DA, and the intermediate frequency modulation signals are output.
The superframe processing module adopts three modulation modes of BPSK, QPSK and 8PSK to scramble, PN codes are used for generating scrambling in parallel by 8 bits respectively, baseband bit data of each constellation point are decomposed into parallel 1, 2 and 3 paths, then the parallel branches are scrambled by the same PN respectively, and the parallel branches are combined into one path for output after scrambling.
The FPGA device adopts a full-digital parallel pipeline structure coding and modulation algorithm to realize superframe framing, realizes data interfaces with different bit widths through a plurality of double-port RAMs with different bit widths, and performs flow control management on the whole data processing process; the data superframe framing part adopts a complex command generation state machine and a command response state machine, takes an LDPC code block as a unit, adds a frame head and a frame tail in front of and behind the LDPC code block according to the protocol requirement, and forms 274 data subframe structures by filling 8 LDPC code blocks, and finally forms a superframe with the length of 17958400 symbols; the code algorithm part realizes 1/2, 3/4 and 7/8 LDPC codes with different code rates and symbol scrambling of BPSK, QPSK and 8PSK with different debugging modes, the modulation algorithm part adopts 8 bits of data bit width, 40 paths of parallel symbol interpolation with 12 bits of data bit width are adopted based on parameterized parallel symbol interpolation and parallel carrier, and the carrier generates 40 paths of parallel orthogonal modulation signals with 12 bits of data bit width.
In the FPGA device, a superframe framing processing control state machine generates a state machine command and a response state machine command based on FPGA, data with an LDPC code block as a unit is used as basic signal processing granularity according to protocol requirements, frame head frame tails are added in front of and behind the code block, 8 low-density parity check LDPC code blocks are added and filled to form a data subframe structure, a code word of an n-dimensional vector m is generated, a superframe with output bit width symbols of which the lengths reach phase shift keying PSK, QPSK and BPSK are respectively 24bit, 16bit and 8bit is formed, then service data input by 32bit is read out from a cache stored in a superframe data cache according to the bit width of 8bit, and superframe framing processing is carried out. The LDPC code block multiplies an information vector m to be coded by a sparse matrix H to obtain an intermediate result S, then repeatedly accumulates the intermediate result S to obtain a check bit, and finally combines the information bit and the check bit to obtain a final code word.
The superframe processing module takes a command generation and response state machine as a control scheduling center for superframe generation and a complex data flow control manager; controlling superframe data to be inserted before and after each LDPC code block formed by superframes, carrying out superframe transmission according to the LDPC code blocks, and controlling the insertion content of the superframes to be added in front of or behind the LDPC code blocks according to the requirements of the superframes; the superframe data buffer is managed to ensure error-free ingress and egress of data streams both to the preceding superframe framing and to the following modulator.
The data bit width conversion module reads out cache data in a superframe data buffer with bit widths of 24 bits, 16 bits and 8 bits respectively according to different modulation modes, the cache data are sent to a symbol mapping module for modulation constellation mapping, the symbol mapping module sends 8 paths of parallel 8-bit-width data to a symbol interpolation and shaping filtering module, symbol interpolation up-sampling and baseband shaping filtering are carried out according to the phase generation of an input parallel code clock, interpolation shaping data are sent to an orthogonal modulator for modulation according to 40 paths of parallel 40-bit-width data, and a generator of parallel carriers generates 40 paths of parallel 40-bit-width orthogonal carrier signals, orthogonal carrier sin signals and orthogonal carrier cos signals; and after orthogonal debugging, outputting 4 paths of parallel 40 × 112bit wide LVDS modulation signals to a high-speed DA, and finally outputting intermediate frequency modulation signals.
The superframe framing processing control state machine provides control information by adding code block numbers obtained by counting LDPC code blocks in a data subframe structure formed by filling, and decides according to the code block numbers: whether a superframe head, a superframe tail, signaling, data subframe tail filling, scrambling initial phase resetting and other contents which need to be filled in the superframe structure are inserted in front of and behind the current LDPC code block or not is respectively combined through the superframe head, the LDPC code block, the data subframe, the subframe filling and the frame tail to form a physical layer superframe frame structure with the length of 17958400 symbols.
The data bit width conversion module respectively reads and reads out data with 24bit, 16bit and 8bit data bit width from the superframe data buffer according to different modulation modes, the data with 24bit, 16bit and 8bit data bit width are respectively input to the symbol mapping module for modulation constellation mapping, 8 paths of parallel constellation mapping are output through the 8PSK, QPSK and BPSK mapping modules to obtain LUT data symbols and different coding modes, and mapping is carried out to obtain mapping constellation point complex data I + j Q with the output bit width of 8 bit. I + j Q. The symbol mapping module sends 8 paths of parallel 8-bit-wide data to a symbol interpolation and forming filtering module for symbol interpolation up-sampling and baseband forming filtering, the symbol interpolation and forming filtering module sends 40 paths of parallel 12-bit-wide data interpolation forming data to an orthogonal modulator for modulation, and a generator generates 40 paths of parallel carrier 12-bit-wide orthogonal carrier signals sin and cos; and after different branches and clocks are switched, a set accumulated value is continuously added from head to tail, and the accumulated value of the phase word is obtained by calculating the modulation symbol rate.
The orthogonal modulator adopts 40 parallel orthogonal carrier sin and cos circuits, a FPGA processes a clock cycle to obtain parallel 40-point contact carrier digital sampling points with continuous phases, phase parallel calculation and parallel updating of a parallel lookup table are carried out according to the 40 generated parallel carrier sampling points, parallel orthogonal modulation is carried out on 40 paths of real parts and imaginary parts, parallel multiplication of 40 paths of parallel symbol waveforms and carriers is respectively completed through parallel multipliers, parallel corresponding summation is output by the parallel multipliers, 40 paths of parallel modulation signal output is finally obtained, and data output after orthogonal debugging is 4 paths of parallel 12-bit-wide LVDS modulation signals and is sent to a high-speed digital-to-analog converter DA.
See fig. 2. The superframe header and the superframe body form a superframe with the superframe length of 17958400 symbols, wherein the superframe header is all 1 and the superframe header is 1536 symbols; the superframe body consists of 274 data subframes, which are 17956864 symbols long; each data subframe length 131072 symbols; each data subframe contains a plurality of LDPC code blocks arranged in the order LDPC code block 1, LDPC code block 2 … LDPC code block n, the data subframe evenly divides less than a partial fill of one LDPC code block by all 1.
The content of the LDPC code block padding mainly includes: the length of the unique word is 4 bytes, the content is that virtual channel protocol data units (VC-PDU) from a virtual channel access layer (VCA) are added with 4-byte frame synchronous codes 1ACFFC1D specified by CCSDS, virtual channel marks with the length of 1 byte, effective data length with the length of 2 bytes, virtual channel frame counting with the length of 4 bytes, a data area with the length of 997 bytes and LDPC check codes; the empty frame without padding data is X '00', the padding data is X '01', the signaling is X '02', the padding is carried out according to the effective data length in the actual coding block, the virtual channel counting length is 4 bytes, the length of the data area changes according to different coding modes, 493 bytes, 743 bytes and 871 bytes are respectively used for 1/2, 3/4 and 7/8 coding modes, the LDPC check code length changes according to different coding modes if the dummy frame is padded FF, and 504 bytes, 252 bytes and 126 bytes are respectively used for 1/2, 3/4 and 7/8 coding modes.
See fig. 3. In the superframe processing, according to data cache and data cache null detection, null frame insertion processing and signaling insertion processing are carried out, and through an encoder interface, a parallel 1/2 code rate LDPC encoder, a 3/4 code rate LDPC encoder and a 3/4 code rate LDPC encoder are adopted to carry out superframe header insertion and symbol scrambling in different modulation modes; in the empty frame insertion processing, an empty frame insertion module receives an empty frame insertion signal, completely fills the data area of the current LDPC code block into FF, fills a virtual channel mark into X00, and reads data from a data cache area for framing if the empty frame insertion mark is not received; in the signaling insertion processing, based on superframe framing state control and parameters and monitoring parameters, a signaling control word with the unique word length of 4 bytes, the effective data length of 2 bytes, the virtual channel mark length of 1 byte, the virtual channel counting length of 4 bytes and the content of 4-byte frame synchronization code 1ACFFC1D is inserted in front of a data area, the padding data is X '01', the signaling is X '02', the empty frame without the padding data is X '00', and filling is carried out according to the effective data length in an actual coding block. In the LDPC coding, an LDPC code block adopts three modes of transmitted data bits 1 and 0, carrier phase 225 degrees and +45 degrees according to the relation between the data bits and the output carrier phase of a BPSK modulator, and the length of a frame of the USB equipment interface IPcore coding based on the FPGA is 1008 bytes; in the insertion of the superframe header, when a superframe header insertion control signal is received, inserting all 1 of 1536 symbols in front of a currently input LDPC code block, and directly outputting data if no control signal exists; in the symbol scrambling, after the scrambled data is buffered and converted in bit width, the data is sent to a symbol mapping module to be subjected to BPSK, QPSK and 8PSK modulation mapping respectively according to the controlled modulation mode, after modulation mapping, symbol interpolation and shaping filtering processing are carried out, then orthogonal modulation is carried out, the modulated data is sent to a high-speed DA, according to different current modulation modes, scrambling methods are different, and the realized parallel structures are different, wherein BPSK is 8bit, QPSK is 16bit, and 8PSK is 24 bit.
In the null frame detection, the service data of the user input in real time is temporarily cached in a data cache to be used for framing, the data null detection detects the number of unsent data in the cache in real time, and if the number of the cached data is detected to be less than the number of data required by one LDPC code, and the length of a data area, a difference null frame signal is sent to a null frame insertion module.
For BPSK modulation, performing superframe header insertion and superframe tail insertion through the relationship between the data bits transmitted by the coding interface and the phase of the carrier output by the modulator to complete BPSK symbol scrambling; for QPSK modulation and 8PSK modulation, data bits are transmitted through an I branch and a Q branch, and the transmitted data bits 111, 101, 100, 110, 011, 001, 000 and 010 are subjected to 8-to-16 conversion and 8-to-24 conversion, so that QPSK symbols and 8PSK symbol scrambling are completed; the modulator outputs QPSK16 bits bie and 8PSK24-bit corresponding to carrier phases 270 °, +315 °, +90 °, +135 °, +225 °, +0 °, +45 °, +180 °.
The focus of the present invention is on the superframe implementation method, and therefore the photocopy frame in the bitmap is emphasized. The operation processing action of each module of the superframe processing is controlled by a control signal sent by a state machine, and the timing relation of various control signals and the sending time of a control word are generated by the state machine, which is specifically shown in fig. 5.
See fig. 4. The operation processing action of each module of superframe processing is controlled by a control signal sent by a state machine, the state machine outputs 1bit in each clock cycle, the timing relation of various control signals and the sending time of a control word are generated from a serial scrambling structure to a parallel scrambling structure, feedback structure linear shift registers D0, D1, D2, D3, … D7, D8, D9, … D22, D23 and D24 are adopted, PN codes of the serial scrambling structure are given, initial phases are used as PN codes of all 1 registers to generate parallel PN0, PN1, PN2 and PN3 … PN7, the binary XOR combinational logic XOR chain structure is adopted, scrambling positions are coded symbols + are scrambled by modulo 2, and a scrambling polynomial is adopted: x25+X3+1, scrambling the whole superframe, wherein D0-D24 are registers. The present embodiment adopts the following 8-bit parallel output structure, and outputs 8 bits per clock cycle. In the figure, D0-D24 are registers.
The state machine utilizes the values of D0-D24 in the registersThe shift register moves 8 bits in one clock cycle, 8-bit PN codes are calculated through iteration, and 8-bit PN code generation is realized in parallel in one clock cycle. Based on the condition that the feedback shift structure is no longer sequential shift, the following relation of feedback shift is adopted: D0-D7 are PN 0-PN 7, D8-D24 are D0-D16, and the serial scrambling structure and the scrambling polynomial X in the figure are based on25+X3+1, deducing the following 8-bit parallel coding structure:
in the formula (I), the compound is shown in the specification,
indicating mod2 addition, i.e., exclusive or.
In the practical scrambling, the state machine is based on that 1 symbol of BPSK is 1bit, 1 symbol of QPSK is 2bit, 1 symbol of 8PSK is 3bit and 1bit to form a symbol of BPSK, the bit of one symbol is scrambled by the same PN code, the 8bit data according to the input BPSK is R0-R7, and the use of the input BPSK
Obtaining scrambled data PNR 0-PNR 7;
based on setting 16-bit data of input QPSK as R0-R15 and 2-bit to form a symbol of QPSK, the following formula is adopted:
the data after scrambling are obtained from PNR0 to PNR15,
according to the 24-bit data input into the 8PSK, R0-R23 and 3 bits form a symbol of the 8PSK, the following formula is adopted:
the scrambled data are obtained from PNR 0-PNR 23, and the symbol scrambling processing of 3 different modulation modes can be completed by the formula and the parallel PN code generating structure.
See fig. 5. The state machine as the control scheduling center of superframe generation sends a reset monitoring command, after reset, the first LDPC code block is sent when St is 1, after reset clearing, the command number with cmd being 1 is sent after delaying waiting T0 time, cmd is 1, in fig. 1, the service data buffer end sends the pre-coding data of 1 LDPC coding code block without performing super-frame tail insertion, then, after superframe processing such as null frame insertion, signaling insertion, LDPC encoding, superframe header insertion, symbol scrambling and the like is performed in sequence, after waiting for T1, a command number with cmd 2 is sent, after cmd 2, in fig. 1, the service data buffer sends the pre-coding data of 1 LDPC code block, and still does not perform superframe tail insertion, then, the superframe processing process of operations such as hollow frame insertion, signaling insertion, LDPC coding, superframe header insertion, symbol scrambling and the like in the figure 1 is carried out in sequence; after waiting for the delay T2, entering the state of the super-frame intermediate LDPC code block, and making a state transition to St 2, and after St 2, as long as St is not the last LDPC code block of the data subframe, performing the following operations: 1) delaying waiting for T3 time, sending a command cmd ═ St +1, and modifying a command word; 2) delaying to wait for T4, wherein St is St +1, modifying a state word, judging whether the state word is the last LDPC code block of the data subframe, and continuing to stay in the LDPC code block state in the middle of the superframe; waiting T3 for the delayed modification control word; if not, entering the LDPC code block state at the end of the data subframe.
The delay parameters mentioned above are used by a delay timer, cleared each time the state St changes, re-timed,
t0 ═ 32 (fixed value), number of clock cycles
T1-super frame header length +1 LDPC code block length + inter-frame space length, clock period number
T2 modulation memory output data byte is super frame header length +1 LDPC code block length, counter count value
T3 ═ 1 LDPC code block length + interframe space length, number of clock cycles
T4 modulation memory output data byte 1 LDPC code block length, counter count value
T5 ═ 1 LDPC code block length + subframe filler length + interframe space length, clock period number
T6 ═ 1 LDPC code block length + subframe pad length, counter count value.
Claims (10)
1. A multi-user data multiplexing superframe frame coding modulation method has the following technical characteristics: a plurality of users share a transmission line resource, service data of the users are respectively input to a superframe framing coding modulator of a satellite wireless digital transmitter or a gateway station wireless digital transmitter through a satellite or ground communication network service data income interface, data short frames of the users are digitally multiplexed to form a superframe according to different requirements of Qos, instantaneity, transmission rate, error code performance and the like, and multi-user ultralong frame framing multiplexed data stream information is sent to a superframe data buffer for buffering; after the data is cached, a superframe processing module completes empty frame insertion, command insertion, LDPC coding, superframe head insertion, superframe tail insertion and symbol scrambling in sequence under the control of a superframe cycle state of a superframe framing processing control state machine according to monitoring parameters, full-digital parallel pipeline structure superframe framing coding is realized in an FPGA device, a superframe framing coding modulator is multiplexed together in sequence according to a certain speed series according to different modulation mode requirements and according to a time division multiplexing basic principle, and the data is sent to a high-speed digital-to-analog converter DA to complete digital-to-analog conversion and is combined into a high-speed digital code stream after modulation symbol mapping, symbol interpolation and shaping filtering, digital intermediate frequency orthogonal modulation and superframe processing are completed; the superframe is stored in a superframe data buffer, and then a data bit width conversion module sequentially performs: the 8PSK or QPSK or BPSK modulation mode symbol mapping is realized, parallel code phase generation signals are sent to an orthogonal modulator through a symbol interpolation and shaping filtering module, orthogonal modulation is carried out on parallel carrier generation signals through a modulation algorithm to generate digital intermediate frequency modulation signals, data after orthogonal debugging are output, modulation signals of parallel low-voltage differential signals LVDS are sent to a high-speed analog-to-digital converter DA, and the intermediate frequency modulation signals are output.
2. The multi-user data multiplexing superframe frame coding modulation method according to claim 1, wherein: the superframe processing module adopts three modulation modes of BPSK, QPSK and 8PSK to scramble, PN codes are used for generating scrambling in parallel by 8 bits respectively, baseband bit data of each constellation point are decomposed into parallel 1, 2 and 3 paths, then the parallel branches are scrambled by the same PN respectively, and the parallel branches are combined into one path for output after scrambling.
3. The multi-user data multiplexing superframe frame coding modulation method according to claim 1, wherein: the FPGA device adopts a full-digital parallel pipeline structure coding and modulation algorithm to realize superframe framing, realizes data interfaces with different bit widths through a plurality of double-port RAMs with different bit widths, and performs flow control management on the whole data processing process; the data superframe framing part adopts a complex command generation state machine and a command response state machine, takes an LDPC code block as a unit, adds a frame head and a frame tail in front of and behind the LDPC code block according to the protocol requirement, and forms 274 data subframe structures by filling 8 LDPC code blocks, and finally forms a superframe with the length of 17958400 symbols; the code algorithm part realizes 1/2, 3/4 and 7/8 LDPC codes with different code rates and symbol scrambling of BPSK, QPSK and 8PSK with different debugging modes, the modulation algorithm part adopts 8 bits of data bit width, 40 paths of parallel symbol interpolation with 12 bits of data bit width are adopted based on parameterized parallel symbol interpolation and parallel carrier, and the carrier generates 40 paths of parallel orthogonal modulation signals with 12 bits of data bit width.
4. The multi-user data multiplexing superframe frame coding modulation method according to claim 1, wherein: in an FPGA device, a superframe framing processing control state machine generates a state machine command and a response state machine command based on an FPGA, data with an LDPC code block as a unit is used as basic signal processing granularity according to protocol requirements, frame head frame tails are added in front of and behind the code block, 8 low-density parity check LDPC code blocks are added and filled to form a data subframe structure, a code word with an n-dimensional vector m is generated, a superframe with output bit width symbols with the lengths reaching phase shift keying PSK, QPSK and BPSK respectively being 24 bits, 16 bits and 8 bits is formed, then service data input by 32 bits are read out from a cache stored in a superframe data buffer according to the bit width of 8 bits, and superframe framing processing is carried out; the LDPC code block multiplies an information vector m to be coded by a sparse matrix H to obtain an intermediate result S, then repeatedly accumulates the intermediate result S to obtain a check bit, and finally combines the information bit and the check bit to obtain a final code word.
5. The multi-user data multiplexing superframe frame coding modulation method according to claim 1, wherein: the superframe processing module takes a command generation and response state machine as a control scheduling center for superframe generation and a complex data flow control manager; controlling superframe data to be inserted before and after each LDPC code block formed by superframes, carrying out superframe transmission according to the LDPC code blocks, and controlling the insertion content of the superframes to be added in front of or behind the LDPC code blocks according to the requirements of the superframes; the superframe data buffer is managed to ensure error-free ingress and egress of data streams both to the preceding superframe framing and to the following modulator.
6. The multi-user data multiplexing superframe frame coding modulation method according to claim 1, wherein: the data bit width conversion module reads the cache data in the superframe data buffer with bit widths of 24bit, 16bit and 8bit respectively according to different modulation modes, and sends the cache data to the symbol mapping module for modulation constellation mapping, the symbol mapping module sends 8 paths of parallel 8bit width data to the symbol interpolation and forming filter module, the symbol interpolation is carried out for up sampling and baseband forming filtering according to the phase generation of the input parallel code clock, the interpolation forming data is sent to the orthogonal modulator for modulation according to 40 paths of parallel 40 bit width data of 12bit, and the generator of the parallel carrier generates 40 paths of parallel 40 bit width orthogonal carrier signals, orthogonal carrier sin signals and orthogonal carrier cos signals; and after orthogonal debugging, outputting 4 paths of parallel 40 × 112bit wide LVDS modulation signals to a high-speed DA, and finally outputting intermediate frequency modulation signals.
7. The multi-user data multiplexing superframe frame coding modulation method according to claim 1, wherein: the superframe framing processing control state machine provides control information by adding code block numbers obtained by counting LDPC code blocks in a data subframe structure formed by filling, and decides according to the code block numbers: whether a superframe head, a superframe tail, signaling, data subframe tail filling, scrambling initial phase resetting and other contents which need to be filled in the superframe structure are inserted in front of and behind the current LDPC code block or not is respectively combined through the superframe head, the LDPC code block, the data subframe, the subframe filling and the frame tail to form a physical layer superframe frame structure with the length of 17958400 symbols.
8. The multi-user data multiplexing superframe frame code modulation method as claimed in claim 1, characterized in that: the data bit width conversion module respectively reads out and reads out 24-bit, 16-bit and 8-bit data bit width data which are respectively input into a superframe data buffer according to different modulation modes, the data are sent to a symbol mapping module for modulation constellation mapping, 8 paths of parallel constellation mapping are output through 8PSK, QPSK and BPSK mapping modules to obtain LUT data symbols and different coding modes, and mapping constellation point complex data I + j Q with the output bit width of 8 bits is obtained; i + j × Q; the symbol mapping module sends 8 paths of parallel 8-bit-wide data to a symbol interpolation and forming filtering module for symbol interpolation up-sampling and baseband forming filtering, the symbol interpolation and forming filtering module sends 40 paths of parallel 12-bit-wide data interpolation forming data to an orthogonal modulator for modulation, and a generator generates 40 paths of parallel carrier 12-bit-wide orthogonal carrier signals sin and cos; and after different branches and clocks are switched, a set accumulated value is continuously added from head to tail, and the accumulated value of the phase word is obtained by calculating the modulation symbol rate.
9. The multi-user data multiplexing superframe frame code modulation method as claimed in claim 1, characterized in that: the orthogonal modulator adopts 40 parallel orthogonal carrier sin and cos circuits, in an FPGA processing clock period, parallel 40-point contact carrier digital sampling points with continuous phases are obtained, phase parallel calculation and parallel updating of a parallel lookup table are carried out according to the generated 40 paths of parallel carrier sampling points, parallel orthogonal modulation is carried out on 40 paths of real parts and imaginary parts, parallel multiplication of 40 paths of parallel symbol waveforms and carriers is respectively completed through parallel multipliers, parallel corresponding summation is output through the parallel multipliers, finally 40 paths of parallel modulation signal output are obtained, and data output after orthogonal debugging is 4 paths of parallel modulation signals of 12-bit-width LVDS and is sent to a high-speed digital-to-analog converter DA.
10. The multi-user data multiplexing superframe frame code modulation method as claimed in claim 1, characterized in that:
in the superframe processing, according to data cache and data cache null detection, null frame insertion processing and signaling insertion processing are carried out, and through an encoder interface, a parallel 1/2 code rate LDPC encoder, a 3/4 code rate LDPC encoder and a 3/4 code rate LDPC encoder are adopted to carry out superframe header insertion and symbol scrambling in different modulation modes; in the empty frame insertion processing, an empty frame insertion module receives an empty frame insertion signal, completely fills the data area of the current LDPC code block into FF, fills a virtual channel mark into X00, and reads data from a data cache area for framing if the empty frame insertion mark is not received; in the signaling insertion processing, based on superframe framing state control and parameters and monitoring parameters, a signaling control word with the unique word length of 4 bytes, the effective data length of 2 bytes, the virtual channel mark length of 1 byte, the virtual channel count length of 4 bytes and the content of 4-byte frame synchronization code 1ACFFC1D is inserted in front of a data area, the padding data is X '01', the signaling is X '02', the empty frame without the padding data is X '00', filling is carried out according to the effective data length in an actual coding block, in LDPC coding, an LDPC code block adopts three modes of transmitted data bits 1 and 0, carrier phase 225 degrees and +45 degrees according to the relationship between the data bits and the BPSK modulator output carrier phase, and the USB device interface IPcore coding completion frame based on FPGA has the frame length of 1008 bytes; in the insertion of the superframe header, when a superframe header insertion control signal is received, inserting all 1 of 1536 symbols in front of a currently input LDPC code block, and directly outputting data if no control signal exists; in the symbol scrambling, after the scrambled data is buffered and converted in bit width, the data is sent to a symbol mapping module to carry out BPSK, QPSK and 8PSK modulation mapping respectively according to the controlled modulation mode, after modulation mapping, symbol interpolation and shaping filtering processing are carried out, then orthogonal modulation is carried out, and the modulated data is sent to a high-speed DA.
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