CN111430460A - Lateral diffusion metal oxide semiconductor device and forming method thereof - Google Patents

Lateral diffusion metal oxide semiconductor device and forming method thereof Download PDF

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Publication number
CN111430460A
CN111430460A CN201910022854.2A CN201910022854A CN111430460A CN 111430460 A CN111430460 A CN 111430460A CN 201910022854 A CN201910022854 A CN 201910022854A CN 111430460 A CN111430460 A CN 111430460A
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region
fin
dummy gate
substrate
forming
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CN111430460B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A lateral diffusion metal oxide semiconductor device and a forming method thereof are provided, wherein the structure comprises: the substrate comprises a first area and a second area, and a plurality of first fin parts which are arranged in parallel are arranged on the substrate of the first area; the first well regions are positioned in the plurality of first fin parts and the first region of the substrate; at least one first dummy gate structure spanning the plurality of first fin portions; the plurality of drain regions are positioned in the first fin parts on one side of the first dummy gate structure; and the first conductive structure is positioned on the drain region and spans the plurality of first fin parts. The self-heating effect of the lateral diffusion metal oxide semiconductor device is effectively weakened.

Description

Lateral diffusion metal oxide semiconductor device and forming method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a laterally diffused metal oxide semiconductor device and a forming method thereof.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, as well as higher integration and higher performance.
The power field effect transistor mainly includes a Vertical Diffused Metal Oxide Semiconductor (VDMOS) transistor and a lateral Diffused Metal Oxide semiconductor (L) Double-Diffused MOSFET, &ttttranslation = L "&gtt L &ltt/t &gtt DMOS) transistor.
However, the prior art ldmos device has a serious self-heating effect.
Disclosure of Invention
The invention provides a lateral diffusion metal oxide semiconductor device and a forming method thereof, which can reduce self-heating effect.
To solve the above technical problem, the present invention provides a lateral diffusion metal oxide semiconductor device, including: the substrate comprises a first area and a second area, and a plurality of first fin parts which are arranged in parallel are arranged on the substrate of the first area; the first well regions are positioned in the plurality of first fin parts and the first region of the substrate; at least one first dummy gate structure spanning the plurality of first fin portions; the plurality of drain regions are positioned in the first fin parts on one side of the first dummy gate structure; and the first conductive structure is positioned on the drain region and spans the plurality of first fin parts.
Optionally, a plurality of second fin portions arranged in parallel are located on the second region substrate, the second fin portions extend from the second region to the first region substrate, and the second fin portions and the first fin portions are mutually separated; and the second well regions are positioned in the plurality of second fin parts and the second region of the substrate and are in contact with the first well regions.
Optionally, the method further includes: the main gate structure stretches across the plurality of second fin portions, extends from the second region to the first region, and is also located on the side walls of the second fin portions.
Optionally, the first well region is further located in the second fin portion of the first region.
Optionally, the number of the first dummy gate structures is greater than or equal to 2, and the first dummy gate structures are arranged in parallel.
Optionally, the drain region is located in the first fin portion between two adjacent first dummy gate structures.
Optionally, the method further includes: and a plurality of second conductive structures located on the first dummy gate structures.
Optionally, the method further includes: and the second conductive structures are positioned on partial top surfaces of the plurality of third conductive structures.
Optionally, the method further includes: and the source regions are positioned in the second fin parts on one side of the main grid electrode structure.
Optionally, the method further includes: and the second dummy gate structures cross the plurality of second fin parts, and the second dummy gate structures and the main gate structures are respectively positioned at two sides of the source region.
Optionally, the method further includes: and the fourth conductive structure is positioned on the source region and spans the second fin parts.
Optionally, a dimension of the first conductive structure in the extending direction of the first fin portion is larger than a dimension of the fourth conductive structure in the extending direction of the second fin portion.
Optionally, the method further includes: and the first dielectric layer is positioned on the substrate and covers the first conductive structure and the side wall surfaces of the plurality of first dummy gate structures.
Optionally, the method further includes: and the isolation structure is positioned on the surface of the side wall of the first fin part, and the top surface of the isolation structure is lower than that of the first fin part.
Correspondingly, the invention also provides a method for forming the lateral diffusion metal oxide semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate comprises a first area and a second area, and a plurality of first fin parts which are arranged in parallel are arranged on the substrate of the first area; forming first well regions in the plurality of first fin portions and the first region of the substrate; after the first well region is formed, at least one first dummy gate structure is formed on the surfaces of the plurality of first fin portions; forming a drain region in each first fin portion respectively, wherein the drain region is located on one side of the first dummy gate structure; and forming a first conductive structure on the drain region, wherein the first conductive structure spans the plurality of first fin parts.
Optionally, the number of the first dummy gate structures is greater than or equal to 2, and the first dummy gate structures are arranged in parallel; the drain region is positioned in the first fin part between two adjacent first dummy gate structures; the forming method of the drain region comprises the following steps: removing part of the substrate between the first dummy gate structures, and forming a first groove in a first region of the substrate; and forming a source and drain region material layer in the first groove so as to form a drain region.
Optionally, the method further includes: after the first dummy gate structure is formed and before the first conductive structure is formed, forming a first dielectric layer on the substrate; the forming method of the first conductive structure comprises the following steps: forming a first contact hole in the first dielectric layer, wherein the bottom of the first contact hole is exposed out of the top surface of the drain region; filling a conductive material in the first contact hole to form a first conductive structure material film, wherein the first conductive structure material film is filled in the first contact hole, and the top surface of the first conductive structure material film is higher than that of the first medium layer; and flattening the first conductive structure material film until the top surface of the first dielectric layer is exposed to form the first conductive structure.
Optionally, the method further includes: after forming the first conductive structure, a second conductive structure is formed on the first dummy gate structure.
Optionally, the method further includes: after the first conductive structures are formed and before the second conductive structures are formed, third conductive structures are formed on the surfaces of the plurality of first dummy gate structures respectively, and the second conductive structures are located on the surfaces of the plurality of third conductive structures.
Optionally, the second region of the substrate has a plurality of second fin portions arranged in parallel, the second fin portions extend from the second region to the substrate of the first region, and the second fin portions and the first fin portions are separated from each other; the method for forming the laterally diffused metal oxide semiconductor device further comprises the following steps: forming second well regions in the plurality of second fin portions and the second region of the substrate, wherein the second well regions are in contact with the first well regions; forming a main gate structure crossing the plurality of second fin portions, wherein the main gate structure extends from the second region to the first region, and the main gate structure is located on part of the tops and part of the side wall surfaces of the second fin portions; after the main grid electrode structure is formed, forming a plurality of source regions in each second fin part on one side of the main grid electrode structure; and after the source region is formed, forming a fourth conductive structure on the source region, wherein the fourth conductive structure spans the plurality of second fin parts.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the laterally diffused metal oxide semiconductor device provided by the technical scheme of the invention, the first dummy gate structure spans the plurality of first fin parts, so that at least one first dummy gate structure positioned on the surfaces of the plurality of first fin parts can increase heat transfer paths of the plurality of first fin parts, thereby being beneficial to radiating heat of the device on the first fin parts to the periphery and effectively weakening the spontaneous heating effect of the laterally diffused metal oxide semiconductor device.
Furthermore, the second conductive structure is located on the top surface of the first dummy gate structure, namely, the second conductive structure is in contact with the first dummy gate structure, so that the second conductive structure can further conduct heat conducted by the first dummy gate structure to the periphery, namely, further conduct heat accumulated in the device on the first fin portion, and further weaken the spontaneous heating effect of the laterally diffused metal oxide semiconductor device.
Furthermore, the size of the first conductive structure in the extending direction of the first fin portion is larger than that of the fourth conductive structure in the extending direction of the second fin portion, the first conductive structure is located on the surface of the drain region in the first fin portion, and the fourth conductive structure is located on the surface of the source region in the second fin portion.
Drawings
FIG. 1 is a schematic cross-sectional view of an embodiment of a LDMOS device;
fig. 2 to 13 are schematic structural diagrams of steps of a method for forming a ldmos device according to an embodiment of the invention.
Detailed Description
As described in the background, lateral diffused metal oxide semiconductor devices have poor thermal conductivity.
FIG. 1 is a cross-sectional schematic view of an embodiment of a LDMOS device.
Referring to fig. 1, a substrate includes a first region a and a second region B, the first region a of the substrate has a plurality of first fin portions 101 arranged in parallel, and the second region B of the substrate has a plurality of second fin portions 102; a main gate structure 110 spanning over a plurality of the second fins 102, the main gate structure 110 extending from the second region B to the first region a, and the main gate structure 110 further being located on a sidewall of the second fins 102; a source region 121, wherein the source region 121 is located in the second fin 102 on one side of the main gate structure 110; the drain region 121, wherein the drain region 121 is located in the first fin portion 101 on the other side of the primary gate structure 110; a first conductive structure 131, wherein the first conductive structure 131 is located on the surface of the drain region 121; a second conductive structure 132, wherein the second conductive structure 132 is located on the surface of the source region 122.
In order to meet the requirement of integration, the laterally diffused metal oxide semiconductor device is formed on the fin portion. However, laterally diffused metal oxide semiconductor devices formed based on fin technology still have problems. The fin portions arranged in parallel are located in a small space, a large amount of heat can be generated when devices on the fin portions work, and the heat in the devices on the fin portions cannot be effectively conducted, so that a large amount of heat is accumulated in the devices on the fin portions easily, a spontaneous heating effect is generated, and the performance of a transverse diffusion metal oxide semiconductor device is further influenced.
In order to solve the technical problem, the invention provides a method for forming a laterally diffused metal oxide semiconductor device, which comprises the following steps: by forming at least one first dummy gate structure on the surface of the first fin portion, the heat transfer paths of the plurality of first fin portions can be increased, and therefore the spontaneous heating effect of the laterally diffused metal oxide semiconductor device is effectively weakened. The lateral diffusion metal oxide semiconductor device formed by the method has low spontaneous effect.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 13 are schematic structural diagrams of steps of a method for forming a ldmos device according to an embodiment of the invention.
Referring to fig. 2 and 3, fig. 3 is a schematic cross-sectional view taken along a cutting line a-a1 in fig. 2, fig. 2 is a schematic top view taken along a direction Z1 in fig. 3, and a substrate 200 is provided, where the substrate 200 includes a first region I and a second region II, and the first region I has a plurality of first fins 210 arranged in parallel on the substrate 200.
The substrate 200 may be single crystal silicon, polycrystalline silicon, or amorphous silicon; or a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like. In this embodiment, the material of the substrate 200 is monocrystalline silicon.
In this embodiment, the second region II of the substrate 200 has a plurality of second fins 220 arranged in parallel, the second fins 220 extend from the second region II to the substrate 200 of the first region a, and the second fins 220 are separated from the first fins 210.
In this embodiment, the first fin portion 210 and the second fin portion 220 are formed by etching an initial substrate. In other embodiments, a fin material layer is formed on the substrate 200 and then patterned to form the first fin 210 and the second fin 220.
With continuing reference to fig. 2 and 3, first well regions 201a are formed in the first fin portions 210 and the first region I of the substrate 200.
The first well region 201a is also located in the second fin portion 220 of the first region I.
In this embodiment, the method further includes: second well regions 201b are formed in the plurality of second fin portions 220 and the second region II of the substrate 200, and the second well regions 201b are in contact with the first well regions 201 a.
The second well region 201b is used as a transverse diffusion region to form a channel with concentration gradient; the first well 201a serves as a drift region to withstand a larger voltage division.
The step of forming the first well region 201a includes: forming a second mask layer (not shown) on the substrate 200, wherein the second mask layer exposes the surface of the substrate 200 corresponding to the first well 201 a; with the second mask layer as a mask, a first trap ion implantation process is used to implant first trap ions into the substrate 200 and the first fin portion 210, so as to form a first well region 201 a.
The step of forming the second well region 201b includes: forming a third mask layer (not shown) on the substrate 200, wherein the second mask layer exposes the surface of the substrate 200 corresponding to the second well 201 b; and implanting second trap ions into the substrate 200 and the second fin portion 220 by using the third mask layer as a mask and using a second trap ion implantation process to form a second well region 201 b.
In an embodiment, after the first well region 201a is formed, the second well region 201b is formed. In another embodiment, the first well region 201a is formed after the second well region 201b is formed.
The first well region 201a is doped with first well ions, and the second well region 201b is doped with second well ions. The first trap ion is of the opposite type to the second trap ion.
When the type of the transverse diffusion metal oxide semiconductor device is P type, the type of the first trap ion is P type, and the type of the second trap ion is N type; when the type of the lateral diffusion metal oxide semiconductor device is N type, the type of the first trap ion is N type, and the type of the first trap ion is P type.
A first dummy gate structure is subsequently formed on the first fin portion 210 in the first region I.
In this embodiment, the surface of the substrate 200 further has an isolation structure 202, the isolation structure 202 is located on a portion of the sidewall surface of the first fin 210, and the top surface of the isolation structure 202 is lower than the top surface of the first fin 210. The isolation structure 202 is used to achieve electrical isolation between different devices.
In the present embodiment, the isolation structure 202 is also located on a portion of the sidewall surface of the second fin 220, and the top surface of the isolation structure 202 is lower than the top surface of the second fin 220.
Referring to fig. 4 and 5, fig. 5 is a schematic top view along the direction Z2 in fig. 4, and fig. 4 is a schematic cross-sectional view along the direction B-B1 in fig. 5, after the first well 201a is formed, at least one first dummy gate structure 230 is formed on the surfaces of the first fins 210.
The first dummy gate structure 230 includes a dummy gate dielectric layer (not shown) on a portion of the first I-substrate 200, and a dummy gate electrode layer (not shown) on a surface of the dummy gate dielectric layer.
The method for forming the first dummy gate structure 230 includes: forming a dummy gate dielectric material layer (not shown) and a dummy gate electrode material layer on the surface of the dummy gate dielectric material layer (not shown) on the surface of the first region I isolation structure 202; the dummy gate dielectric material layer and the dummy gate electrode material layer are patterned to form a dummy gate dielectric layer and a dummy gate electrode layer, and the first dummy gate structure comprises a dummy gate dielectric layer and a dummy gate electrode layer located on the surface of the dummy gate dielectric layer.
Because the first dummy gate structures 230 cross over the plurality of first fins 210, at least one first dummy gate structure 230 on the surface of the plurality of first fins 210 can increase the heat transfer paths of the plurality of first fins 210, thereby facilitating the heat dissipation of the devices on the first fins 210 to the periphery and effectively weakening the spontaneous heating effect of the laterally diffused metal oxide semiconductor device.
In this embodiment, the first dummy gate structure 230 further includes first sidewalls (not shown) on sidewalls of the dummy gate dielectric layer and the dummy gate electrode layer. In other embodiments, the gate structure may not include the first sidewall.
The pseudo gate dielectric layer is made of silicon oxide or a high-K dielectric material. The material of the dummy gate electrode layer is polysilicon. The first side wall can be made of silicon nitride, silicon oxynitride or silicon oxycarbide.
The number of the first dummy gate structures 230 is greater than or equal to 2, and the first dummy gate structures 230 are arranged in parallel.
In this embodiment, the number of the first dummy gate structures is 2, the first dummy gate structures 230 respectively cross over a portion of the top surface and the sidewalls of the first fin portion 210, and the first dummy gate structures 230 are respectively located at two sides of a subsequently formed first conductive structure.
In other embodiments, the number of the first dummy gate structures is 1.
In another embodiment, the number of the first dummy gate structures is 3.
In this embodiment, a main gate structure 240 crossing over a plurality of the second fins 220 is further formed, the main gate structure 240 extends from the second region II to the first region I, and the main gate structure 240 is further located on a portion of the top and a portion of the sidewall surface of the second fins 220
In the present embodiment, a second dummy gate structure 250 is also formed across a plurality of the second fins 220.
The second dummy gate structure 250 and the main gate structure 240 together confine a subsequently formed source region between the second dummy gate structure 250 and the main gate structure 240.
In this embodiment, the main gate structure 240 and the second dummy gate structure 250 are formed while the first dummy gate structure 230 is formed, so that the second dummy gate structure 250 includes a second dummy gate dielectric layer crossing the second fin portion 220 and a second dummy gate electrode layer located on the second dummy gate dielectric layer, so that the main gate structure 240 includes a gate dielectric layer crossing the second fin portion 220 and a gate electrode layer located on the gate dielectric layer, and the gate dielectric layer is also located on the sidewall of the second fin portion 220. In other embodiments, the first dummy gate structure, the gate structure, and the second dummy gate structure may be formed separately in different steps.
In this embodiment, the main gate structure 240 further includes a main sidewall located on the sidewalls of the gate dielectric layer and the gate electrode layer; the second dummy gate structure 250 further includes a second sidewall spacer on sidewalls of the second dummy gate dielectric layer and the second gate electrode layer. In other embodiments, the main sidewall and the second sidewall may not be formed.
The materials of the pseudo gate dielectric layer, the gate dielectric layer and the second pseudo gate dielectric layer are the same. The dummy gate electrode layer, the gate electrode layer and the second gate electrode layer are made of the same material. The first side wall, the second side wall and the main side wall are made of the same material.
Since the main gate structure 240 and the second dummy gate structure 250 are formed at the same time as the first dummy gate structure 230, the process is simplified.
Referring to fig. 6, it should be noted that, the view directions of fig. 6 and fig. 4 are the same, a drain region 261 is formed in each first fin 210, and the drain region 261 is located at one side of the first dummy gate structure 230.
When the number of the first dummy gate structures 230 is greater than or equal to 2, the drain region 261 is located in the first fin 210 between two adjacent first dummy gate structures 230.
In this embodiment, the number of the first dummy gate structures 230 is 2, and the drain region 261 is located in the first fin 210 between the two first dummy gate structures 230.
The first dummy gate structures 230 located at two sides of the drain region 261 have an effect of limiting a region where the drain region grows in a subsequent drain region forming process so as to limit a lateral size of the drain region, in addition to an effect of increasing a heat transfer path of the plurality of first fins 210, which is beneficial to conducting a large amount of heat accumulated by devices on the first fins 210 of the first region I to the periphery.
In this embodiment, the method further includes: a source region 262 is formed in each second fin 220, and the source region 262 is located at one side of the main gate structure 240.
In the present embodiment, the source region 262 is located in the second fin 220 between the main gate structure 240 and the second dummy gate structure 250.
In the present embodiment, the method of forming the source region 262 and the drain region 261 includes: removing a portion of the first fin portion 210 between two adjacent first dummy gate structures 230 to form a first recess (not shown); removing a portion of the second fin portion 220 between the main gate structure 240 and the second dummy gate structure 250 to form a second recess (not shown); source and drain material layers (not shown) are formed in the first and second recesses to form source and drain regions 262 and 261.
Referring to fig. 7, after the drain region 261 is formed, a first dielectric layer 270 is formed on the substrate 200, and the first dielectric layer 270 covers sidewalls of the first dummy gate structure 230.
In this embodiment, the first dielectric layer 270 is located on the surface of the isolation structure 202, the first dielectric layer 270 covers sidewalls of the first fin portion 210, the second fin portion 220, the first dummy gate structure 230, the main gate structure 240, and the second dummy gate structure 250, and a top surface of the first dielectric layer 270 is higher than top surfaces of the first dummy gate structure 230, the main gate structure 240, and the second dummy gate structure 250.
The method for forming the first dielectric layer 270 includes: forming a dielectric material film (not shown) on the surface of the isolation structure 202, wherein the dielectric material film covers the sidewalls of the first fin portion 210, the second fin portion 220, the first dummy gate structure 230, the main gate structure 240, and the second dummy gate structure 250, and the top surface of the dielectric material film is higher than the top surfaces of the first dummy gate structure 230, the main gate structure 240, and the second dummy gate structure 250; and planarizing the dielectric material film to form the first dielectric layer 270.
The material of the first dielectric layer 270 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride. In this embodiment, the material of the first dielectric layer 270 is silicon oxide.
Referring to fig. 8 and 9, fig. 8 is a schematic cross-sectional view taken along a cutting line D-D1 in fig. 9, fig. 9 is a schematic top view taken along a direction Z3 after the first dielectric layer 270 is omitted in fig. 8, and after the first dielectric layer 270 is formed, a first conductive structure 281 is formed on the surface of the drain region 261.
The method for forming the first conductive structure 281 includes: forming a fourth mask layer (not shown in the figure) on the surface of the first dielectric layer 270, wherein the fourth mask layer exposes the surface of the first dielectric layer 270 on the drain region 261; etching the first dielectric layer 270 with the fourth mask layer as a mask until the top surface of the drain region 261 is exposed, and forming a first contact hole (not shown in the figure) in the first dielectric layer 270; filling the first contact hole with a conductive material to form a first conductive structure material film (not shown), wherein the first conductive structure material film fills the first contact hole and has a top surface higher than that of the first dielectric layer 270; the first conductive structure material film is planarized until the top surface of the first dielectric layer 270 is exposed, forming the first conductive structure 281.
The material of the first conductive structure film includes: copper, tungsten, nickel, chromium, titanium, aluminum. Accordingly, the material of the first conductive structure 281 includes: copper, tungsten, nickel, chromium, titanium, aluminum.
In this embodiment, the method further includes: and respectively forming third conductive structures 283 on the surfaces of the plurality of first dummy gate structures 230, wherein the top surfaces of the third conductive structures 283 are flush with the top surface of the first dielectric layer 270.
In this embodiment, the method further includes: a fourth conductive structure 282 is formed on the surface of each of the source regions 262, and the top surface of the fourth conductive structure 282 is flush with the top surface of the first dielectric layer 270.
In this embodiment, the third conductive structure 283 and the fourth conductive structure 282 are formed at the same time as the first conductive structure 281 is formed, so that the process is simplified.
In this embodiment, the dimension of the first conductive structure 281 along the extending direction of the first fin 210 is greater than the dimension of the fourth conductive structure 282 along the extending direction of the second fin 220, the first conductive structure 281 is located on the surface of the drain region 261 in the first fin 210, and the fourth conductive structure 282 is located on the surface of the source region 262 in the second fin 220, so that the larger dimension of the first conductive structure 281 is more helpful to improve the thermal conductivity of the device located on the first fin 210, thereby effectively reducing the spontaneous heating effect of the ldmos device.
After the first conductive structures 281 are formed, a plurality of second conductive structures are formed on the first dummy gate structures, and the second conductive structures are arranged in parallel, please refer to fig. 10 to 13, which will be described in detail.
Referring to fig. 10, after the first conductive structure 281 is formed, a second dielectric layer 271 is formed on the surface of the first dielectric layer 270.
Fig. 10 and 8 are the same in view direction.
The material of the second dielectric layer 271 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
In this embodiment, the second dielectric layer 271 and the first dielectric layer 270 are made of the same material, and are both silicon oxide.
Referring to fig. 11 to 13, fig. 11 is a schematic cross-sectional view taken along a cutting line F-F1 in fig. 13, fig. 12 is a schematic cross-sectional view taken along a cutting line G-G1 in fig. 13, fig. 13 is a schematic top view taken along Z3 in fig. 11 without the first dielectric layer 270 and the second dielectric layer 271, a second conductive structure 290 is formed in the second dielectric layer 271, and the second conductive structure 290 is located on the first dummy gate structure 230.
In this embodiment, the second conductive structure 290 is located on a portion of the top surface of the third conductive structure 283 on the surface of the first dummy gate structure 230.
In this embodiment, the number of the first dummy gate structures 230 is 2, one end of each of the second conductive structures 290 is located on a portion of the top surface of the third conductive structure 282 on the surface of one of the first dummy gate structures 230, and the other end of each of the second conductive structures 290 is located on a portion of the top surface of the third conductive structure 282 on the surface of another one of the first dummy gate structures 230.
The second conductive structure 290 is located on a part of the top surface of the first dummy gate structure 230, that is, the second conductive structure 290 is in contact with the first dummy gate structure 230, so that the second conductive structure 290 can further conduct heat conducted by the first dummy gate structure 230 to the periphery, that is, further conduct heat accumulated in the device on the first fin portion 210, thereby effectively weakening the spontaneous heating effect of the laterally diffused metal oxide semiconductor device.
The method for forming the second conductive structure 290 includes: forming a first mask layer (not shown in the figure) on the surface of the second dielectric layer 271, wherein the first mask layer exposes the surface of the second dielectric layer 271 between the adjacent fin portions; etching the second dielectric layer 271 by using the first mask layer as a mask until the top surface of the first dummy gate structure 230 is exposed, and forming a second contact hole (not shown in the figure) in the second dielectric layer 271; filling the second contact hole with a conductive material to form a second conductive structure material film (not shown in the figure), wherein the second conductive structure material film fills the second contact hole and the top surface of the second conductive structure material film is higher than that of the second medium layer 271; and flattening the second conductive structure material film until the second dielectric layer 271 is exposed to form the second conductive structure 290.
The material of the second conductive structure film includes: copper, tungsten, nickel, chromium, titanium, aluminum. Accordingly, the material of the second conductive structure 290 includes: copper, tungsten, nickel, chromium, titanium, aluminum.
In the embodiment, the second conductive structure 290 is parallel to the extending direction of the first fins 210, and the second conductive structure 290 is located in the second dielectric layer 271 on the substrate 200 between the adjacent first fins 210.
In other embodiments, the second conductive structure is located within the second dielectric layer on the first fin.
Accordingly, an embodiment of the present invention further provides a ldmos device, referring to fig. 11, including: the substrate 200 comprises a first area I and a second area II, wherein the substrate 200 of the first area I is provided with a plurality of first fin parts 210 which are arranged in parallel; first well regions 201a located in the plurality of first fin portions 210 and in the first region I of the substrate 200; at least one first dummy gate structure 230 spanning a number of the first fins 210; a plurality of drain regions 261 in each first fin portion 210 on one side of the first dummy gate structure 230; a first conductive structure 281 is located on the drain region 261, and the first conductive structure 281 spans several first fins 210.
Because the first dummy gate structures 230 cross over the plurality of first fins 210, at least one first dummy gate structure 230 on the surface of the plurality of first fins 210 can increase the heat transfer paths of the plurality of first fins 210, thereby facilitating the heat dissipation of the devices on the first fins 210 to the periphery and effectively weakening the spontaneous heating effect of the laterally diffused metal oxide semiconductor device.
The following detailed description is made with reference to the accompanying drawings.
In this embodiment, the ldmos device further includes: a first dielectric layer 270 on the substrate 200, wherein the first dielectric layer 270 covers the first conductive structures 281 and the sidewall surfaces of the plurality of first dummy gate structures 230.
In this embodiment, the ldmos device further includes: an isolation structure 202 on the surface of the substrate 200, wherein the isolation structure 202 is located on a portion of a sidewall surface of the first fin 210, and a top surface of the isolation structure 202 is lower than a top surface of the first fin 210.
The laterally diffused metal oxide semiconductor device further comprises: a plurality of second fin portions 220 arranged in parallel on the second region II substrate 200, wherein the second fin portions 220 extend from the second region II to the first region I substrate 200, and the second fin portions 220 and the first fin portions 210 are separated from each other; and a second well region 201b located in the plurality of second fin portions 220 and the second region II of the substrate 200, wherein the second well region 201b is in contact with the first well region 201 a.
The laterally diffused metal oxide semiconductor device further comprises: the main gate structure 240 spans a plurality of the second fins 220, the main gate structure 240 extends from the second region II to the first region I, and the main gate structure 240 is further located on the sidewall of the second fins 220.
In this embodiment, the first well region 201a is also located in the second fin portion 220 of the first region I.
The number of the first dummy gate structures 230 is greater than or equal to 2, and the first dummy gate structures 230 are arranged in parallel.
The drain region 261 is located in the first fin portion 210 between two adjacent first dummy gate structures 230. In this embodiment, the number of the first dummy gate structures 230 is 2, and the drain region 261 is located in the first fin 210 between two first dummy gate structures 230.
In this embodiment, the ldmos device further includes: a number of second conductive structures 290 located on the first dummy gate structures 230.
In this embodiment, the ldmos device further includes: the third conductive structures 283 are respectively located on the surfaces of the plurality of first dummy gate structures 230, and the second conductive structure 290 is located on a portion of the top surfaces of the plurality of third conductive structures 283.
The second conductive structure 290 is located on a part of the top surface of the first dummy gate structure 230, that is, the second conductive structure 290 is in contact with the first dummy gate structure 230, so that the second conductive structure 290 can further conduct heat conducted by the first dummy gate structure 230 to the periphery, that is, further conduct heat accumulated in the device on the first fin portion 210, thereby effectively weakening the spontaneous heating effect of the laterally diffused metal oxide semiconductor device.
The laterally diffused metal oxide semiconductor device further comprises: a plurality of source regions 262 in each of the second fins 220 on one side of the main gate structure 240.
In this embodiment, the ldmos device further includes: and the second dummy gate structures 250 cross a plurality of second fins 220, and the second dummy gate structures 250 and the main gate structures 240 are respectively located at two sides of the source region 262.
In this embodiment, the ldmos device further includes: a fourth conductive structure 282 is located on the source region 262, and the fourth conductive structure 282 spans a number of the second fins 220.
In this embodiment, the ldmos device further includes: a source region 262, the source region 262 being located within the second well region 201 b; a fourth conductive structure 282, the fourth conductive structure 282 being located at the surface of the source region 262.
In the embodiment, the dimension of the first conductive structure 281 along the extending direction of the first fin portion 210 is larger than the dimension of the fourth conductive structure 282 along the extending direction of the second fin portion 220.
The dimension of the first conductive structure 281 in the extending direction of the first fin 210 is larger than the dimension of the fourth conductive structure 282 in the extending direction of the second fin 220, the first conductive structure 281 is located on the surface of the drain region 261 in the first fin 210, and the fourth conductive structure 282 is located on the surface of the source region 262 in the second fin 220, so that the larger dimension of the first conductive structure 281 is more beneficial to improving the thermal conductivity of the device on the first fin 210, and is further beneficial to improving the thermal conductivity of L DMOS.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A laterally diffused metal oxide semiconductor device, comprising:
the substrate comprises a first area and a second area, and a plurality of first fin parts which are arranged in parallel are arranged on the substrate of the first area;
the first well regions are positioned in the plurality of first fin parts and the first region of the substrate;
at least one first dummy gate structure spanning the plurality of first fin portions;
the plurality of drain regions are positioned in the first fin parts on one side of the first dummy gate structure;
and the first conductive structure is positioned on the drain region and spans the plurality of first fin parts.
2. The laterally diffused metal oxide semiconductor device of claim 1, further comprising:
the second fin parts are arranged on the second region substrate in parallel, extend from the second region to the first region substrate, and are mutually separated from the first fin parts; and the second well regions are positioned in the plurality of second fin parts and the second region of the substrate and are in contact with the first well regions.
3. The laterally diffused metal oxide semiconductor device of claim 2, further comprising:
the main gate structure stretches across the plurality of second fin portions, extends from the second region to the first region, and is also located on the side walls of the second fin portions.
4. The ldmos device of claim 1, wherein the first well region is further located in the second fin portion of the first region.
5. The ldmos device of claim 1, wherein the number of the first dummy gate structures is greater than or equal to 2, and a plurality of the first dummy gate structures are arranged in parallel.
6. The LDMOS device of claim 5, wherein the drain region is located in the first fin portion between two adjacent first dummy gate structures.
7. The laterally diffused metal oxide semiconductor device of claim 1, further comprising: and a plurality of second conductive structures located on the first dummy gate structures.
8. The laterally diffused metal oxide semiconductor device of claim 7, further comprising: and the second conductive structures are positioned on partial top surfaces of the plurality of third conductive structures.
9. The laterally diffused metal oxide semiconductor device of claim 2, further comprising: and the source regions are positioned in the second fin parts on one side of the main grid electrode structure.
10. The ldmos device of claim 9 further comprising: and the second dummy gate structures cross the plurality of second fin parts, and the second dummy gate structures and the main gate structures are respectively positioned at two sides of the source region.
11. The laterally diffused metal oxide semiconductor device of claim 2, further comprising: and the fourth conductive structure is positioned on the source region and spans the second fin parts.
12. The ldmos device of claim 11, wherein a dimension of the first conductive structure in a direction in which the first fin extends is larger than a dimension of the fourth conductive structure in a direction in which the second fin extends.
13. The laterally diffused metal oxide semiconductor device of claim 1, further comprising: and the first dielectric layer is positioned on the substrate and covers the first conductive structure and the side wall surfaces of the plurality of first dummy gate structures.
14. The laterally diffused metal oxide semiconductor device of claim 1, further comprising: and the isolation structure is positioned on the surface of the side wall of the first fin part, and the top surface of the isolation structure is lower than that of the first fin part.
15. A method for forming a laterally diffused metal oxide semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, and a plurality of first fin parts which are arranged in parallel are arranged on the substrate of the first area;
forming first well regions in the plurality of first fin portions and the first region of the substrate;
after the first well region is formed, at least one first dummy gate structure is formed on the surfaces of the plurality of first fin portions;
forming a drain region in each first fin portion respectively, wherein the drain region is located on one side of the first dummy gate structure;
and forming a first conductive structure on the drain region, wherein the first conductive structure spans the plurality of first fin parts.
16. The method of claim 15, wherein the number of the first dummy gate structures is greater than or equal to 2, and a plurality of the first dummy gate structures are arranged in parallel; the drain region is positioned in the first fin part between two adjacent first dummy gate structures; the forming method of the drain region comprises the following steps: removing part of the substrate between the first dummy gate structures, and forming a first groove in a first region of the substrate; and forming a source and drain region material layer in the first groove so as to form a drain region.
17. The method of forming a ldmos device as claimed in claim 15 further comprising: after the first dummy gate structure is formed and before the first conductive structure is formed, forming a first dielectric layer on the substrate; the forming method of the first conductive structure comprises the following steps: forming a first contact hole in the first dielectric layer, wherein the bottom of the first contact hole is exposed out of the top surface of the drain region; filling a conductive material in the first contact hole to form a first conductive structure material film, wherein the first conductive structure material film is filled in the first contact hole, and the top surface of the first conductive structure material film is higher than that of the first medium layer; and flattening the first conductive structure material film until the top surface of the first dielectric layer is exposed to form the first conductive structure.
18. The method of forming a ldmos device as claimed in claim 17 further including: after forming the first conductive structure, a second conductive structure is formed on the first dummy gate structure.
19. The method of forming a ldmos device as claimed in claim 17 further including: after the first conductive structures are formed and before the second conductive structures are formed, third conductive structures are formed on the surfaces of the plurality of first dummy gate structures respectively, and the second conductive structures are located on the surfaces of the plurality of third conductive structures.
20. The method of claim 15, wherein the second region of the substrate has a plurality of second fins arranged in parallel thereon, the second fins extending from the second region to the substrate in the first region, the second fins being discrete from the first fins; the method for forming the laterally diffused metal oxide semiconductor device further comprises the following steps: forming second well regions in the plurality of second fin portions and the second region of the substrate, wherein the second well regions are in contact with the first well regions; forming a main gate structure crossing the plurality of second fin portions, wherein the main gate structure extends from the second region to the first region, and the main gate structure is located on part of the tops and part of the side wall surfaces of the second fin portions; after the main grid electrode structure is formed, forming a plurality of source regions in each second fin part on one side of the main grid electrode structure; and after the source region is formed, forming a fourth conductive structure on the source region, wherein the fourth conductive structure spans the plurality of second fin parts.
CN201910022854.2A 2019-01-10 2019-01-10 Laterally diffused metal oxide semiconductor device and method of forming the same Active CN111430460B (en)

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Publication number Priority date Publication date Assignee Title
CN106558507A (en) * 2015-09-23 2017-04-05 中芯国际集成电路制造(北京)有限公司 Test structure and forming method thereof, method of testing
CN106920788A (en) * 2015-12-25 2017-07-04 中芯国际集成电路制造(上海)有限公司 ESD-protection structure and forming method thereof
CN107045982A (en) * 2016-02-05 2017-08-15 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106558507A (en) * 2015-09-23 2017-04-05 中芯国际集成电路制造(北京)有限公司 Test structure and forming method thereof, method of testing
CN106920788A (en) * 2015-12-25 2017-07-04 中芯国际集成电路制造(上海)有限公司 ESD-protection structure and forming method thereof
CN107045982A (en) * 2016-02-05 2017-08-15 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure

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