CN106920788A - ESD-protection structure and forming method thereof - Google Patents
ESD-protection structure and forming method thereof Download PDFInfo
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- CN106920788A CN106920788A CN201510995357.2A CN201510995357A CN106920788A CN 106920788 A CN106920788 A CN 106920788A CN 201510995357 A CN201510995357 A CN 201510995357A CN 106920788 A CN106920788 A CN 106920788A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
Abstract
A kind of ESD-protection structure and forming method thereof, ESD-protection structure includes：Substrate with first area, second area and the 3rd region, first area both sides are adjacent with second area and the 3rd region respectively；Positioned at first fin some arranged in parallel on substrate first area surface, the first fin have extend to the first end of second area and extend to second end in the 3rd region；Positioned at second fin on substrate second area surface, the second fin is connected with the first end of some first fins；Positioned at the 3rd fin of the region surface of substrate the 3rd, the 3rd fin is connected with the second end of some first fins；Across the first grid structure of some first fins, first grid structure is located at the side wall and top surface of the fin of part first；Source region in the second fin and the fin of part first；Drain region in the 3rd fin.The performance improvement of ESD-protection structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of ESD-protection structure and its
Forming method.
Background technology
As the utilization of semiconductor chip is more and more extensive, cause semiconductor chip be subject to electrostatic damage because
Element is also more and more.In the design of existing chip, frequently with static discharge (ESD, Electrostatic
Discharge) protection circuit is damaged with reducing chip.The design of existing ESD protection circuit and should
With including：Grid ground connection field-effect transistor (Gate Grounded NMOS, GGNMOS) protection circuit,
Controllable silicon (Silicon Controlled Rectifier, SCR) protection circuit, horizontal proliferation field effect transistor
Pipe (Laterally Diffused MOS, LDMOS) protection circuit etc..
Fig. 1 is the cross-sectional view of the field-effect transistor protection structure of existing grid ground connection, including：
Substrate 10；N-type well region 11 in substrate 10；Positioned at the grid structure 12 on the surface of N-type well region 11；Position
In the drain electrode 14 of the source electrode 13 and p-type of the p-type in the N-type well region 11 of the both sides of grid structure 12.The p-type source
Pole 13, P type trap zone 11 and N-type drain 14 constitute a parasitic PNP triode；Wherein, the source electrode 13 is
The emitter stage of parasitic triode, the drain electrode 14 is the colelctor electrode of parasitic triode, and the well region 11 is to post
The base of raw triode；The grounded-grid of the source electrode 13, well region 11 and grid structure 12, external circuit
Electrostatic potential input drain electrode 14, the external circuit is electrically connected with chip internal circuits, for driving core
Piece internal circuit works.
With the development of semiconductor technology so that the size of semiconductor devices constantly reduces, device density is not
Disconnected to improve, existing ESD protection circuit structure cannot meet technical need, it is necessary to be put in electrostatic
Fin formula field effect transistor is introduced in electric protection circuit structure.
However, as the size of semiconductor devices further reduces, even if in ESD protection circuit
Using fin formula field effect transistor, its performance is still unstable.
The content of the invention
The problem that the present invention is solved is to provide a kind of ESD-protection structure and forming method thereof, described quiet
The performance improvement of discharge of electricity protection structure.
To solve the above problems, the present invention provides a kind of ESD-protection structure, including：Substrate, institute
Stating substrate has first area, second area and the 3rd region, and the first area both sides are respectively with second
Region and the 3rd region are adjacent；Positioned at first fin some arranged in parallel on substrate first area surface,
First fin have extend to the first end of second area and extend to second end in the 3rd region；
Positioned at second fin on substrate second area surface, the first end of second fin and some first fins
Connection；Positioned at the 3rd fin of the region surface of substrate the 3rd, the 3rd fin and some first fins
Second end connects；Positioned at the separation layer of the substrate surface, the separation layer cover first fin,
The partial sidewall of the second fin and the 3rd fin, and the insulation surface is less than first fin, the
The top surface of two fins and the 3rd fin；Across the first grid structure of some first fins, described
One grid structure is located at the side wall and top surface of the fin of part first；Positioned at the second fin and part first
Source region in fin；Drain region in the 3rd fin.
Optionally, there is well region in the substrate, the first fin, the second fin and the 3rd fin, it is described
There is N-type ion in well region.
Optionally, there is p-type ion in the source region and drain region.
Optionally, also include：Some second grid structures in second area, the second grid
Structure is located at least in the second fin top surface, and some second grid parallelism structurals are arranged, and described second
Grid structure is parallel to first grid structure.
Optionally, the source region includes：Between adjacent second grid structure and first grid knot
Source region epitaxial layer between structure and second grid structure, the source region epitaxial layer be located at first fin and
The top of the second fin.
Optionally, the material of the source region epitaxial layer is silicon or SiGe；Doped with P in the source region epitaxial layer
Type ion.
Optionally, the second grid structure includes second grid；The second grid and electrostatic potential end
Connection.
Optionally, some 3rd grid structures in the 3rd region, the 3rd grid structure is at least
Positioned at the 3rd fin top surface, some 3rd grid structures are arranged in parallel, and the 3rd grid structure
Parallel to first grid structure.
Optionally, the drain region includes：Drain extensions layer between adjacent 3rd grid structure, institute
State the top that drain extensions layer is located at the 3rd fin.
Optionally, the material of the drain extensions layer is silicon or SiGe；Doped with P in the source region epitaxial layer
Type ion.
Optionally, the 3rd grid structure includes the 3rd grid；3rd grid and electrostatic potential end
Connection.
Optionally, also include：Lightly doped district in the first fin of first grid structure both sides；Its
In, the lightly doped district of side is located between first grid structure and the 3rd grid structure.
Optionally, the first grid structure includes first grid.
Optionally, also include：The first conductive structure at the top of the first grid；Described first leads
Electric grounding structure.
Optionally, also include：The second conductive structure at the top of source region；Second conductive structure connects
Ground.
Optionally, also include：The 3rd conductive structure at the top of drain region；3rd conductive structure with
Electrostatic potential end connects.
Accordingly, the present invention also provides a kind of formation of the ESD-protection structure described in any of the above-described
Method, including：Substrate is provided, the substrate has first area, second area and the 3rd region, institute
State first area both sides adjacent with second area and the 3rd region respectively, substrate first area surface tool
Have some first fins arranged in parallel, first fin have extend to the first end of second area with
And extend to second end in the 3rd region, and the substrate second area surface has the second fin, and described the
Two fins are connected with the first end of some first fins, the 3rd fin of the region surface of the substrate the 3rd,
3rd fin is connected with the second end of some first fins；Separation layer is formed in the substrate surface,
The separation layer covers the partial sidewall of first fin, the second fin and the 3rd fin, and it is described every
Top surface of the absciss layer surface less than first fin, the second fin and the 3rd fin；If being developed across
The first grid structure of dry first fin, the first grid structure be located at the fin of part first side wall and
Top surface；Form source region in the second fin and the fin of part first and positioned at the 3rd fin
Interior drain region.
Optionally, while first grid structure is formed, some second grids are formed in second area
Structure, forms some 3rd grid structures in the 3rd region；The second grid structure is located at least in
Two fin top surfaces, the arrangement of some second grid parallelism structurals, and the second grid parallelism structural in
First grid structure；3rd grid structure is located at least in the 3rd fin top surface, some 3rd grid
Pole parallelism structural arrangement, and the 3rd grid structure is parallel to first grid structure.
Optionally, the forming step for stating source region and drain region includes：Form the first opening and the second opening, institute
The first opening is stated to be located between adjacent second grid structure and first grid structure and second grid structure
Between the first fin and the second fin in, it is described second opening be located at adjacent 3rd grid structure between
In 3rd fin；Source region epitaxial layer is formed in the described first opening using epitaxy technique, described second
Drain extensions layer is formed in opening；The doped p-type ion in the source region epitaxial layer and drain extensions layer.
Compared with prior art, technical scheme has advantages below：
In structure of the invention, the source region is located in the second fin, and drain region is located in the 3rd fin, and
After the raceway groove between source region and drain region is opened, electrostatic charge can be subject in electrostatic charge input drain region
The driving of electrical potential difference is conveyed to each first fin, until source region is exported.Due to positioned at substrate second area
The second fin be connected with the first end of some first fins, positioned at the region of substrate the 3rd the 3rd fin with
Some first fins the second end connection, therefore each first fin first end and the second end between voltage
It is homogeneous, and ensure that the raceway groove in the first fin can be while open such that it is able to ensure each first fin
Electric current in portion is homogeneous, and is conducive to increasing the electric current of source region output.Further, since the drain region position
In in the 3rd fin, then there is certain distance between the drain region and first grid structure, be conducive to avoiding
Puncture because the potential in drain region is too high in grid structure such that it is able to avoid ESD-protection structure
Fail.
In the method for the present invention, source region is formed in second fin, drain region is formed in the 3rd fin,
Electrostatic charge is input into from drain region, until the raceway groove between source region and drain region is opened, the electrostatic charge can
Conveyed to each first fin by the driving of electrical potential difference, until source region is exported.Due to second fin
First end with some first fins is connected, and the 3rd fin is connected with the second end of some first fins,
Therefore the voltage between the first end of each first fin and the second end is homogeneous, and ensure that in the first fin
Raceway groove can open simultaneously such that it is able to ensure that the electric current in each first fin is homogeneous, be conducive to increase
The electric current of source region output.Further, since the drain region is located in the 3rd fin, then the drain region and first
There is certain distance between grid structure, be conducive to avoiding being sent out because the potential in drain region is too high in grid structure
Life punctures such that it is able to avoid ESD-protection structure from failing.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the field-effect transistor protection structure of existing grid ground connection；
Fig. 2 and Fig. 3 are a kind of cross-sectional views of ESD protection circuit structure；
Fig. 4 to Figure 13 is the cross-section structure of the forming process of the ESD-protection structure of the embodiment of the present invention
Schematic diagram.
Specific embodiment
As stated in the Background Art, as the size of semiconductor devices further reduces, even if in static discharge
Fin formula field effect transistor is used in protection circuit circuit, its performance is still unstable.
Refer to Fig. 2 and Fig. 3, Fig. 2 and Fig. 3 is a kind of cross-section structure of ESD protection circuit structure
Schematic diagram, Fig. 2 is cross-sectional views of the Fig. 3 along AA ' directions.The ESD protection circuit
Structure includes：Substrate 100, the surface of the substrate 100 has some fins 101 arranged in parallel, described
The surface of substrate 100 has separation layer 102, and the separation layer 102 covers the partial sidewall of the fin 101
There is well region 103 in surface, the fin 101 and section substrate 100；Across the side wall of some fins 101
With the grid structure 106 of top surface；It is outer at the top of the fin 101 of the both sides of the grid structure 106
Prolong in layer 104, the epitaxial layer 104 doped with N-type ion or p-type ion；Positioned at separation layer 102,
Fin 101 and the dielectric layer 108 on the surface of grid structure 106.It should be noted that Fig. 3 is to ignore medium
The overlooking the structure diagram of layer 108.
The ESD protection circuit structure is formed based on fin 101.Wherein, respectively positioned at grid knot
The epitaxial layer 104 of the both sides of structure 106 forms doping in source region 107a and drain region 107b, and epitaxial layer 104
Ion and the interior ion transoid adulterated of well region 103.The grid structure 106 and source region 107a and drain region 107b
Composition nmos pass transistor or PMOS transistor, and the field that the ESD protection circuit is grounded by grid
Effect transistor is constituted.The electrostatic potential access drain region 107b, and well region 103, source region 107a and grid
Pole structure 106 is grounded.
However, as dimensions of semiconductor devices diminution, device density are improved, the width of the fin 101
Size reduction.And the source region 107a and drain region 107b with the well region 103 in the fin 101
It is in contact, therefore, the width dimensions of the fin 101 determine the source region 107a and drain region 107b
With the contact area of the well region 103.Because the width dimensions of the fin 101 are smaller, cause described
Source region 107a and drain region 107b are smaller with the contact area of the well region 103, then the breakdown potential in PN junction
Stream is smaller, and the charge buildup in the drain region 107b is serious.Therefore, the ESD protection circuit
Not only electrostatic discharge capacity is weaker for structure, is also easy to be produced from the fin 101 where the drain region 107b
Fever phenomenon, causes the work efficiency drop of the ESD protection circuit structure, and under service life
Drop.
The grid structure 106 is additionally, since across some fins 101, and electrostatic potential is tied by conductive
Structure accesses some drain region 107b simultaneously, until electrostatic charge is discharged by conductive structure from source region 107a.By
Had differences when electrostatic charge is into each drain region 107b, be easily caused based on each of the formation of each fin 101
The breakdown voltage of the field-effect transistor of grid ground connection has differences, and causes ESD protection circuit structure
Less stable.
In order to solve the above problems, the present invention provides a kind of ESD-protection structure, including：Substrate,
The substrate has first area, second area and the 3rd region, and the first area both sides are respectively with
Two regions and the 3rd region are adjacent；Positioned at first fin some arranged in parallel on substrate first area surface,
First fin have extend to the first end of second area and extend to second end in the 3rd region；
Positioned at second fin on substrate second area surface, the first end of second fin and some first fins
Connection；Positioned at the 3rd fin of the region surface of substrate the 3rd, the 3rd fin and some first fins
Second end connects；Positioned at the separation layer of the substrate surface, the separation layer cover first fin,
The partial sidewall of the second fin and the 3rd fin, and the insulation surface is less than first fin, the
The top surface of two fins and the 3rd fin；Across the first grid structure of some first fins, described
One grid structure is located at the side wall and top surface of the fin of part first；Positioned at the second fin and part first
Source region in fin；Drain region in the 3rd fin.
Wherein, the source region is located in the second fin, and drain region is located in the 3rd fin, and electrostatic charge is defeated
After entering drain region until the raceway groove between source region and drain region is opened, electrostatic charge can be subject to electrostatic potential
Drive and conveyed to each first fin, until source region is exported.Due to the second fin positioned at substrate second area
Portion is connected with the first end of some first fins, positioned at the 3rd fin and some first in the region of substrate the 3rd
Fin the second end connection, therefore each first fin first end and the second end between voltage it is homogeneous, and
Ensure that the raceway groove in the first fin can be while open such that it is able to ensure the electricity in each first fin
Stream is homogeneous, and is conducive to increasing the electric current of source region output.Further, since the drain region is located at the 3rd fin
In portion, then there is certain distance between the drain region and first grid structure, be conducive to avoiding grid structure
It is interior to puncture because the potential in drain region is too high such that it is able to avoid ESD-protection structure from failing.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.
Fig. 4 to Figure 13 is the structural representation of the forming process of the ESD-protection structure of the embodiment of the present invention
Figure.
Refer to Fig. 4 and Fig. 5, Fig. 4 is cross-sectional views of the Fig. 5 along BB ' directions, there is provided substrate
200, the substrate 200 has first area 210, the region 230 of second area 220 and the 3rd, described
The both sides of first area 210 are adjacent with the region 230 of second area 220 and the 3rd respectively, the substrate 200
The surface of first area 210 has some first fins 211 arranged in parallel, and first fin 211 has
The first end for extending to second area 220 and the second end for extending to the 3rd region 230, the substrate
The surface of second area 220 has the second fin 221, second fin 221 and some first fins 211
First end connection, the 3rd fin 231 on the surface of the 3rd region of substrate 230, the 3rd fin
231 are connected with the second end of some first fins 211.
In the present embodiment, the ESD-protection structure for being formed is made up of grid ground connection field-effect transistor.
And, the grid ground connection field-effect transistor is fin formula field effect transistor.
In the present embodiment, the first area 210 is used to be formed the grid of field-effect transistor, described
Second area 220 is used to be formed the source electrode of field-effect transistor, and the 3rd region 230 is used to form field
The drain electrode of effect transistor.Wherein, the source electrode and grounded-grid, the drain electrode are connected with electrostatic potential.
When the ESD-protection structure for being formed works, electrostatic charge is input into from the drain electrode, until grid connect
The raceway groove of ground field-effect transistor is opened, and electrostatic charge is flowed into source electrode from channel region and is discharged.So as to reach
To the purpose for avoiding electrostatic charge from causing to damage to the device in other regions of substrate 200.
In the present embodiment, the grid ground connection field-effect transistor is p type field effect transistor.At other
In embodiment, the grid ground connection field-effect transistor is n type field effect transistor.
The quantity of the first fin 211 of the first area 210 is more than 1, and some first fins 211
It is arranged in parallel；The width at the top of first fin 211 is less than 20 nanometers, such as 14 nanometers；It is adjacent
The distance between first fin 211 is 50 nanometers~60 nanometers.It is described in the second area 220
The quantity of the second fin 221 is at least 1, and each the second fin 221 and at least two the first fins
211 first end connection.In the 3rd region 230, the quantity of the 3rd fin 231 is at least
1, and each the 3rd fin 231 is connected with the second end of at least two article first fin 211.
It is used to be formed the grid of field-effect transistor, therefore first fin due to the first area 210
The channel region of field-effect transistor can be formed in portion 211.3rd fin 231 is used to form field effect
The drain electrode of transistor is answered, the second fin 221 is used to be formed the source electrode of field-effect transistor, due to some the
The two ends of one fin 211 are connected with same second fin 221 and same 3rd fin 231 respectively, therefore,
After electrostatic charge is input into drain, electrostatic charge is to accumulate in the 3rd fin 231.When the first fin 211
After interior channel region is opened, because the electrical potential difference at each two ends of first fin 211 is identical, therefore, electrostatic
Electric charge can uniformly be input into each first fin 211, and come together in the second fin 221 further to export.
Time and the quantity variance of each first fin 211 are input into due to avoiding electrostatic charge, so as to
Enough ensure that the voltage at the two ends of the first fin of each bar 211 is homogeneous, and electric current in the first fin of each bar 211 is equal
Weighing apparatus.And, the electric current increase between the second fin 221 and the 3rd fin 231 such that it is able to improve
The efficiency of discharge electrostatic charges.
In the present embodiment, the substrate 200, the first fin 211, the second fin 221 and the 3rd fin
231 forming step includes：Semiconductor base is provided；Patterned layer is formed in the semiconductor substrate surface,
The patterned layer covering needs the area to form the first fin 211, the second fin 221 and the 3rd fin 231
Domain position；With the patterned layer as mask, etching semiconductor substrate, formed the substrate 200 and
The first fin 211, the second fin 221 and the 3rd fin 231 positioned at the surface of substrate 200；In etching institute
State after semiconductor base, remove the patterned layer.
The semiconductor base is monocrystalline substrate, single-crystal germanium substrate, silicon-Germanium substrate or silicon carbide substrates.
In the present embodiment, the semiconductor base is monocrystalline substrate.The patterned layer includes patterned
Photoresist layer, can also have mask layer, institute between the patterned photoresist layer and semiconductor base
The material for stating mask layer includes silicon nitride.The technique for etching the semiconductor base is anisotropic dry method
Etching technics, the side wall of the first fin 211, the second fin 221 and the 3rd fin 231 that are formed is relative
It is vertical in the surface of substrate 200 or incline；When first fin 211, the second fin 221 and the 3rd fin
When 231 side wall is inclined relative to the surface of substrate 200, first fin 211, the and of the second fin 221
The top dimension of the 3rd fin 231 is less than bottom size.
In another embodiment, the shape of first fin 211, the second fin 221 and the 3rd fin 231
Include into step：Fin layer is formed on the surface of substrate 200 using epitaxy technique；The fin layer is etched,
Form first fin 211, the second fin 221 and the 3rd fin 231.The substrate 200 is served as a contrast for silicon
Bottom, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium substrate on insulator, glass substrate
Or III-V substrate, such as gallium nitride substrate or gallium arsenide substrate etc.；The material of the fin layer
It is silicon, germanium, carborundum or SiGe.
There is well region in the substrate 200, the first fin 211, the second fin 221 and the 3rd fin 231.
In the present embodiment, there is N-type ion in the well region；The N-type ion include phosphonium ion or arsenic from
Son.In other embodiments, there is p-type ion in the well region.The well region is in etching semiconductor base
Formed before or after bottom；The formation process of the well region is ion implantation technology.
Fig. 6 is refer to, separation layer 201 is formed on the surface of the substrate 200, the separation layer 201 is covered
The partial sidewall of first fin 211, the second fin 221 and the 3rd fin 231, and the separation layer
Top surface of 201 surfaces less than first fin 211, the second fin 221 and the 3rd fin 231.
It should be noted that Fig. 6 is the cross-sectional view based on Fig. 4.
The separation layer 201 is used to isolate the first adjacent fin 211, the second fin 221 or the 3rd fin
231.The material of the separation layer 201 is silica, silicon nitride, silicon oxynitride, low-K dielectric material (Jie
Electric constant more than or equal to 2.5, less than 3.9), in ultralow K dielectric materials (dielectric constant is less than 2.5)
One or more combination.In the present embodiment, the material of the separation layer 201 is silica.
The forming step of the separation layer 201 includes：In the substrate 200, the first fin 211, second
Fin 221 or the surface of the 3rd fin 231 form barrier film；The barrier film is planarized until exposing institute
Untill stating the top surface of the first fin 211, the second fin 221 or the 3rd fin 231；In planarization institute
State after barrier film, be etched back to the barrier film, expose part the first fin 211, the second fin 221
Or the sidewall surfaces of the 3rd fin 231, form separation layer 201.
The formation process of the barrier film be chemical vapor deposition method or physical gas-phase deposition, for example
Fluid chemistry vapour deposition (FCVD, Flowable Chemical Vapor Deposition) technique, etc. from
Daughter strengthens chemical vapor deposition method or high-aspect-ratio chemical vapor deposition method (HARP)；It is described flat
Smooth chemical industry skill is CMP process；The technique that is etched back to is for anisotropic dry etch process.
In the present embodiment, the formation process of the barrier film is fluid chemistry gas-phase deposition, using institute
The barrier film for stating the formation of fluid chemistry gas-phase deposition is easy to the groove being packed between adjacent fin 201
It is interior, formed barrier film even compact can be made, then the isolation performance of separation layer 201 for being formed is good.
Refer to Fig. 7 and Fig. 8, Fig. 7 is cross-sectional views of the Fig. 8 along BB ' directions, is developed across
The first grid structure 212 of some first fins 211, the first grid structure 212 is located at part first
The side wall and top surface of fin 211.
It should be noted that the first grid structure 212 of Fig. 8 illustrate only first grid, second grid
Structure 222 illustrate only second grid, and the 3rd grid structure 232 illustrate only the 3rd grid.
In the present embodiment, while first grid structure 212 are formed, the shape in second area 220
Into some second grid structures 222, some 3rd grid structures 232 are formed in the 3rd region 230.Institute
State second grid structure 222 and be located at least in the top surface of the second fin 221, some second grid structures 222
It is arranged in parallel, and the second grid structure 222 is parallel to first grid structure 212；3rd grid
Structure 232 is located at least in the top surface of the 3rd fin 231, and some 3rd grid structures 232 are arranged in parallel,
And the 3rd grid structure 232 is parallel to first grid structure 212.
In the present embodiment, the quantity of the second grid structure 222 is 2, the 3rd grid knot
The quantity of structure 232 is 2.
In the present embodiment, the first grid structure 212 is used to form grid ground connection field-effect transistor
Grid.The second grid structure 222 is used to control to be subsequently formed the source region extension in second area 220
The size of layer；3rd grid structure 232 is used to control to be subsequently formed in the drain region in the 3rd region 230
The size of epitaxial layer.On parallel to the direction on the surface of substrate 200, the first grid structure 212
Width dimensions of the width dimensions more than the grid structure 232 of the second grid structure 222 or the 3rd.
In the present embodiment, the first grid structure 212 includes first grid.The second grid knot
Structure 222 includes second grid；The second grid is used to be connected with electrostatic potential end.3rd grid
Structure 232 includes the 3rd grid；3rd grid is used to be connected with electrostatic potential end.
The first grid structure 212 also includes be located between first grid and the first fin 211 first
Gate dielectric layer；Positioned at the first mask layer of the first grid top surface；Positioned at first grid and first
First side wall of gate dielectric layer sidewall surfaces.The second grid structure 222 also includes being located at second grid
With the second gate dielectric layer between the second fin 221；Positioned at the second grid top surface second covers
Film layer；Positioned at second grid and the second side wall of the second gate dielectric layer sidewall surfaces.The 3rd grid knot
Structure 232 also includes the 3rd gate dielectric layer being located between the 3rd grid and the 3rd fin 231；Positioned at described
3rd mask layer of the 3rd gate top surface；Positioned at the 3rd grid and the 3rd gate dielectric layer sidewall surfaces
3rd side wall.
The material of the first grid, second grid and the 3rd grid is polysilicon；First gate medium
The material of layer, the second gate dielectric layer and the 3rd gate dielectric layer is silica；First side wall, the second side
The material of wall and the 3rd side wall is one or more combination in silica, silicon nitride and silicon oxynitride.
First mask layer forms the mask of first grid as etching, and second mask layer is used as quarter
Erosion forms the mask of second grid, and the 3rd mask layer forms the mask of the 3rd grid as etching.Institute
It is silica, silicon nitride and nitrogen oxidation to state the first mask layer, the second mask layer, the material of the 3rd mask layer
One or more combination in silicon.
In another embodiment, the first grid structure 212, the grid of second grid structure 222 and the 3rd
Structure 232 is dummy gate structure.The first grid structure 212 includes the first dummy grid；Described second
Grid structure 222 includes the second dummy grid；3rd grid structure 232 includes the 3rd dummy grid.Institute
The material for stating the first dummy grid, the second dummy grid and the 3rd dummy grid is polysilicon.It is follow-up to form source region
After drain region, first dummy grid is removed, and substituted with the first gate dielectric layer and first grid, gone
Except the second dummy grid, and substituted with the second gate dielectric layer and second grid, the 3rd dummy grid of removal, and with
3rd gate medium and the 3rd grid are substituted.
The material of the first grid, second grid and the 3rd grid is metal；The metal include copper,
One or more in tungsten, aluminium, silver, titanium nitride, tantalum nitride, titanium-aluminium alloy.First gate medium
The material of layer, the second gate dielectric layer and the 3rd gate dielectric layer is high K dielectric material (dielectric coefficient is more than 3.9).
Fig. 9 is refer to, lightly doped district is formed in the first fin 211 of the both sides of first grid structure 212
213。
In the present embodiment, the grid ground connection field-effect transistor for being formed is PMOS transistor, described light
Doped with p-type ion in doped region 213.In other embodiments, the grid ground connection field-effect for being formed is brilliant
Body pipe is doped with N-type ion in nmos pass transistor, the lightly doped district 213.
The lightly doped district 213 is formed using ion implantation technology.In the present embodiment, the ion note
Enter technique with first grid structure 212, the grid structure 232 of second grid structure 222 and the 3rd as mask,
Lightly doped district described in first for being formed be located at the grid structure 232 of first grid structure 212 and the 3rd between,
Between first grid structure 212 and second grid structure 222, between adjacent second grid structure 222,
And the 3rd between grid structure 232.
Refer to Figure 10, formed source region in the second fin 221 and the first fin of part 211, with
And the drain region in the 3rd fin 231.
In the present embodiment, the grid ground connection field-effect transistor for being formed is PMOS transistor, the source
There is p-type ion in area and drain region；And, the p-type ion concentration in the source region and drain region is higher than light
Doped region 213.In other embodiments, the grid ground connection field-effect transistor for being formed is NMOS crystal
Pipe, has N-type ion in the source region and drain region.
In the present embodiment, the source region includes：Between adjacent second grid structure 222 and
Source region epitaxial layer 223 between first grid structure 212 and second grid structure 222, the source region extension
Layer 223 is located at the top of the fin 221 of first fin 211 and second.The drain region includes：It is located at
Drain extensions layer 233 between adjacent 3rd grid structure 232, the drain extensions layer 233 is located at described
The top of the 3rd fin 231.
The forming step in the source region and drain region includes：Form the first opening and the second opening, described first
Opening is located between adjacent second grid structure 222 and first grid structure 212 and second grid knot
In the first fin 211 and the second fin 221 between structure 222, second opening is located at the adjacent 3rd
In the 3rd fin 231 between grid structure 232；Formed in the described first opening using epitaxy technique
Source region epitaxial layer 223, forms drain extensions layer 233 in the described second opening；In the source region epitaxial layer
223 and drain extensions layer 233 in doped p-type ion.
The forming step of first opening and the second opening includes：In the separation layer 201, the first fin
211st, the sidewall surfaces of the second fin 221 and the 3rd fin 231 form barrier layer, the barrier layer exposure
Go out the top surface of the second fin 221, the top surface of the 3rd fin 231 and positioned at first grid structure
The top surface of the first fin of part 211 between 212 and second grid structure 222；It is with the barrier layer
Mask, etches first fin 211, the second fin 221 and the 3rd fin 231, forms first and is open
With the second opening.
The etching technics includes anisotropic dry etch process, the first opening for being formed and second
Top surface of the side wall of opening perpendicular to the first fin 211, the second fin 221 and the 3rd fin 231.
In other embodiments, after the dry etch process of the opposite sex, additionally it is possible to be open to described first
Wet-etching technology is carried out with the second opening；The wet-etching technology can be carved for isotropic wet method
Etching technique or anisotropic wet-etching technology.
The material of the source region epitaxial layer 223 is silicon or SiGe；Doped with P in the source region epitaxial layer 223
Type ion.In the present embodiment, the material of the source region epitaxial layer 223 is SiGe, and formation process is choosing
Selecting property epitaxial deposition process；The selective epitaxial depositing operation includes：Temperature is 500 degrees Celsius~800
Degree Celsius, air pressure is 1 support~100 support, and process gas includes silicon source gas (SiH4Or SiH2Cl2) and germanium
Source gas (GeH4), the flow of the silicon source gas or ge source gas is 1 standard milliliters/minute~1000
Standard milliliters/minute, the process gas also includes HCl and H2, the flow of the HCl for 1 standard in the least
Liter/min~1000 standard milliliters/minute, H2Flow be 0.1 standard liter/min~50 standard liter/min.
In the selective epitaxial deposition process, can be using doping process in situ in source region epitaxial layer 223
Interior doped p-type ion.
The material of the drain extensions layer 233 is silicon or SiGe；Doped with P in the drain extensions layer 233
Type ion.In the present embodiment, the material of the source region epitaxial layer 223 is silicon, and formation process is selection
Property epitaxial deposition process；The selective epitaxial depositing operation includes：Temperature is taken the photograph for 500 degrees Celsius~800
Family name's degree, air pressure is 1 support~100 support, and process gas includes silicon source gas (SiH4Or SiH2Cl2), it is described
The flow of silicon source gas is 1 standard milliliters/minute~1000 standard milliliters/minute, and the process gas is also wrapped
Include HCl and H2, the flow of the HCl is 1 standard milliliters/minute~1000 standard milliliters/minute, H2
Flow be 0.1 standard liter/min~50 standard liter/min.In the selective epitaxial deposition process
In, can be using doping process doped p-type ion in source region epitaxial layer 223 in situ.
Because the surface of the second fin 221 is formed with some second grid structures 222, therefore, work as use
Epitaxy technique is between adjacent first grid structure 212 and second grid structure 222 and adjacent second
When forming source region epitaxial layer 223 between grid structure 222, the second grid structure 222 can suppress
The growth of source region epitaxial layer 223, it is to avoid the volume of the source region epitaxial layer 223 is excessive, so as to be conducive to
Bridged between the source region epitaxial layer 223 for avoiding the top of adjacent first fin 211, and be conducive to subtracting
The resistance of small formed source region epitaxial layer 223, so as to increase the electric current of source region discharge electrostatic charges；This
Outward, additionally it is possible to avoid protruding the first fin because of the source region epitaxial layer 223 formed close to first grid structure 212
The size of the top surface of portion 211 excessively produces excessive parasitic capacitance between first grid structure, from
And the parasitic load that formed grid are grounded field-effect transistor is reduced, improve formed static discharge
The operating efficiency of protection structure.
Because the surface of the 3rd fin 231 is formed with some 3rd grid structures 232, therefore, work as use
When epitaxy technique forms drain extensions layer 233 between adjacent 3rd grid structure 232, the 3rd grid
Pole structure 232 can suppress the growth of drain extensions layer 233, so as to be conducive to reducing formed drain region
The resistance of epitaxial layer 233, it is to avoid drain region overheats because of build-up of electrostatic charges.It is additionally, since the drain region
Epitaxial layer 233 is only formed in the 3rd fin 231, and the grid of adjacent first grid structure 212 and the 3rd
There is lightly doped district 213, i.e., between drain extensions layer 233 and first grid structure 212 between structure 232
It is spaced by the grid structure 232 of lightly doped district 213 and the 3rd, is conducive to avoiding drain extensions 233 internal cause of layer
The first gate medium that build-up of electrostatic charges and the too high voltages that produce puncture in the first grid structure 212
Layer, so as to avoid the failure that grid are grounded field-effect transistor, improves formed electrostatic discharge (ESD) protection
The yield and reliability of structure.
Figure 11 is refer to, in the separation layer 201, the first fin 211, the second fin 221, the 3rd fin
Portion 231, source region, drain region, first grid structure 212, the grid structure of second grid structure 222 and the 3rd
232 surfaces form dielectric layer 202.
In the present embodiment, the forming step of the dielectric layer 202 includes：In the substrate and dummy grid
Body structure surface forms deielectric-coating；The deielectric-coating is planarized, the dielectric layer 202 is formed.
The formation process of the deielectric-coating is chemical vapor deposition method, physical gas-phase deposition or atom
Layer depositing operation；The chemical vapor deposition method can for fluid chemistry gas-phase deposition (FCVD,
Flowable Chemical Vapor Deposition), plasma enhanced chemical vapor deposition technique
Or high-aspect-ratio chemical vapor deposition method (HARP) (PECVD).The flatening process is change
Learn mechanical polishing process.
The material of the dielectric layer 202 is silica, silicon nitride, silicon oxynitride, low k dielectric materials (Jie
Electrostrictive coefficient is such as porous silica or porous silicon nitride more than or equal to 2.5, less than 3.9) or it is super
Low k dielectric materials (dielectric coefficient is less than 2.5, such as porous SiC OH).
In another embodiment, first grid structure 212, the grid structure of second grid structure 222 and the 3rd
232 is dummy gate structure.The dielectric layer 202 includes：First sub- dielectric layer and the second sub- dielectric layer；Institute
The first sub- dielectric layer is stated positioned at the separation layer 201, the first fin 211, the second fin 221, the 3rd fin
Portion 231, source region and drain region surface；The second sub- dielectric layer is located at the first sub- dielectric layer, first grid knot
Structure 212, second grid structure 222 and the surface of the 3rd grid structure 232.Wherein, the described first sub- medium
Surface and the first grid structure 212 of layer, the grid structure 232 of second grid structure 222 and the 3rd
Top surface is flushed.
After the first sub- dielectric layer is formed, remove first dummy grid and opened with forming first grid
Mouthful, the second dummy grid of removal removes the 3rd dummy grid to form the 3rd grid to form second grid opening
Opening；Inner wall surface in the first grid opening forms the first gate dielectric layer, in the first gate dielectric layer
Surface forms the first grid of the full first grid opening of filling；In the inwall of the second grid opening
Surface forms the second gate dielectric layer, and the full second grid opening of filling is formed in second gate dielectric layer surface
Second grid；The 3rd gate dielectric layer is formed in the inner wall surface of the 3rd gate openings, in the 3rd grid
Dielectric layer surface forms the 3rd grid of full 3rd gate openings of filling.
The forming step of the first sub- dielectric layer includes：Formed in the substrate and dummy gate structure surface
First sub- deielectric-coating；The described first sub- deielectric-coating is planarized until exposing first grid structure 212, second
Untill the top surface of the grid structure 232 of grid structure 222 and the 3rd, the first sub- dielectric layer is formed.
The formation process of the second sub- dielectric layer is chemical vapor deposition method, physical gas-phase deposition
Or atom layer deposition process.
Refer to Figure 12 and Figure 13, Figure 12 is cross-sectional views of the Figure 13 along BB ' directions, is being situated between
The first conductive structure 214, the second conductive structure 224 and the 3rd conductive structure 234 are formed in matter layer 202,
First conductive structure 214 is located at first grid top, and second conductive structure 224 is located at
Source region top, the 3rd conductive structure 234 is located at drain region top.
It should be noted that Figure 13 is the overlooking the structure diagram for ignoring dielectric layer 202, and first grid
Structure 212 illustrate only first grid, and second grid structure 222 illustrate only second grid, the 3rd grid
Pole structure 232 illustrate only the 3rd grid.
The formation step of first conductive structure 214, the second conductive structure 224 and the 3rd conductive structure 234
Suddenly include：Form first through hole, second groove and the 3rd groove in the dielectric layer 202, described the
One through hole exposes the first grid top in first grid structure, the second groove and second grid knot
Structure is parallel, and the second groove exposes the surface of source region epitaxial layer 223, the 3rd groove and the 3rd
Grid structure is parallel, and the 3rd groove exposes 233 surface of drain extensions layer；It is logical described first
Full conductive material is filled in hole, to form the first conductive structure 214；Filled in the second groove and completely led
Electric material, to form the second conductive structure 224；Full conductive material is filled in the 3rd groove, with shape
Into the 3rd conductive structure 234.
The formation process of the first through hole, second groove and the 3rd groove is carved including anisotropic dry method
Etching technique.The conductive material includes copper, tungsten or aluminium.
In the present embodiment, first conductive structure 214 is grounded, and second conductive structure 224 connects
Ground, the 3rd conductive structure 234 is connected with electrostatic potential end.Therefore, the first grid and source region
Epitaxial layer 223 is grounded, and the drain extensions layer 233 is connected with electrostatic potential end, i.e., described source region ground connection,
The drain region is connected with electrostatic potential end.
In the present embodiment, it is additionally included in second grid and the 3rd top portions of gates forms the 4th conductive knot respectively
Structure, the second grid is connected by the 4th conductive structure with electrostatic potential end；3rd grid passes through
4th conductive structure is connected with electrostatic potential end.
In the present embodiment, divide near the both sides of the 3rd grid structure 232 of first grid structure 212
Ju You not lightly doped district 213 and drain extensions layer 233, the 3rd grid structure 232, lightly doped district 213
Transistor arrangement is constituted with drain extensions layer 233.When 3rd grid accesses electrostatic potential, described
Channel region is opened in 3rd fin 231 of the bottom of the 3rd grid structure 232, and electrostatic potential drives electrostatic electricity
Lotus flows into lightly doped district 213 from drain region epitaxial layer 233.
The electrostatic charge accumulation, institute in the lightly doped district 213 of the side of first grid structure 212
The potential stated in lightly doped district 213 is raised, until the first well region of the bottom of first grid structure 213 with it is light
PN junction conducting between doped region 213, the electrostatic charge is driven by conducting electric current, flows into source region extension
In layer 223.The electrostatic charge is obtained from source region epitaxial layer 223 by second conductive structure 224
Release.
And in second area 220, in the second grid structure 222 near first grid structure 212
Both sides have source region epitaxial layer 223 respectively.When second grid accesses electrostatic potential, in the second grid
Channel region is opened in second fin 221 of the bottom of structure 222, and electrostatic potential drives electrostatic charge from first
Source region epitaxial layer 223 between grid structure 212 and second grid structure 222, flow into adjacent second grid
In source region epitaxial layer 223 between structure 222, and further must by second conductive structure 224
To release.
Accordingly, the embodiment of the present invention also provides the electrostatic discharge (ESD) protection that a kind of use above method is formed
Structure, please continue to refer to Figure 12 and Figure 13, including：Substrate 200, the substrate have first area 210,
The region 230 of second area 220 and the 3rd, the both sides of the first area 210 respectively with second area 220 and
3rd region 230 is adjacent；Positioned at some arranged in parallel first on the surface of 200 first area of substrate 210
Fin 211, first fin 211 has the first end that extends to second area 220 and extends to the
Second end in three regions 230；It is described positioned at second fin 221 on the surface of 200 second area of substrate 220
Second fin 221 is connected with the first end of some first fins 211；Positioned at the region 230 of substrate 200 the 3rd
3rd fin 231 on surface, the 3rd fin 231 is connected with the second end of some first fins 211；
Positioned at the separation layer 201 on the surface of the substrate 200, the separation layer 201 cover first fin 211,
The partial sidewall of the second fin 221 and the 3rd fin 231, and the surface of the separation layer 201 is less than described
The top surface of the first fin 211, the second fin 221 and the 3rd fin 231；Across some first fins
211 first grid structure 212, the first grid structure 212 is located at the side of the first fin of part 211
Wall and top surface；Source region in the second fin 221 and the first fin of part 211；Positioned at the 3rd
Drain region in fin 231.
Illustrated below with reference to accompanying drawing.
In the present embodiment, the substrate 200, the first fin 211, the second fin 221 and the 3rd fin
There is well region in 231；There is N-type ion in the well region.In the source region and drain region have p-type from
Son.In other embodiments, there is p-type ion in the well region.There is N in the source region and drain region
Type ion.The source region top has the second conductive structure 224；Second conductive structure 224 is grounded.
The drain region top has the 3rd conductive structure 234；3rd conductive structure 234 connects with electrostatic potential end
Connect.
In the present embodiment, also include：Some second grid structures 222 in second area 220,
The second grid structure 222 is located at least in the top surface of the second fin 221, some second grid structures
222 is arranged in parallel, and the second grid structure 222 is parallel to first grid structure 212.Described second
Grid structure 222 includes second grid；The second grid is connected with electrostatic potential end.
The source region includes：Between adjacent second grid structure 222 and first grid structure 212
With the source region epitaxial layer 223 between second grid structure 222, the source region epitaxial layer 223 is located at described the
The top of one fin 211 and the second fin 221.Wherein, the material of the source region epitaxial layer 223 is silicon
Or SiGe；Doped with p-type ion in the source region epitaxial layer 223.
In the present embodiment, also include：Some 3rd grid structures 232 in the 3rd region 230,
3rd grid structure 232 is located at least in the top surface of the 3rd fin 231, some 3rd grid structures
232 is arranged in parallel, and the 3rd grid structure 232 is parallel to first grid structure 212.Described 3rd
Grid structure 232 includes the 3rd grid；3rd grid is connected with electrostatic potential end.
The drain region includes：Drain extensions layer 233 between adjacent 3rd grid structure 232, it is described
Drain extensions layer 233 is located at the top of the 3rd fin 231.The material of the drain extensions layer 233
It is silicon or SiGe；Doped with p-type ion in the drain extensions layer 233.
In the present embodiment, also include：In the first fin 211 of the both sides of first grid structure 212
Lightly doped district 213；Wherein, the lightly doped district 213 of side is located at the grid of first grid structure 212 and the 3rd
Between pole structure 232.The first grid structure 212 includes first grid.The first grid top
With the first conductive structure 214；First conductive structure 214 is grounded.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (19)
1. a kind of ESD-protection structure, it is characterised in that including：
Substrate, the substrate has first area, second area and the 3rd region, the first area two
Side is adjacent with second area and the 3rd region respectively；
Positioned at first fin some arranged in parallel on substrate first area surface, first fin has
The first end for extending to second area and the second end for extending to the 3rd region；
Positioned at second fin on substrate second area surface, second fin and the of some first fins
One end connects；
Positioned at the 3rd fin of the region surface of substrate the 3rd, the 3rd fin and the of some first fins
Two ends connect；
Positioned at the separation layer of the substrate surface, the separation layer covers first fin, the second fin
With the partial sidewall of the 3rd fin, and the insulation surface less than first fin, the second fin and
The top surface of the 3rd fin；
Across the first grid structure of some first fins, the first grid structure is located at the fin of part first
The side wall and top surface in portion；
Source region in the second fin and the fin of part first；
Drain region in the 3rd fin.
2. ESD-protection structure as claimed in claim 1, it is characterised in that the substrate, the first fin
Having in portion, the second fin and the 3rd fin has N-type ion in well region, the well region.
3. ESD-protection structure as claimed in claim 2, it is characterised in that in the source region and drain region
With p-type ion.
4. ESD-protection structure as claimed in claim 1, it is characterised in that also include：Positioned at second
Some second grid structures in region, the second grid structure is located at least in the second fin top table
Face, some second grid parallelism structural arrangements, and the second grid parallelism structural is in first grid knot
Structure.
5. ESD-protection structure as claimed in claim 4, it is characterised in that the source region includes：Position
Source region between adjacent second grid structure and between first grid structure and second grid structure
Epitaxial layer, the source region epitaxial layer is located at the top of first fin and the second fin.
6. ESD-protection structure as claimed in claim 5, it is characterised in that the source region epitaxial layer
Material is silicon or SiGe；Doped with p-type ion in the source region epitaxial layer.
7. ESD-protection structure as claimed in claim 4, it is characterised in that the second grid structure
Including second grid；The second grid is connected with electrostatic potential end.
8. ESD-protection structure as claimed in claim 1, it is characterised in that in the 3rd region
Some 3rd grid structures, the 3rd grid structure is located at least in the 3rd fin top surface, some
3rd grid structure is arranged in parallel, and the 3rd grid structure is parallel to first grid structure.
9. ESD-protection structure as claimed in claim 8, it is characterised in that the drain region includes：Position
Drain extensions layer between adjacent 3rd grid structure, the drain extensions layer is located at the 3rd fin
The top in portion.
10. ESD-protection structure as claimed in claim 9, it is characterised in that the drain extensions layer
Material is silicon or SiGe；Doped with p-type ion in the source region epitaxial layer.
11. ESD-protection structures as claimed in claim 8, it is characterised in that the 3rd grid structure
Including the 3rd grid；3rd grid is connected with electrostatic potential end.
12. ESD-protection structures as claimed in claim 1, it is characterised in that also include：Positioned at first
Lightly doped district in first fin of grid structure both sides；Wherein, the lightly doped district of side is located at first
Between grid structure and the 3rd grid structure.
13. ESD-protection structures as claimed in claim 1, it is characterised in that the first grid structure
Including first grid.
14. ESD-protection structures as claimed in claim 13, it is characterised in that also include：Positioned at described
The first conductive structure at the top of first grid；The first conductive structure ground connection.
15. ESD-protection structures as claimed in claim 1, it is characterised in that also include：Positioned at source region
Second conductive structure at top；The second conductive structure ground connection.
16. ESD-protection structures as claimed in claim 1, it is characterised in that also include：Positioned at drain region
3rd conductive structure at top；3rd conductive structure is connected with electrostatic potential end.
A kind of forming method of 17. ESD-protection structures as described in any one of claim 1 to 16, it is special
Levy and be, including：
Substrate is provided, the substrate has first area, second area and the 3rd region, firstth area
Domain both sides are adjacent with second area and the 3rd region respectively, and substrate first area surface has some flat
First fin of row arrangement, first fin is with the first end for extending to second area and extends to
Second end in the 3rd region, the substrate second area surface have the second fin, second fin with
The first end connection of some first fins, the 3rd fin of the region surface of the substrate the 3rd, the described 3rd
Fin is connected with the second end of some first fins；
Separation layer is formed in the substrate surface, the separation layer covers first fin, the second fin
With the partial sidewall of the 3rd fin, and the insulation surface less than first fin, the second fin and
The top surface of the 3rd fin；
It is developed across the first grid structure of some first fins, the first grid structure is located at part the
The side wall and top surface of one fin；
Form the source region in the second fin and the fin of part first and the leakage in the 3rd fin
Area.
The forming method of 18. ESD-protection structures as claimed in claim 17, it is characterised in that formed
While first grid structure, some second grid structures are formed in second area, in the 3rd region
It is interior to form some 3rd grid structures；The second grid structure is located at least in the second fin top surface,
Some second grid parallelism structural arrangements, and the second grid parallelism structural is in first grid structure；
3rd grid structure is located at least in the 3rd fin top surface, some 3rd grid structure parallels
Row, and the 3rd grid structure is parallel to first grid structure.
The forming method of 19. ESD-protection structures as claimed in claim 17, it is characterised in that the source
The forming step in area and drain region includes：The first opening and the second opening are formed, first opening is located at
The first fin between adjacent second grid structure and between first grid structure and second grid structure
In portion and the second fin, second opening is in the 3rd fin between adjacent 3rd grid structure；
Source region epitaxial layer is formed in the described first opening using epitaxy technique, is formed in the described second opening
Drain extensions layer；The doped p-type ion in the source region epitaxial layer and drain extensions layer.
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| CN107799514A (en) * | 2016-08-29 | 2018-03-13 | 中芯国际集成电路制造(上海)有限公司 | ESD-protection structure and forming method thereof |
| CN111430460A (en) * | 2019-01-10 | 2020-07-17 | 中芯国际集成电路制造(上海)有限公司 | Lateral diffusion metal oxide semiconductor device and forming method thereof |
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| US20140097465A1 (en) * | 2012-10-08 | 2014-04-10 | Mayank Shrivastava | Silicon controlled rectifier (scr) device for bulk finfet technology |
| CN103811484A (en) * | 2012-11-15 | 2014-05-21 | 台湾积体电路制造股份有限公司 | ESD Devices Comprising Semiconductor Fins |
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| CN107799514A (en) * | 2016-08-29 | 2018-03-13 | 中芯国际集成电路制造(上海)有限公司 | ESD-protection structure and forming method thereof |
| CN107799514B (en) * | 2016-08-29 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure and forming method thereof |
| CN111430460A (en) * | 2019-01-10 | 2020-07-17 | 中芯国际集成电路制造(上海)有限公司 | Lateral diffusion metal oxide semiconductor device and forming method thereof |
| CN111430460B (en) * | 2019-01-10 | 2023-09-19 | 中芯国际集成电路制造(上海)有限公司 | Laterally diffused metal oxide semiconductor device and method of forming the same |
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