CN106920788B - ESD-protection structure and forming method thereof - Google Patents
ESD-protection structure and forming method thereof Download PDFInfo
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- CN106920788B CN106920788B CN201510995357.2A CN201510995357A CN106920788B CN 106920788 B CN106920788 B CN 106920788B CN 201510995357 A CN201510995357 A CN 201510995357A CN 106920788 B CN106920788 B CN 106920788B
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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Abstract
A kind of ESD-protection structure and forming method thereof, ESD-protection structure includes: the substrate with first area, second area and third region, and first area two sides are adjacent with second area and third region respectively；Several first fins arranged in parallel positioned at substrate first area surface, the first fin, which has, to be extended to the first end of second area and extends to the second end in third region；The second fin positioned at substrate second area surface, the second fin are connect with the first end of several first fins；Positioned at the third fin of substrate third region surface, third fin is connect with the second end of several first fins；Across the first grid structure of several first fins, first grid structure is located at the side wall and top surface of the first fin of part；Source region in the first fin of the second fin and part；Drain region in third fin.The performance improvement of ESD-protection structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of ESD-protection structure and its formation sides
Method.
Background technique
As semiconductor chip is with more and more extensive, cause the semiconductor chip also more next by the factor of electrostatic damage
It is more.Existing chip design in, frequently with static discharge (ESD, Electrostatic Discharge) protect circuit with
Reduce chip damage.The design and application of existing ESD protection circuit include: grid ground connection field effect transistor (Gate
Grounded NMOS, GGNMOS) protection circuit, silicon-controlled (Silicon Controlled Rectifier, SCR) protection electricity
Road, horizontal proliferation field effect transistor (Laterally Diffused MOS, LDMOS) protection circuit etc..
Fig. 1 is the schematic diagram of the section structure of the field effect transistor protection of pipe structure of existing grid ground connection, comprising: substrate 10；
N-type well region 11 in substrate 10；Gate structure 12 positioned at 11 surface of N-type well region；N-type positioned at 12 two sides of gate structure
The source electrode 13 of p-type in well region 11 and the drain electrode 14 of p-type.The p-type source electrode 13, P type trap zone 11 and N-type drain 14 constitute one and post
Raw PNP triode；Wherein, the source electrode 13 is the emitter of parasitic triode, and the drain electrode 14 is the current collection of parasitic triode
Pole, the well region 11 are the base area of parasitic triode；The grounded-grid of the source electrode 13, well region 11 and gate structure 12, it is external
The electrostatic potential input drain electrode 14 of circuit, the external circuit is electrically connected with chip internal circuits, for electricity inside driving chip
Road work.
With the development of semiconductor technology, so that the size of semiconductor devices constantly reduces, device density is continuously improved, existing
Some ESD protection circuit structures have been unable to satisfy technical need, need to introduce fin in ESD protection circuit structure
Formula field effect transistor.
However, the size with semiconductor devices further decreases, even if using fin in ESD protection circuit
Field effect transistor, performance are still unstable.
Summary of the invention
Problems solved by the invention is to provide a kind of ESD-protection structure and forming method thereof, and the static discharge is protected
The performance improvement of protection structure.
To solve the above problems, the present invention provides a kind of ESD-protection structure, comprising: substrate, the substrate have
First area, second area and third region, the first area two sides are adjacent with second area and third region respectively；It is located at
Several first fins arranged in parallel on substrate first area surface, first fin, which has, extends to the first of second area
Hold and extend to the second end in third region；The second fin positioned at substrate second area surface, if second fin with
The first end connection of dry first fin；Positioned at the third fin of substrate third region surface, the third fin and several first
The second end of fin connects；Positioned at the separation layer of the substrate surface, the separation layer covers first fin, the second fin
With the partial sidewall of third fin, and the insulation surface lower than first fin, the second fin and third fin top
Portion surface；Across the first grid structure of several first fins, the first grid structure is located at the side wall of the first fin of part
And top surface；Source region in the first fin of the second fin and part；Drain region in third fin.
Optionally, there is well region in the substrate, the first fin, the second fin and third fin, there is N in the well region
Type ion.
Optionally, there is P-type ion in the source region and drain region.
Optionally, further includes: several second grid structures in second area, the second grid structure at least position
In the second fin top surface, several second grid parallelism structural arrangements, and the second grid parallelism structural is in first grid
Structure.
Optionally, the source region includes: between adjacent second grid structure and first grid structure and second gate
Source region epitaxial layer between the structure of pole, the source region epitaxial layer are located at the top of first fin and the second fin.
Optionally, the material of the source region epitaxial layer is silicon or SiGe；Doped with P-type ion in the source region epitaxial layer.
Optionally, the second grid structure includes second grid；The second grid is connect with electrostatic potential end.
Optionally, several third gate structures in third region, the third gate structure are located at least in third
Fin top surface, several third gate structures are arranged in parallel, and the third gate structure is parallel to first grid structure.
Optionally, the drain region includes: the drain extensions layer between adjacent third gate structure, the drain extensions
Layer is located at the top of the third fin.
Optionally, the material of the drain extensions layer is silicon or SiGe；Doped with P-type ion in the source region epitaxial layer.
Optionally, the third gate structure includes third grid；The third grid is connect with electrostatic potential end.
Optionally, further includes: the lightly doped district in the first fin of first grid structure two sides；Wherein, side
Lightly doped district is between first grid structure and third gate structure.
Optionally, the first grid structure includes first grid.
Optionally, further includes: the first conductive structure at the top of the first grid；First conductive structure connects
Ground.
Optionally, further includes: the second conductive structure at the top of source region；The second conductive structure ground connection.
Optionally, further includes: the third conductive structure at the top of drain region；The third conductive structure and electrostatic potential end
Connection.
Correspondingly, the present invention also provides a kind of forming method of ESD-protection structure described in any of the above embodiments, packet
It includes: substrate is provided, the substrate has first area, second area and a third region, and the first area two sides are respectively with the
Two regions and third region are adjacent, substrate first area surface have several first fins arranged in parallel, described first
Fin, which has, to be extended to the first end of second area and extends to the second end in third region, substrate second area surface
With the second fin, second fin is connect with the first end of several first fins, and the of the substrate third region surface
Three fins, the third fin are connect with the second end of several first fins；The substrate surface formed separation layer, it is described every
Absciss layer covers the partial sidewall of first fin, the second fin and third fin, and the insulation surface is lower than described the
The top surface of one fin, the second fin and third fin；It is developed across the first grid structure of several first fins, described
One gate structure is located at the side wall and top surface of the first fin of part；It is formed and is located in the first fin of the second fin and part
Source region and the drain region in third fin.
Optionally, while forming first grid structure, several second grid structures are formed in second area,
Several third gate structures are formed in three regions；The second grid structure is located at least in the second fin top surface, Ruo Gan
Two gate structures are arranged in parallel, and the second grid parallelism structural is in first grid structure；The third gate structure is at least
Positioned at third fin top surface, several third gate structures are arranged in parallel, and the third gate structure is parallel to the first grid
Pole structure.
Optionally, the forming step for stating source region and drain region includes: to form the first opening and the second opening, first opening
The first fin and the second fin between adjacent second grid structure and between first grid structure and second grid structure
In portion, second opening is in the third fin between adjacent third gate structure；Using epitaxy technique described first
Source region epitaxial layer is formed in opening, forms drain extensions layer in second opening；Outside the source region epitaxial layer and drain region
Prolong doped p-type ion in layer.
Compared with prior art, technical solution of the present invention has the advantage that
In structure of the invention, the source region is located in the second fin, and drain region is located in third fin, and electrostatic charge is defeated
After entering drain region until channel between source region and drain region opens, electrostatic charge can by potential difference driving to each first
Fin conveying, until source region exports.Since the first end of the second fin and several first fins that are located at substrate second area connects
It connects, the third fin positioned at substrate third region is connect with the second end of several first fins, therefore the first of each first fin
Voltage between end and second end is uniform, and can guarantee that the channel in the first fin can be opened simultaneously, so as to guarantee
Electric current in each first fin is uniform, and is conducive to increase the electric current of source region output.Further, since the drain region is located at third
In fin, then there is certain distance between the drain region and first grid structure, be conducive to avoid gate structure internal cause drain region
Potential is excessively high and punctures, so as to avoid ESD-protection structure from failing.
In method of the invention, source region is formed in second fin, forms drain region, electrostatic charge in third fin
Inputted from drain region, until channel between source region and drain region is opened, the electrostatic charge can by potential difference driving to each
A first fin conveying, until source region exports.Since second fin is connect with the first end of several first fins, described
Three fins are connect with the second end of several first fins, therefore the voltage between the first end and second end of each first fin is equal
One, and can guarantee that the channel in the first fin can be opened simultaneously, so as to guarantee that the electric current in each first fin is uniform,
Be conducive to increase the electric current of source region output.Further, since the drain region is located in third fin, then the drain region and first grid
There is certain distance between structure, be conducive to avoid puncturing in gate structure because the potential in drain region is excessively high, so as to
ESD-protection structure is avoided to fail.
Detailed description of the invention
Fig. 1 is the schematic diagram of the section structure of the field effect transistor protection of pipe structure of existing grid ground connection；
Fig. 2 and Fig. 3 is a kind of the schematic diagram of the section structure of ESD protection circuit structure；
Fig. 4 to Figure 13 is the schematic diagram of the section structure of the forming process of the ESD-protection structure of the embodiment of the present invention.
Specific embodiment
As stated in the background art, as the size of semiconductor devices further decreases, even if in ESD protection circuit
Fin formula field effect transistor is used in circuit, performance is still unstable.
Fig. 2 and Fig. 3 are please referred to, Fig. 2 and Fig. 3 are a kind of the schematic diagram of the section structure of ESD protection circuit structure, Fig. 2
It is the schematic diagram of the section structure of the Fig. 3 along the direction AA '.The ESD protection circuit structure includes: substrate 100, the substrate
100 surfaces have several fins 101 arranged in parallel, and 100 surface of substrate has separation layer 102, and the separation layer 102 covers
The partial sidewall surface of the fin 101 is covered, there is well region 103 in the fin 101 and section substrate 100；Across several fins
The gate structure 106 of 101 side wall of portion and top surface；Epitaxial layer positioned at 101 top of fin of 106 two sides of gate structure
104, the epitaxial layer 104 is interior doped with N-type ion or P-type ion；Positioned at separation layer 102, fin 101 and gate structure 106
The dielectric layer 108 on surface.It should be noted that Fig. 3 is the overlooking structure diagram for ignoring dielectric layer 108.
The ESD protection circuit structure is based on the formation of fin 101.Wherein, 106 two sides of gate structure are located at
Epitaxial layer 104 formed source region 107a and drain region 107b, and epitaxial layer 104 in adulterate ion and well region 103 in adulterate from
Sub- transoid.The gate structure 106 and source region 107a and drain region 107b constitutes NMOS transistor or PMOS transistor, and described quiet
Discharge of electricity protection circuit is made of the field effect transistor that grid are grounded.The electrostatic potential access drain region 107b, and well region 103,
Source region 107a and gate structure 106 are grounded.
However, the width dimensions of the fin 101 reduce as dimensions of semiconductor devices reduces, device density improves.And
The source region 107a and drain region 107b is in contact in the fin 101 with the well region 103, therefore, the width of the fin 101
Degree size determines the contact area of the source region 107a and drain region 107b Yu the well region 103.Due to the width of the fin 101
It is smaller to spend size, causes the source region 107a and drain region 107b and the contact area of the well region 103 smaller, then hitting in PN junction
Wear that electric current is smaller, and the charge buildup in the drain region 107b is serious.Therefore, the ESD protection circuit structure is not only quiet
Discharge of electricity ability is weaker, is also easy to be produced from fever phenomenon in the fin 101 where the drain region 107b, the electrostatic is caused to be put
The work efficiency drop of electric protection circuit structure, and service life declines.
Moreover, because the gate structure 106 is across several fins 101, and electrostatic potential is connect simultaneously by conductive structure
Enter several drain region 107b, until electrostatic charge is discharged by conductive structure from source region 107a.Since electrostatic charge enters each drain region
It is had differences when 107b, the breakdown voltage of the field effect transistor of each grid ground connection formed based on each fin 101 is easy to cause to deposit
In difference, cause the stability of ESD protection circuit structure poor.
To solve the above-mentioned problems, the present invention provides a kind of ESD-protection structure, comprising: substrate, the substrate tool
There are first area, second area and third region, the first area two sides are adjacent with second area and third region respectively；Position
Several first fins arranged in parallel in substrate first area surface, first fin have extend to second area the
One end and the second end for extending to third region；The second fin positioned at substrate second area surface, second fin with
The first end of several first fins connects；Positioned at the third fin of substrate third region surface, the third fin and several the
The second end of one fin connects；Positioned at the separation layer of the substrate surface, the separation layer covers first fin, the second fin
The partial sidewall in portion and third fin, and the insulation surface is lower than first fin, the second fin and third fin
Top surface；Across the first grid structure of several first fins, the first grid structure is located at the side of the first fin of part
Wall and top surface；Source region in the first fin of the second fin and part；Drain region in third fin.
Wherein, the source region is located in the second fin, and drain region is located in third fin, and electrostatic charge input drain region until
After channel between source region and drain region is opened, electrostatic charge can by electrostatic potential driving it is defeated to each first fin
It send, until source region exports.The second fin due to being located at substrate second area is connect with the first end of several first fins, is located at
The third fin in substrate third region is connect with the second end of several first fins, therefore the first end and second of each first fin
Voltage between end is uniform, and can guarantee that the channel in the first fin can be opened simultaneously, so as to guarantee each first fin
Electric current in portion is uniform, and is conducive to increase the electric current of source region output.Further, since the drain region is located in third fin,
Then there is between the drain region and first grid structure certain distance, be conducive to avoid the potential in gate structure internal cause drain region excessively high
And puncture, so as to avoid ESD-protection structure from failing.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 13 is the structural schematic diagram of the forming process of the ESD-protection structure of the embodiment of the present invention.
Fig. 4 and Fig. 5 are please referred to, Fig. 4 is the schematic diagram of the section structure of the Fig. 5 along the direction BB ', provides substrate 200, the substrate
200 have first area 210, second area 220 and third region 230,210 two sides of first area respectively with second area
220 and third region 230 it is adjacent, 200 first area of substrate, 210 surface have several first fins 211 arranged in parallel,
First fin 211, which has, to be extended to the first end of second area 220 and extends to the second end in third region 230, institute
220 surface of substrate second area is stated with the second fin 221, the first end of second fin 221 and several first fins 211
Connection, the third fin 231 on 230 surface of substrate third region, the third fin 231 and several first fins 211
Second end connection.
In the present embodiment, ESD-protection structure is formed by be made of grid ground connection field effect transistor.Moreover, institute
Stating grid ground connection field effect transistor is fin formula field effect transistor.
In the present embodiment, the first area 210 is used to form the grid of field effect transistor, the second area
220 are used to form the source electrode of field effect transistor, and the third region 230 is used to form the drain electrode of field effect transistor.Wherein,
The source electrode and grounded-grid, the drain electrode are connect with electrostatic potential.It is quiet when being formed by ESD-protection structure work
Charge is inputted from the drain electrode, until the channel of grid ground connection field effect transistor is opened, flows into electrostatic charge from channel region
Source electrode simultaneously discharges.To achieve the purpose that avoid electrostatic charge to cause damage to the device in the other regions of substrate 200.
In the present embodiment, the grid ground connection field effect transistor is p type field effect transistor.In other embodiments,
The grid ground connection field effect transistor is n type field effect transistor.
The quantity of first fin 211 of the first area 210 is greater than 1, and several first fins 211 are arranged in parallel；
The width at first fin, 211 top is less than 20 nanometers, such as 14 nanometers；The distance between adjacent first fin 211 is 50
Nanometer~60 nanometers.In the second area 220, the quantity of second fin 221 is at least 1, and each second fin
Portion 221 is connect with the first end of at least two the first fins 211.In the third region 230, the third fin 231
Quantity is at least 1, and each third fin 231 is connect with the second end of at least two the first fins 211.
Since the first area 210 is used to form the grid of field effect transistor, energy in first fin 211
Enough form the channel region of field effect transistor.The third fin 231 is used to form the drain electrode of field effect transistor, the second fin
221 are used to form the source electrode of field effect transistor, due to several first fins 211 both ends respectively with same second fin 221
It is connected with same third fin 231, therefore, after electrostatic charge, which inputs, to drain, electrostatic charge accumulates in third fin 231
It is interior.After the channel region in the first fin 211 is opened, since the potential difference at each first fin, 211 both ends is identical, quiet
Charge can uniformly input each first fin 211, and come together in the second fin 221 further to export.
Time and the quantity variance of each first fin 211 are inputted due to avoiding electrostatic charge, it is each so as to guarantee
The voltage at 211 both ends of the first fin of item is uniform, and the current balance in the first fin of each item 211.Moreover, in the second fin 221
Electric current between third fin 231 increases, so as to improve the efficiency of discharge electrostatic charges.
In the present embodiment, the formation step of the substrate 200, the first fin 211, the second fin 221 and third fin 231
It suddenly include: offer semiconductor base；Patterned layer is formed in the semiconductor substrate surface, the patterned layer covering needs shape
At the first fin 211, the regional location of the second fin 221 and third fin 231；Using the patterned layer as exposure mask, etching half
Conductor substrate forms the substrate 200 and the first fin 211, the second fin 221 and third fin positioned at 200 surface of substrate
Portion 231；After etching the semiconductor base, the patterned layer is removed.
The semiconductor base is monocrystalline substrate, single-crystal germanium substrate, silicon-Germanium substrate or silicon carbide substrates.In the present embodiment
In, the semiconductor base is monocrystalline substrate.The patterned layer includes patterned photoresist layer, the patterned light
There can also be mask layer between photoresist layer and semiconductor base, the material of the mask layer includes silicon nitride.Etch described half
The technique of conductor substrate is anisotropic dry etch process, is formed by the first fin 211, the second fin 221 and third
The side wall of fin 231 is vertical relative to 200 surface of substrate or tilts；When first fin 211, the second fin 221 and third
When the side wall of fin 231 is tilted relative to 200 surface of substrate, first fin 211, the second fin 221 and third fin 231
Top dimension be less than bottom size.
In another embodiment, the forming step packet of first fin 211, the second fin 221 and third fin 231
It includes: fin layer is formed on 200 surface of substrate using epitaxy technique；It etches the fin layer, forms first fin 211, the
Two fins 221 and third fin 231.The substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator lining
Bottom, germanium substrate on insulator, glass substrate or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc.；Institute
The material for stating fin layer is silicon, germanium, silicon carbide or SiGe.
There is well region in the substrate 200, the first fin 211, the second fin 221 and third fin 231.In the present embodiment
In, there is N-type ion in the well region；The N-type ion includes phosphonium ion or arsenic ion.In other embodiments, the trap
There is P-type ion in area.The well region is formed before or after etching semiconductor substrate；The formation process of the well region be from
Sub- injection technology.
Referring to FIG. 6, forming separation layer 201 on 200 surface of substrate, the separation layer 201 covers first fin
Portion 211, the second fin 221 and third fin 231 partial sidewall, and 201 surface of the separation layer be lower than first fin
211, the top surface of the second fin 221 and third fin 231.
It should be noted that Fig. 6 is the schematic diagram of the section structure based on Fig. 4.
The separation layer 201 is for being isolated the first adjacent fin 211, the second fin 221 or third fin 231.It is described
The material of separation layer 201 be silica, silicon nitride, silicon oxynitride, low-K dielectric material (dielectric constant be greater than or equal to 2.5, it is small
In 3.9), one of ultralow K dielectric material (dielectric constant is less than 2.5) or multiple combinations.In the present embodiment, the separation layer
201 material is silica.
The forming step of the separation layer 201 includes: in the substrate 200, the first fin 211, the second fin 221 or the
Three fins, 231 surface forms isolation film；The isolation film is planarized until exposing first fin 211, the second fin 221
Or until the top surface of third fin 231；After planarizing the isolation film, it is etched back to the isolation film, exposes portion
Divide 231 sidewall surfaces of the first fin 211, the second fin 221 or third fin, forms separation layer 201.
The formation process of the isolation film is chemical vapor deposition process or physical gas-phase deposition, such as fluid chemistry
(FCVD, Flowable Chemical Vapor Deposition) technique, the plasma enhanced chemical vapor of being vapor-deposited are heavy
Product technique or high-aspect-ratio chemical vapor deposition process (HARP)；The flatening process is CMP process；It is described
Being etched back to technique is anisotropic dry etch process.
In the present embodiment, the formation process of the isolation film is fluid chemistry gas-phase deposition, using the fluidisation
The isolation film that gas-phase deposition is formed is learned to be easy to be packed into the groove between adjacent fin 201, can make to be formed by every
From film even compact, then it is good to be formed by 201 isolation performance of separation layer.
Fig. 7 and Fig. 8 are please referred to, Fig. 7 is the schematic diagram of the section structure of the Fig. 8 along the direction BB ', is developed across several first fins
211 first grid structure 212, the first grid structure 212 are located at the side wall and top surface of the first fin of part 211.
It should be noted that the first grid structure 212 of Fig. 8 illustrates only first grid, second grid structure 222 is only shown
Second grid is gone out, third gate structure 232 illustrates only third grid.
In the present embodiment, while forming first grid structure 212, several second are formed in second area 220
Gate structure 222 forms several third gate structures 232 in third region 230.The second grid structure 222 at least position
In 221 top surface of the second fin, several second grid structures 222 are arranged in parallel, and the second grid structure 222 is parallel to
First grid structure 212；The third gate structure 232 is located at least in 231 top surface of third fin, several third grid knots
Structure 232 is arranged in parallel, and the third gate structure 232 is parallel to first grid structure 212.
In the present embodiment, the quantity of the second grid structure 222 is 2, the quantity of the third gate structure 232
It is 2.
In the present embodiment, the first grid structure 212 is used to form the grid of grid ground connection field effect transistor.It is described
Second grid structure 222 is subsequently formed for controlling in the size of the source region epitaxial layer of second area 220；The third grid knot
Structure 232 is subsequently formed for controlling in the size of the drain extensions layer in third region 230.In the side for being parallel to 200 surface of substrate
Upwards, the width dimensions of the first grid structure 212 are greater than the second grid structure 222 or third gate structure 232
Width dimensions.
In the present embodiment, the first grid structure 212 includes first grid.The second grid structure 222 includes
Second grid；The second grid with electrostatic potential end for connecting.The third gate structure 232 includes third grid；Institute
Third grid is stated for connecting with electrostatic potential end.
The first grid structure 212 further includes the first gate dielectric layer between first grid and the first fin 211；
Positioned at the first mask layer of the first grid top surface；Positioned at the first of first grid and the first gate dielectric layer sidewall surfaces
Side wall.The second grid structure 222 further includes the second gate dielectric layer between second grid and the second fin 221；Position
In the second mask layer of the second grid top surface；Positioned at second side of second grid and the second gate dielectric layer sidewall surfaces
Wall.The third gate structure 232 further includes the third gate dielectric layer between third grid and third fin 231；It is located at
The third mask layer of the third gate top surface；Positioned at the third side of third grid and third gate dielectric layer sidewall surfaces
Wall.
The material of the first grid, second grid and third grid is polysilicon；First gate dielectric layer, second gate
The material of dielectric layer and third gate dielectric layer is silica；The material of first side wall, the second side wall and third side wall is oxygen
One of SiClx, silicon nitride and silicon oxynitride or multiple combinations.
First mask layer forms the exposure mask of first grid as etching, and second mask layer forms the as etching
The exposure mask of two grids, the third mask layer form the exposure mask of third grid as etching.First mask layer, the second exposure mask
Layer, third mask layer material be one of silica, silicon nitride and silicon oxynitride or multiple combinations.
In another embodiment, the first grid structure 212, second grid structure 222 and third gate structure 232 are
Dummy gate structure.The first grid structure 212 includes the first dummy grid；The second grid structure 222 includes the second pseudo- grid
Pole；The third gate structure 232 includes third dummy grid.First dummy grid, the second dummy grid and third dummy grid
Material is polysilicon.It is subsequent to remove first dummy grid after forming source region and drain region, and with the first gate dielectric layer and the
One grid substitution is removed the second dummy grid, and is substituted with the second gate dielectric layer and second grid, removal third dummy grid, and with
Third gate medium and third grid substitution.
The material of the first grid, second grid and third grid is metal；The metal include copper, tungsten, aluminium, silver,
One of titanium nitride, tantalum nitride, titanium-aluminium alloy are a variety of.First gate dielectric layer, the second gate dielectric layer and third grid are situated between
The material of matter layer is high K dielectric material (dielectric coefficient is greater than 3.9).
Referring to FIG. 9, forming lightly doped district 213 in the first fin 211 of 212 two sides of first grid structure.
In the present embodiment, grid are formed by and are grounded field effect transistor for PMOS transistor, in the lightly doped district 213
Doped with P-type ion.In other embodiments, being formed by grid ground connection field effect transistor is NMOS transistor, described gently to mix
Doped with N-type ion in miscellaneous area 213.
The lightly doped district 213 is formed using ion implantation technology.In the present embodiment, the ion implantation technology is with
One gate structure 212, second grid structure 222 and third gate structure 232 are exposure mask, are formed by the first lightly doped district
Between first grid structure 212 and third gate structure 232, first grid structure 212 and second grid structure 222 it
Between, between adjacent second grid structure 222 and between third gate structure 232.
Referring to FIG. 10, forming the source region positioned at the second fin 221 and in the first fin of part 211 and being located at third
Drain region in fin 231.
In the present embodiment, grid are formed by and are grounded field effect transistor for PMOS transistor, in the source region and drain region
With P-type ion；Moreover, the P-type ion concentration in the source region and drain region is higher than lightly doped district 213.In other embodiments,
Being formed by grid ground connection field effect transistor is NMOS transistor, has N-type ion in the source region and drain region.
In the present embodiment, the source region includes: between adjacent second grid structure 222 and first grid knot
Source region epitaxial layer 223 between structure 212 and second grid structure 222, the source region epitaxial layer 223 are located at first fin
211 and second fin 221 top.The drain region includes: the drain extensions layer between adjacent third gate structure 232
233, the drain extensions layer 233 is located at the top of the third fin 231.
The source region and the forming step in drain region include: to form the first opening and the second opening, and first opening is located at
The first fin 211 between adjacent second grid structure 222 and between first grid structure 212 and second grid structure 222
In the second fin 221, second opening is in the third fin 231 between adjacent third gate structure 232；Using outer
Prolong technique and form source region epitaxial layer 223 in first opening, forms drain extensions layer 233 in second opening；In
Doped p-type ion in the source region epitaxial layer 223 and drain extensions layer 233.
The forming step of the first opening and the second opening includes: in the separation layer 201, the first fin 211, second
The sidewall surfaces of fin 221 and third fin 231 formed barrier layer, the barrier layer expose 221 top surface of the second fin,
231 top surface of third fin and the first fin of part between first grid structure 212 and second grid structure 222
211 top surface of portion；Using the barrier layer as exposure mask, first fin 211, the second fin 221 and third fin are etched
231, form the first opening and the second opening.
The etching technics includes anisotropic dry etch process, is formed by the side of the first opening and the second opening
Wall is perpendicular to the first fin 211, the top surface of the second fin 221 and third fin 231.In other embodiments, described
After anisotropic dry etch process, additionally it is possible to carry out wet-etching technology to the first opening and the second opening；It is described wet
Method etching technics can be isotropic wet-etching technology or anisotropic wet-etching technology.
The material of the source region epitaxial layer 223 is silicon or SiGe；Doped with P-type ion in the source region epitaxial layer 223.In
In the present embodiment, the material of the source region epitaxial layer 223 is SiGe, and formation process is selective epitaxial depositing operation；The choosing
Selecting property epitaxial deposition process includes: that temperature is 500 degrees Celsius~800 degrees Celsius, and air pressure is 1 support~100 supports, and process gas includes
Silicon source gas (SiH4Or SiH2Cl2) and ge source gas (GeH4), the flow of the silicon source gas or ge source gas is 1 standard milli
Liter/min~1000 standard milliliters/minute, the process gas further includes HCl and H2, the flow of the HCl is 1 standard milli
Liter/min~1000 standard milliliters/minute, H2Flow be 0.1 standard liter/min~50 standard liter/mins.In the selection
Property epitaxial deposition process during, can be using doping process doped p-type ion in source region epitaxial layer 223 in situ.
The material of the drain extensions layer 233 is silicon or SiGe；Doped with P-type ion in the drain extensions layer 233.In
In the present embodiment, the material of the source region epitaxial layer 223 is silicon, and formation process is selective epitaxial depositing operation；The selection
Property epitaxial deposition process include: temperature be 500 degrees Celsius~800 degrees Celsius, air pressure be 1 support~100 supports, process gas includes silicon
Source gas (SiH4Or SiH2Cl2), the flow of the silicon source gas is 1 standard milliliters/minute~1000 standard milliliters/minute, institute
Stating process gas further includes HCl and H2, the flow of the HCl is 1 standard milliliters/minute~1000 standard milliliters/minute, H2's
Flow is 0.1 standard liter/min~50 standard liter/mins.It, can be using original in the selective epitaxial deposition process
Position doping process doped p-type ion in source region epitaxial layer 223.
Since 221 surface of the second fin is formed with several second grid structures 222, when using epitaxy technique
Source is formed between adjacent first grid structure 212 and second grid structure 222 and between adjacent second grid structure 222
When area's epitaxial layer 223, the second grid structure 222 is able to suppress the growth of source region epitaxial layer 223, avoids the source region extension
The volume of layer 223 is excessive, thus be conducive to avoid bridging between the source region epitaxial layer 223 at the top of adjacent first fin 211,
And be conducive to reduce the resistance for being formed by source region epitaxial layer 223, to increase the electric current of source region discharge electrostatic charges；This
Outside, additionally it is possible to avoid because of prominent first fin, 211 top surface of the source region epitaxial layer 223 formed close to first grid structure 212
Size it is excessive and excessive parasitic capacitance is generated between first grid structure, be formed by grid ground connection field effect to reduce
The parasitic load of transistor is answered, the working efficiency for being formed by ESD-protection structure is improved.
Since 231 surface of third fin is formed with several third gate structures 232, when using epitaxy technique
When forming drain extensions layer 233 between adjacent third gate structure 232, the third gate structure 232 is able to suppress drain region
The growth of epitaxial layer 233 avoids drain region because of electrostatic charge to be conducive to reduce the resistance for being formed by drain extensions layer 233
It gathers and overheats.Moreover, because the drain extensions layer 233 is only formed in third fin 231, and adjacent first grid structure
There is lightly doped district 213, i.e., between drain extensions layer 233 and first grid structure 212 between 212 and third gate structure 232
It is spaced, is conducive to avoid in drain extensions layer 233 due to build-up of electrostatic charges by lightly doped district 213 and third gate structure 232
The too high voltages of generation puncture the first gate dielectric layer in the first grid structure 212, are grounded field-effect so as to avoid grid
The failure of transistor improves the yield and reliability for being formed by ESD-protection structure.
Please refer to Figure 11, the separation layer 201, the first fin 211, the second fin 221, third fin 231, source region,
Drain region, first grid structure 212, second grid structure 222 and 232 surface of third gate structure form dielectric layer 202.
In the present embodiment, the forming step of the dielectric layer 202 includes: in the substrate and dummy gate structure surface shape
At deielectric-coating；The deielectric-coating is planarized, the dielectric layer 202 is formed.
The formation process of the deielectric-coating is chemical vapor deposition process, physical gas-phase deposition or atomic layer deposition work
Skill；The chemical vapor deposition process can be fluid chemistry gas-phase deposition (FCVD, Flowable Chemical
Vapor Deposition), plasma enhanced chemical vapor deposition technique (PECVD) or high-aspect-ratio chemical vapor deposition work
Skill (HARP).The flatening process is CMP process.
The material of the dielectric layer 202 is silica, silicon nitride, silicon oxynitride, (dielectric coefficient is big to low k dielectric materials
In or be equal to 2.5, less than 3.9, such as porous silica or porous silicon nitride) or ultra-low k dielectric material (dielectric coefficient is less than
2.5, such as porous SiC OH).
In another embodiment, first grid structure 212, second grid structure 222 and third gate structure 232 are pseudo- grid
Pole structure.The dielectric layer 202 includes: the first sub- dielectric layer and the second sub- dielectric layer；The first sub- dielectric layer is located at described
Separation layer 201, the first fin 211, the second fin 221, third fin 231, source region and drain region surface；The second sub- dielectric layer
Positioned at the first sub- dielectric layer, 232 surface of first grid structure 212, second grid structure 222 and third gate structure.Wherein, institute
State surface and the first grid structure 212, second grid structure 222 and the third gate structure 232 of the first sub- dielectric layer
Top surface flushes.
After forming the first sub- dielectric layer, first dummy grid is removed to form first grid opening, removal
Second dummy grid removes third dummy grid to form second grid opening to form third gate openings；In the first grid
The inner wall surface of opening forms the first gate dielectric layer, forms the full first grid opening of filling in first grid dielectric layer surface
First grid；The second gate dielectric layer is formed in the inner wall surface of second grid opening, is formed in second gate dielectric layer surface
The second grid of the full second grid opening of filling；Third gate medium is formed in the inner wall surface of the third gate openings
Layer forms the third grid for filling the full third gate openings on third gate dielectric layer surface.
The forming step of the first sub- dielectric layer includes: to form the first son in the substrate and dummy gate structure surface to be situated between
Plasma membrane；The described first sub- deielectric-coating is planarized until exposing first grid structure 212, second grid structure 222 and third grid
Until the top surface of pole structure 232, the first sub- dielectric layer is formed.
The formation process of the second sub- dielectric layer is chemical vapor deposition process, physical gas-phase deposition or atomic layer
Depositing operation.
Figure 12 and Figure 13 are please referred to, Figure 12 is the schematic diagram of the section structure of the Figure 13 along the direction BB ', the shape in dielectric layer 202
At the first conductive structure 214, the second conductive structure 224 and third conductive structure 234, first conductive structure 214 is located at institute
It states at the top of first grid, second conductive structure 224 is located at the top of source region, and the third conductive structure 234 is located at drain region top
Portion.
It should be noted that Figure 13 is the overlooking structure diagram for ignoring dielectric layer 202, and first grid structure 212 is only
First grid is shown, second grid structure 222 illustrates only second grid, and third gate structure 232 illustrates only third grid
Pole.
The forming step of first conductive structure 214, the second conductive structure 224 and third conductive structure 234 includes: In
First through hole, second groove and third groove, the first through hole, which are formed, in the dielectric layer 202 exposes first grid structure
At the top of interior first grid, the second groove and second grid parallelism structural, and the second groove exposes source region extension
223 surface of layer, the third groove is parallel with third gate structure, and the third groove exposes 233 table of drain extensions layer
Face；Full conductive material is filled, in the first through hole to form the first conductive structure 214；It is filled in the second groove
Full conductive material, to form the second conductive structure 224；Full conductive material is filled in the third groove, is led with forming third
Electric structure 234.
The formation process of the first through hole, second groove and third groove includes anisotropic dry etch process.
The conductive material includes copper, tungsten or aluminium.
In the present embodiment, first conductive structure 214 is grounded, and second conductive structure 224 is grounded, the third
Conductive structure 234 is connect with electrostatic potential end.Therefore, the first grid and source region epitaxial layer 223 are grounded, the drain extensions
Layer 233 is connect with electrostatic potential end, i.e., the described source region ground connection, the drain region is connect with electrostatic potential end.
It in the present embodiment, further include being respectively formed the 4th conductive structure in second grid and third top portions of gates, it is described
Second grid is connect by the 4th conductive structure with electrostatic potential end；The third grid passes through the 4th conductive structure and electrostatic electricity
Press bond.
In the present embodiment, it is respectively provided in 232 two sides of third gate structure near first grid structure 212 and gently mixes
Miscellaneous area 213 and drain extensions floor 233, the third gate structure 232, lightly doped district 213 and drain extensions layer 233 constitute crystal
Pipe structure.When the third grid access electrostatic potential, 231 septal fossula of third fin in 232 bottom of third gate structure
Road Qu Kaiqi, electrostatic potential drive electrostatic charge to flow into lightly doped district 213 from drain region epitaxial layer 233.
The electrostatic charge gathers in the lightly doped district 213 of 212 side of first grid structure, the lightly doped district
Potential in 213 is raised, until the first well region of 213 bottom of first grid structure is connected with the PN junction between lightly doped district 213,
The electrostatic charge is driven by conducting electric current, is flowed into source region epitaxial layer 223.The electrostatic charge is logical from source region epitaxial layer 223
Second conductive structure 224 is crossed to be released.
And in second area 220, have respectively in 222 two sides of second grid structure near first grid structure 212
Active area epitaxial layer 223.The second fin when second grid accesses electrostatic potential, in 222 bottom of second grid structure
221 interior raceway groove areas are opened, and electrostatic potential drives electrostatic charge between first grid structure 212 and second grid structure 222
Source region epitaxial layer 223 flows into the source region epitaxial layer 223 between adjacent second grid structure 222, and further passes through described the
Two conductive structures 224 are released.
Correspondingly, the embodiment of the present invention also provide it is a kind of ESD-protection structure is formed by using the above method, ask
Continue to refer to figure 12 and Figure 13, comprising: substrate 200, the substrate have first area 210, second area 220 and third region
230,210 two sides of first area are adjacent with second area 220 and third region 230 respectively；Positioned at 200 first area of substrate
Several first fins 211 arranged in parallel on 210 surfaces, first fin 211, which has, extends to the first of second area 220
Hold and extend to the second end in third region 230；The second fin 221 positioned at 200 second area of substrate, 220 surface, it is described
Second fin 221 is connect with the first end of several first fins 211；Third fin positioned at 200 third region of substrate, 230 surface
231, the third fin 231 is connect with the second end of several first fins 211；Separation layer positioned at 200 surface of substrate
201, the separation layer 201 covers the partial sidewall of first fin 211, the second fin 221 and third fin 231, and institute
201 surface of separation layer is stated lower than first fin 211, the top surface of the second fin 221 and third fin 231；If across
The first grid structure 212 of dry first fin 211, the first grid structure 212 be located at the side wall of the first fin of part 211 with
Top surface；Source region in the second fin 221 and the first fin of part 211；Drain region in third fin 231.
It is illustrated below with reference to attached drawing.
In the present embodiment, there is trap in the substrate 200, the first fin 211, the second fin 221 and third fin 231
Area；There is N-type ion in the well region.There is P-type ion in the source region and drain region.In other embodiments, the well region
It is interior that there is P-type ion.There is N-type ion in the source region and drain region.There is the second conductive structure 224 at the top of the source region；Institute
State the second conductive structure 224 ground connection.There is third conductive structure 234 at the top of the drain region；The third conductive structure 234 with it is quiet
The connection of piezoelectric voltage end.
In the present embodiment, further includes: several second grid structures 222 in second area 220, the second gate
Pole structure 222 is located at least in 221 top surface of the second fin, and several second grid structures 222 are arranged in parallel, and the second gate
Pole structure 222 is parallel to first grid structure 212.The second grid structure 222 includes second grid；The second grid with
The connection of electrostatic potential end.
The source region includes: between adjacent second grid structure 222 and first grid structure 212 and second gate
Source region epitaxial layer 223 between pole structure 222, the source region epitaxial layer 223 are located at first fin 211 and the second fin
221 top.Wherein, the material of the source region epitaxial layer 223 is silicon or SiGe；Doped with p-type in the source region epitaxial layer 223
Ion.
In the present embodiment, further includes: several third gate structures 232 in third region 230, the third grid
Pole structure 232 is located at least in 231 top surface of third fin, and several third gate structures 232 are arranged in parallel, and the third grid
Pole structure 232 is parallel to first grid structure 212.The third gate structure 232 includes third grid；The third grid with
The connection of electrostatic potential end.
The drain region includes: the drain extensions layer 233 between adjacent third gate structure 232, the drain extensions
Layer 233 is located at the top of the third fin 231.The material of the drain extensions layer 233 is silicon or SiGe；The drain extensions
Doped with P-type ion in layer 233.
In the present embodiment, further includes: the lightly doped district in the first fin 211 of 212 two sides of first grid structure
213；Wherein, the lightly doped district 213 of side is between first grid structure 212 and third gate structure 232.The first grid
Pole structure 212 includes first grid.There is the first conductive structure 214 at the top of the first grid；First conductive structure 214
Ground connection.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of ESD-protection structure characterized by comprising
Substrate, the substrate have first area, second area and third region, the first area two sides respectively with the secondth area
Domain and third region are adjacent；
Several first fins arranged in parallel positioned at substrate first area surface, first fin, which has, extends to the secondth area
The first end in domain and the second end for extending to third region；
The second fin positioned at substrate second area surface, second fin are connect with the first end of several first fins；
Positioned at the third fin of substrate third region surface, the third fin is connect with the second end of several first fins；
Positioned at the separation layer of the substrate surface, the separation layer covers first fin, the second fin and third fin
Partial sidewall, and the insulation surface is lower than first fin, the top surface of the second fin and third fin；
Across the first grid structure of several first fins, the first grid structure is located at side wall and the top of the first fin of part
Portion surface；
Several second grid structures in second area, the second grid structure are located at least in table at the top of the second fin
Face, several second grid parallelism structural arrangements, and the second grid parallelism structural is in first grid structure；
Source region in the first fin of the second fin and part, the source region include: between adjacent second grid structure,
And the source region epitaxial layer between first grid structure and second grid structure, the source region epitaxial layer are located at first fin
With the top of the second fin；
Drain region in third fin.
2. ESD-protection structure as described in claim 1, which is characterized in that the substrate, the first fin, the second fin
With there is well region in third fin, there is in the well region N-type ion.
3. ESD-protection structure as claimed in claim 2, which is characterized in that in the source region and drain region have p-type from
Son.
4. ESD-protection structure as described in claim 1, which is characterized in that the material of the source region epitaxial layer be silicon or
SiGe；Doped with P-type ion in the source region epitaxial layer.
5. ESD-protection structure as described in claim 1, which is characterized in that the second grid structure includes second gate
Pole；The second grid is connect with electrostatic potential end.
6. ESD-protection structure as described in claim 1, which is characterized in that several third grid in third region
Pole structure, the third gate structure are located at least in third fin top surface, and several third gate structures are arranged in parallel, and institute
It states third gate structure and is parallel to first grid structure.
7. ESD-protection structure as claimed in claim 6, which is characterized in that the drain region includes: positioned at adjacent third
Drain extensions layer between gate structure, the drain extensions layer are located at the top of the third fin.
8. ESD-protection structure as claimed in claim 7, which is characterized in that the material of the drain extensions layer be silicon or
SiGe；Doped with P-type ion in the source region epitaxial layer.
9. ESD-protection structure as claimed in claim 6, which is characterized in that the third gate structure includes third grid
Pole；The third grid is connect with electrostatic potential end.
10. ESD-protection structure as described in claim 1, which is characterized in that further include: it is located at first grid structure two
Lightly doped district in first fin of side；Wherein, the lightly doped district of side be located at first grid structure and third gate structure it
Between.
11. ESD-protection structure as described in claim 1, which is characterized in that the first grid structure includes first
Grid.
12. ESD-protection structure as claimed in claim 11, which is characterized in that further include: it is located at the first grid
First conductive structure at top；The first conductive structure ground connection.
13. ESD-protection structure as described in claim 1, which is characterized in that further include: second at the top of source region
Conductive structure；The second conductive structure ground connection.
14. ESD-protection structure as described in claim 1, which is characterized in that further include: the third at the top of drain region
Conductive structure；The third conductive structure is connect with electrostatic potential end.
15. a kind of forming method of such as described in any item ESD-protection structures of claim 1 to 14, which is characterized in that
Include:
There is provided substrate, the substrate has first area, second area and a third region, and the first area two sides are respectively with the
Two regions and third region are adjacent, substrate first area surface have several first fins arranged in parallel, described first
Fin, which has, to be extended to the first end of second area and extends to the second end in third region, substrate second area surface
With the second fin, second fin is connect with the first end of several first fins, and the of the substrate third region surface
Three fins, the third fin are connect with the second end of several first fins；
Separation layer is formed in the substrate surface, the separation layer covers first fin, the second fin and third fin
Partial sidewall, and the insulation surface is lower than first fin, the top surface of the second fin and third fin；
It is developed across the first grid structure of several first fins, the first grid structure is located at the side wall of the first fin of part
And top surface；
Several second grid structures are formed in second area, the second grid structure is located at least in table at the top of the second fin
Face, several second grid parallelism structural arrangements, and the second grid parallelism structural is in first grid structure；
Form the source region being located in the first fin of the second fin and part and the drain region in third fin, the source region
It include: the source region epitaxial layer between adjacent second grid structure and between first grid structure and second grid structure,
The source region epitaxial layer is located at the top of first fin and the second fin.
16. the forming method of ESD-protection structure as claimed in claim 15, which is characterized in that further include: it is being formed
While first grid structure, several third gate structures are formed in third region；The third gate structure is located at least in
Third fin top surface, several third gate structures are arranged in parallel, and the third gate structure is parallel to first grid knot
Structure.
17. the forming method of ESD-protection structure as claimed in claim 15, which is characterized in that the source region and drain region
Forming step include: to form the first opening and the second opening, it is described first opening between adjacent second grid structure, with
And in the first fin and the second fin between first grid structure and second grid structure, second opening is located at adjacent the
In third fin between three gate structures；Source region epitaxial layer is formed in first opening using epitaxy technique, described
Drain extensions layer is formed in second opening；The doped p-type ion in the source region epitaxial layer and drain extensions layer.
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| CN103187412A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor antistatic protection structure |
| CN103811484A (en) * | 2012-11-15 | 2014-05-21 | 台湾积体电路制造股份有限公司 | ESD Devices Comprising Semiconductor Fins |
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| CN103187412A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor antistatic protection structure |
| CN103811484A (en) * | 2012-11-15 | 2014-05-21 | 台湾积体电路制造股份有限公司 | ESD Devices Comprising Semiconductor Fins |
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