CN111415931A - L ED chip structure and manufacturing method thereof - Google Patents
L ED chip structure and manufacturing method thereof Download PDFInfo
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- CN111415931A CN111415931A CN202010249852.XA CN202010249852A CN111415931A CN 111415931 A CN111415931 A CN 111415931A CN 202010249852 A CN202010249852 A CN 202010249852A CN 111415931 A CN111415931 A CN 111415931A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 229910002601 GaN Inorganic materials 0.000 claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000001301 oxygen Substances 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
Abstract
The application provides an L ED chip structure and manufacturing method thereof, L ED chip structure, on horizontal structure L ED chip's basis, add to set up one and occupy the less ESD diode of substrate area, ESD diode and horizontal structure L ED chip are reverse parallel connection to make when applying voltage for L ED chip, no matter apply forward voltage or reverse voltage, can both improve L ED's antistatic effect, especially when applying reverse voltage, more can improve L ED's antistatic effect.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an L ED chip structure and a manufacturing method thereof.
Background
L ED (L light-Emitting Diode) emits light in the form of light by utilizing the difference in energy of electrons moving between n-type semiconductor and p-type semiconductor, and is called as a cold light source because it is different from the light-Emitting principle of incandescent lamp heat.
However, with the development of L ED, L ED has become smaller and smaller, resulting in limited ESD (electrostatic discharge) capability of the L ED chip in a horizontal structure made conventionally.
Disclosure of Invention
In view of this, the present invention provides an L ED chip structure and a method for fabricating the same, so as to solve the problem in the prior art that the L ED chip size is reduced and the antistatic capability is limited.
In order to achieve the purpose, the invention provides the following technical scheme:
an L ED chip structure, comprising:
a substrate comprising a first region and a second region, the first region semi-surrounding the second region, and the second region having an area that is between 5% and 10%, inclusive, of the area of the substrate;
the light emitting diode is positioned in the first area and comprises an N-type electrode and a P-type electrode;
the ESD diode is arranged in the second area and has a gap with the light-emitting diode, and the ESD diode comprises an N-type electrode and a P-type electrode;
wherein the light emitting diode and the ESD diode are formed simultaneously by adopting the same process steps;
the N-type electrode of the light emitting diode is electrically connected with the P-type electrode of the ESD diode;
the P-type electrode of the light emitting diode is electrically connected with the N-type electrode of the ESD diode.
Preferably, the light emitting diode and the ESD diode each include:
a first type semiconductor layer, an active layer, and a second type semiconductor layer formed on the substrate are sequentially grown.
Preferably, the method further comprises the following steps:
and the passivation layer covers the second type semiconductor layer, the side wall of the light emitting diode and the side wall of the ESD diode.
Preferably, the method further comprises the following steps:
the first routing line and the second routing line are positioned on the surface, away from the substrate, of the passivation layer;
the first routing wire electrically connects the N-type electrode of the light emitting diode with the P-type electrode of the ESD diode;
the second routing wire electrically connects the P-type electrode of the light emitting diode with the N-type electrode of the ESD diode.
Preferably, the first wire, the second wire, the N-type electrode and the P-type electrode of the light emitting diode, the N-type electrode and the P-type electrode of the ESD diode are made of the same material and are formed in the same process step.
Preferably, the first type semiconductor layer is an N-type semiconductor layer;
the second type semiconductor layer is a P type semiconductor layer.
Preferably, the first type semiconductor layer is a P type semiconductor layer;
the second type semiconductor layer is an N type semiconductor layer.
Preferably, the P-type semiconductor layer is a P-type gallium nitride layer, and the N-type semiconductor layer is an N-type gallium nitride layer.
The invention also provides a manufacturing method of the L ED chip structure, which is used for manufacturing and forming the L ED chip structure, and the manufacturing method comprises the following steps:
providing a substrate, wherein the substrate comprises a first region and a second region, the first region semi-surrounds the second region, and the area of the second region accounts for 5% -10% of the area of the substrate;
adopting the same process steps to simultaneously form a light emitting diode in the first area and an ESD diode in the second area, wherein the light emitting diode comprises an N-type electrode and a P-type electrode, and the ESD diode comprises an N-type electrode and a P-type electrode;
and electrically connecting the N-type electrode of the light-emitting diode with the P-type electrode of the ESD diode, and electrically connecting the P-type electrode of the light-emitting diode with the N-type electrode of the ESD diode.
Preferably, before forming the N-type electrode and the P-type electrode, the method further includes:
forming a whole passivation layer to cover the light emitting diode and the epitaxial structure of the ESD diode;
and etching the passivation layer to form four openings which respectively correspond to the N-type electrode and the P-type electrode of the light-emitting diode and the N-type electrode and the P-type electrode of the ESD diode.
According to the technical scheme, the L ED chip structure provided by the invention is characterized in that an ESD diode occupying a small substrate area is additionally arranged on the basis of a L ED chip in a horizontal structure, and the ESD diode is connected with the L ED chip in a reverse parallel connection mode, so that when a voltage is applied to the L ED chip, the antistatic capacity of L ED can be improved no matter a forward voltage or a reverse voltage is applied, and particularly when the reverse voltage is applied, the antistatic capacity of L ED can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a diagram of an L ED chip in the prior art;
FIG. 2 is a schematic diagram of PN junction capacitance of an L ED chip structure;
FIG. 3 is a schematic diagram of an equivalent circuit of an L ED chip structure according to an embodiment of the present invention;
fig. 4 is a schematic top view of an L ED chip structure according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of an L ED chip structure according to an embodiment of the present invention;
FIG. 6 is a chart of testing antistatic properties of L ED chip structures provided by embodiments of the present invention and L ED chip structures in the prior art.
Detailed Description
As discussed in the background section, the prior art has limited ESD capability as L ED chips are scaled down.
The inventors found that the reason for the above phenomenon is:
as shown in fig. 1, an L ED chip structure in the prior art includes an insulating substrate 0l, a P-type (or N-type) semiconductor layer 02, an MQW (multiple quantum well) active region 03, an N-type (or P-type) semiconductor layer 04, and a passivation layer 05 covering the semiconductor layer, wherein the P-type (or N-type) semiconductor layer, the MQW (multiple quantum well) active region 03, and the N-type (or P-type) semiconductor layer 04 are sequentially stacked on the insulating substrate 0l, and the passivation layer 05 is provided with a through hole to form an N (or P) -type metal electrode 06 and a P (.
The corresponding manufacturing steps comprise: providing an insulating substrate 0 l; then, a P-type (or N-type) semiconductor layer 02, an MQW (multi-quantum well) active region 03 and an N-type (or P-type) semiconductor layer 04 are sequentially formed through an epitaxial growth process; etching the MQW active region by a dry etching or wet etching process until the P-type (or N-type) semiconductor layer 02 is leaked; then, etching through the peripheral part of the epitaxial structure to the insulating substrate 01 by a dry etching or wet etching process; the whole structure is covered with a passivation layer 05; performing dry etching or wet etching on the passivation layer 05 to form two electrode grooves; an ohmic contact layer (not shown) is formed in the electrode groove, and metal is deposited to form an N-type metal electrode and a P-type metal electrode.
As shown in FIG. 2, a certain charge accumulation occurs at the PN junction (the junction between two semiconductors) due to the applied voltage, i.e., the junction capacitance CjThe effect is also shown as depletion region in figure 2. Corresponding junction capacitance CjThe larger the resistance to static Electricity (ESD), and vice versa, the worse. When a voltage is applied, the width w of the depletion region changes, which causes the charge amount to change, thereby generating an equivalent capacitance effect. It is related to the PN junction area a, the depletion region width w, the semiconductor dielectric constant, and the applied voltage.
Cj＝A/w
The chip size determines A, the larger the size is, the larger the A is, the junction capacitance CjThe larger the resistance to static Electricity (ESD).
When L ED device is forward biased, depletion region width w is relatively small, and junction capacitance C is smalljLarger, stronger anti-static Electricity (ESD) capability, and when L ED device is reversely biased, depletion region widthw increases, junction capacitance decreases, and antistatic (ESD) capability is poor if L ED chip size becomes smaller, junction capacitance C becomes smallerjThe conventional L ED chip has a poor electrostatic discharge (ESD) resistance when reverse-biased because the ESD breakdown is easier and the ESD resistance is a bottleneck.
Based on this, the present invention provides an L ED chip structure, including:
a substrate comprising a first region and a second region, the first region semi-surrounding the second region, and the second region having an area that is between 5% and 10%, inclusive, of the area of the substrate;
the light emitting diode is positioned in the first area and comprises an N-type electrode and a P-type electrode;
the ESD diode is arranged in the second area and has a gap with the light-emitting diode, and the ESD diode comprises an N-type electrode and a P-type electrode;
wherein the light emitting diode and the ESD diode are formed simultaneously by adopting the same process steps;
the N-type electrode of the light emitting diode is electrically connected with the P-type electrode of the ESD diode;
the P-type electrode of the light emitting diode is electrically connected with the N-type electrode of the ESD diode.
According to the L ED chip structure, an ESD diode occupying a small substrate area is additionally arranged on the basis of a L ED chip in a horizontal structure, and the ESD diode is connected with a L ED chip in a reverse parallel connection mode, so that when a voltage is applied to the L ED chip, the antistatic capacity of L ED can be improved no matter a forward voltage or a reverse voltage is applied, and particularly when the reverse voltage is applied, the antistatic capacity of L ED can be improved.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An L ED chip structure provided by an embodiment of the invention is shown in FIGS. 3, 4 and 5, wherein FIG. 3 is an equivalent circuit schematic diagram of a L ED chip structure provided by the embodiment of the invention, FIG. 4 is a schematic diagram of a top view structure of a L ED chip structure provided by the embodiment of the invention, FIG. 5 is a schematic diagram of a cross-sectional structure of a L ED chip structure provided by the embodiment of the invention, the L ED chip comprises a substrate 1, the substrate 1 comprises a first region ll and a second region 12, the first region l1 semi-surrounds the second region 12, the area of the second region 12 accounts for 5% -10% of the area of the substrate 1, a light emitting diode L ED2 located in the first region 11, the light emitting diode L ED2 comprises an N-type electrode A and a P-type electrode B, the ESD diode located in the second region 12 and having a gap with the light emitting diode 2, the ESD diode 3 comprises an N-type electrode D and a P-type electrode C, wherein the light emitting diode 2 and the P-type electrode C are formed simultaneously by the same process steps, and the ESD diode 3 is electrically connected with the ESD electrode of the ESD diode 2 and the ESD diode 3.
Fig. 3 is a schematic diagram showing an equivalent circuit of an L ED chip structure according to an embodiment of the present invention, and the L ED chip structure according to an embodiment of the present invention is an ESD protection diode connected in reverse parallel to a conventional L ED chip.
When a forward voltage is applied to L ED, current only passes through the main light-emitting region due to the unidirectional conductive characteristic of the light-emitting diode, so that normal light is emitted, and when a reverse ESD large current passes through the main light-emitting region, the current can preferentially pass through the independent ESD diode, so that the main light-emitting region is prevented from being damaged, and the antistatic capability of the L ED chip is improved.
In this embodiment, the material of the substrate is not limited, and the optional substrate 1 is an insulating substrate. The material of the substrate can be sapphire or silicon.
In the embodiment of the present invention, the specific structures of the light emitting diode and the ESD diode are not limited, and alternatively, as shown in fig. 5, each of the light emitting diode 2 and the ESD diode 3 includes at least a first-type semiconductor layer 4, an active layer 5, and a second-type semiconductor layer 6 sequentially grown on the substrate 1. The light emitting diode and the ESD diode provided by the embodiment of the invention can also comprise other layer structures, such as a current expansion layer, a current barrier layer and the like, wherein the current expansion layer is used for improving current transmission, and the current expansion layer is manufactured below the electrodes of the light emitting diode and the ESD diode so that current is dispersed out of the electrodes.
In order to prevent the formed L ED chip structure surface from being eroded by other moisture or oxygen, the embodiment of the invention further includes forming a passivation layer 7 on the second type semiconductor layer, the sidewalls of the light emitting diode and the sidewalls of the ESD diode after forming the L ED chip epitaxial layer, and then exposing the positions of the N-type electrode and the P-type electrode of the light emitting diode and the positions of the N-type electrode and the P-type electrode of the ESD diode by forming an opening on the passivation layer.
And subsequently, metal is deposited on the passivation layer 7 to form an N-type electrode and a P-type electrode of the corresponding light emitting diode and an N-type electrode and a P-type electrode of the ESD diode.
In the embodiment of the present invention, the materials of the N-type electrode and the P-type electrode of the light emitting diode and the N-type electrode and the P-type electrode of the ESD diode are not limited, and may be copper or silver.
In the embodiment of the invention, specific materials of the first type semiconductor layer and the second type semiconductor layer are not limited, and the first type semiconductor layer and the second type semiconductor layer are semiconductor layers with opposite doping types, wherein the first type semiconductor layer can be an N type semiconductor layer or a P type semiconductor layer, but when the first type semiconductor layer is an N type semiconductor layer, the second type semiconductor layer is a P type semiconductor layer; when the first type semiconductor layer is a P type semiconductor layer, the second type semiconductor layer is an N type semiconductor layer. Optionally, the N-type semiconductor layer is an N-type gallium nitride layer, and the P-type semiconductor layer is a P-type semiconductor layer.
As shown in fig. 4, in the L ED chip structure provided by the embodiment of the present invention, the area of the first substrate on which the L ED chip is located is larger, and the area of the second substrate on which the ESD diode is located is smaller, so as to avoid that the effective light-emitting area of the light-emitting diode is reduced more due to the additional arrangement of the ESD diode, and the light-emitting efficiency of the light-emitting diode is affected.
Referring to fig. 4, the first region where the L ED chip is located semi-encloses the second region where the ESD diode is located, which is equivalent to that the second region where the ESD diode is located utilizes the position of the region where one electrode of the L ED chip with a horizontal structure is located, and occupies a part of the region, so as to form the ESD diode, thereby avoiding the problem of large occupied area of the ESD diode.
Referring to fig. 4, in the embodiment of the present invention, a specific manner of electrically connecting an N-type electrode of a light emitting diode and a P-type electrode of an ESD diode is not limited, optionally, the L ED chip structure further includes a first trace 8l and a second trace 82 above the passivation layer and away from the substrate surface, the first trace 8l is used to electrically connect an N-type electrode a of the light emitting diode and a P-type electrode C of the ESD diode, and the second trace 82 electrically connects a P-type electrode B of the light emitting diode and an N-type electrode D of the ESD diode.
Experimental examples
Wherein, the diamond line represents the antistatic capability curve of a horizontal L ED chip in the prior art, the pass rate is 63% at 1500V, and the square line represents the L ED chip structure provided in the embodiment of the invention and connected with ESD diodes in parallel in the reverse direction, as can be seen from FIG. 6, the pass rate is about 98% when 2500V is applied, and the pass rate is about 66% when 3000V is applied.
The L ED chip with the ESD protection structure provided by the embodiment of the invention effectively prevents the light emitting diode from being damaged under the condition of electrostatic reverse discharge, has a simple manufacturing process and saves the production cost.
The invention also provides a manufacturing method of the L ED chip structure, which is used for manufacturing and forming the L ED chip with the ESD diode in the embodiment, and the manufacturing method comprises the following steps:
providing a substrate, wherein the substrate comprises a first region and a second region, the first region semi-surrounds the second region, and the area of the second region accounts for 5% -10% of the area of the substrate;
adopting the same process steps to simultaneously form a light emitting diode in the first area and an ESD diode in the second area, wherein the light emitting diode comprises an N-type electrode and a P-type electrode, and the ESD diode comprises an N-type electrode and a P-type electrode;
and electrically connecting the N-type electrode of the light-emitting diode with the P-type electrode of the ESD diode, and electrically connecting the P-type electrode of the light-emitting diode with the N-type electrode of the ESD diode.
Wherein before forming the N-type electrode and the P-type electrode, the method further comprises:
forming a whole passivation layer to cover the light emitting diode and the epitaxial structure of the ESD diode;
and etching the passivation layer to form four openings which respectively correspond to the N-type electrode and the P-type electrode of the light-emitting diode and the N-type electrode and the P-type electrode of the ESD diode.
It should be noted that the L ED chip structure manufacturing method provided by the embodiment of the present invention is compatible with the manufacturing process in the prior art, and only needs to grow the first type semiconductor layer, the active layer and the second type semiconductor layer on the substrate, and then, in the process of forming the electrode trench by etching, the trench provided with two electrodes is added to connect the N-type electrode with the N-type semiconductor layer, and the P-type electrode with the P-type semiconductor layer, then, an opening is formed by etching on the passivation layer, and in the process of forming the N-type electrode and the P-type electrode by depositing metal, the first routing line and the second routing line are formed at the same time to connect the N-type electrode of L ED with the P-type electrode of ESD, and the P-type electrode of L ED is connected with the N-type electrode.
That is, the L ED chip structure manufacturing method provided in the embodiment of the present invention only needs to change the area of etching and depositing metal, which is similar to the manufacturing process in the prior art, thereby achieving the purposes of greatly enhancing the antistatic capability and prolonging the service life of the L ED chip without increasing much cost.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. The term "comprising" is used to specify the presence of stated elements, but not to preclude the presence or addition of one or more other like elements in a claim or a device.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An L ED chip structure, comprising:
a substrate comprising a first region and a second region, the first region semi-surrounding the second region, and the second region having an area that is between 5% and 10%, inclusive, of the area of the substrate;
the light emitting diode is positioned in the first area and comprises an N-type electrode and a P-type electrode;
the ESD diode is arranged in the second area and has a gap with the light-emitting diode, and the ESD diode comprises an N-type electrode and a P-type electrode;
wherein the light emitting diode and the ESD diode are formed simultaneously by adopting the same process steps;
the N-type electrode of the light emitting diode is electrically connected with the P-type electrode of the ESD diode;
the P-type electrode of the light emitting diode is electrically connected with the N-type electrode of the ESD diode.
2. The L ED chip structure of claim 1, wherein the light emitting diode and the ESD diode each include:
a first type semiconductor layer, an active layer, and a second type semiconductor layer formed on the substrate are sequentially grown.
3. The L ED chip structure of claim 2, further comprising:
and the passivation layer covers the second type semiconductor layer, the side wall of the light emitting diode and the side wall of the ESD diode.
4. The L ED chip structure of claim 3, further comprising:
the first routing line and the second routing line are positioned on the surface, away from the substrate, of the passivation layer;
the first routing wire electrically connects the N-type electrode of the light emitting diode with the P-type electrode of the ESD diode;
the second routing wire electrically connects the P-type electrode of the light emitting diode with the N-type electrode of the ESD diode.
5. The L ED chip structure of claim 4, wherein the first trace, the second trace, the N-type electrode and the P-type electrode of the LED, the N-type electrode and the P-type electrode of the ESD diode are made of the same material and formed in the same process step.
6. L ED chip structure according to claim 2,
the first type semiconductor layer is an N type semiconductor layer;
the second type semiconductor layer is a P type semiconductor layer.
7. L ED chip structure according to claim 2,
the first type semiconductor layer is a P type semiconductor layer;
the second type semiconductor layer is an N type semiconductor layer.
8. The L ED chip structure of claim 6 or 7,
the P-type semiconductor layer is a P-type gallium nitride layer, and the N-type semiconductor layer is an N-type gallium nitride layer.
9. An L ED chip structure manufacturing method, for manufacturing and forming the L ED chip structure of any one of claims 1-8, the manufacturing method comprising:
providing a substrate, wherein the substrate comprises a first region and a second region, the first region semi-surrounds the second region, and the area of the second region accounts for 5% -10% of the area of the substrate;
adopting the same process steps to simultaneously form a light emitting diode in the first area and an ESD diode in the second area, wherein the light emitting diode comprises an N-type electrode and a P-type electrode, and the ESD diode comprises an N-type electrode and a P-type electrode;
and electrically connecting the N-type electrode of the light-emitting diode with the P-type electrode of the ESD diode, and electrically connecting the P-type electrode of the light-emitting diode with the N-type electrode of the ESD diode.
10. The L ED chip structure manufacturing method of claim 9, further comprising, before forming the N-type and P-type electrodes:
forming a whole passivation layer to cover the light emitting diode and the epitaxial structure of the ESD diode;
and etching the passivation layer to form four openings which respectively correspond to the N-type electrode and the P-type electrode of the light-emitting diode and the N-type electrode and the P-type electrode of the ESD diode.
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2020
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|---|---|---|---|---|
| US20050274956A1 (en) * | 2004-05-26 | 2005-12-15 | Bhat Jerome C | LED chip with integrated fast switching diode for ESD protection |
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| CN107293629A (en) * | 2017-07-31 | 2017-10-24 | 广东工业大学 | A kind of ultraviolet LED epitaxial chip inverted structure and preparation method thereof |
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