CN111404526B - Programmable high-precision dynamic GaN driving circuit and application thereof - Google Patents

Programmable high-precision dynamic GaN driving circuit and application thereof Download PDF

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CN111404526B
CN111404526B CN202010197814.4A CN202010197814A CN111404526B CN 111404526 B CN111404526 B CN 111404526B CN 202010197814 A CN202010197814 A CN 202010197814A CN 111404526 B CN111404526 B CN 111404526B
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driving
circuit
fine
drive
coarse
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CN111404526A (en
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童乔凌
曾婉华
张毅
严金程
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/296—Time-programme switches providing a choice of time-intervals for executing more than one switching action and automatically terminating their operation after the programme is completed
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The invention belongs to the field of power semiconductor device switches, and particularly relates to a programmable high-precision dynamic GaN driving circuit and application thereof, wherein the circuit comprises a programmable digital module, a clock generation module and a driving module; the programmable digital module comprises an EEPROM reading circuit, a register circuit and a logic control circuit; the driving circuit includes a coarse driving circuit and a fine driving circuit. The on-off time is divided into a plurality of time periods, and each time period is a rough driving period; fine drive trimming may be performed once per coarse drive period to generate pulses to control the fine drive circuit drive current. After the power is on, off-chip data are stored in the register through the EEPROM reading circuit, the oscillator circuit controls the logic circuit to transmit required data to the driving circuit in the opening and closing processes, the rough driving circuit and the fine driving circuit of a plurality of rough driving periods are dynamically controlled, and programmable high-precision active GaN grid control is achieved.

Description

Programmable high-precision dynamic GaN driving circuit and application thereof
Technical Field
The invention belongs to the field of power semiconductor device switches, and particularly relates to a programmable high-precision dynamic GaN driving circuit and application thereof.
Background
Power electronic devices are widely used in people's daily life, wherein power semiconductor devices play a crucial role in power electronics. In a power semiconductor device, the performance of an MOSFET device basically tends to be mature and stable, and GaN is used as a new device which is different from the MOSFET in materials and structures and has smaller device size, lower on-resistance and smaller input capacitance; thereby enabling GaN to have faster switching speed and lower static loss.
The faster switching speed of GaN presents challenges to its driving, which can lead to more severe ringing and more overshoot, which not only can damage the device, but can also lead to parasitic conduction, resulting in through-burn out of the device. Typically, to reduce ringing and overshoot, the gate resistance needs to be increased to slow its turn-on speed, but this increases switching losses. There is a trade-off between switching speed and switching losses, and dynamic driving can effectively reduce ringing and overshoot without increasing switching losses. When the GaN-based transistor is switched on, the grid capacitor is rapidly charged by using a small grid driving resistor before the threshold voltage is reached, after a GaN channel is formed, the flowing GaN current rises, then the VDS voltage of the GaN-based transistor drops, and at the stage, the grid capacitor is slowly charged by using a large driving resistor, so that overshoot and ringing phenomena are suppressed. When the grid electrode is turned off, the grid electrode capacitor is discharged, before the grid electrode voltage is reduced to the threshold voltage, the small grid electrode driving resistor is adopted to quickly discharge the grid electrode capacitor, and when the channel is close to be closed, the large grid electrode driving resistor is adopted to slowly discharge the grid electrode capacitor, so that the overshoot and ringing phenomena are inhibited.
The driving method for controlling the grid driving voltage waveform can be realized in a closed loop feedback or open loop mode in theory. Closed-loop feedback is usually implemented by detecting GaN current and voltage, and adjusting the gate drive resistance in real time when the rising or falling speed is too fast, thereby controlling the on/off of the GaN. However, GaN switches at a fast speed, and the feedback loop takes a certain time to adjust the circuit, which is not suitable for driving GaN.
Disclosure of Invention
The invention provides a programmable high-precision dynamic driving GaN circuit and application thereof, which are used for solving the technical problem that a preset driving waveform cannot be obtained when GaN is driven due to driving delay of the conventional dynamic driving GaN circuit.
The technical scheme for solving the technical problems is as follows: a programmable high precision dynamically driven GaN circuit, comprising: the device comprises a programmable digital module, a driving module and a clock generating module; the programmable digital module comprises an EEPROM reading circuit, a register circuit and a logic control circuit; the driving module comprises a rough driving circuit and a fine driving circuit, wherein the outputs of the rough driving circuit and the fine driving circuit are electrically connected with a GaN grid electrode to be driven;
the control driving process of the logic control circuit is divided into a plurality of rough driving time periods, whether fine trimming is carried out once or not can be selected in each rough driving time period to change the driving current of the time period, and the driving data is stored in the programmable EEPROM outside the chip in a programmable mode;
after the power-on, the EEPROM reading circuit is used for reading out the drive data in the EEPROM and storing the drive data in the register circuit, an externally input PWM square wave signal is electrically connected with the input of the logic control circuit, and the drive module is closed and has no drive current until the action of the PWM square wave signal in the power-on process; after the PWM square wave signal acts, the logic control circuit transmits the driving data in the register circuit to the coarse driving circuit and the fine driving circuit according to the clock signal clk of the clock generating circuit, and controls the currents of the coarse driving and the fine driving for the plurality of coarse driving time periods, thereby achieving the desired dynamic driving waveform.
The invention has the beneficial effects that: the invention provides a programmable high-precision dynamic GaN driving circuit, which divides a driving process into a plurality of time periods of rough driving, wherein a plurality of main driving current grades can be selected in each period, whether fine trimming is carried out or not can be selected in each section to change the driving current of the circuit, the currents of the rough driving and the fine driving in eight time periods are controlled in a programmable mode so as to achieve an expected driving waveform, and the control precision is high.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, each coarse driving time period has a plurality of selectable coarse driving circuit current levels, and each fine driving also has a plurality of selectable fine driving circuit current levels, so that the driving data includes the coarse driving circuit current levels, the fine driving delay time, the fine driving pulse duration, and the fine driving circuit current levels in the plurality of coarse driving time periods.
The invention has the further beneficial effects that: each driving period of the rough driving can be provided with a large amount of selectable driving current, whether fine driving is carried out or not can be selected in each driving period of the rough driving, similarly, each fine driving can also be provided with a large amount of selectable driving current, the starting time, the duration and the like of the fine driving can be programmed, driving data can be set according to the actual driving waveform requirement, the driving controllability is high, and the expected driving waveform is finally achieved.
Further, the coarse driving circuit comprises first to eighth main driving circuits with different output current magnitudes, and the logic control circuit comprises a period counting circuit and first to eighth control main driving logic circuits;
the period counting circuit is used for counting the period of the rough driving time period after the PWM square wave signal is detected to jump; the first to eighth control main driving logic circuits are used for selecting corresponding driving data to control the first to eighth main driving circuits according to the rough driving time period indicated by the period counting circuit, so that the total current output by the rough driving circuit meets the current level of the rough driving circuit corresponding to the driving data.
The invention has the further beneficial effects that: the coarse driving circuit for coarse driving of the present invention includes first to eighth main driving circuits having different magnitudes of output currents, each main driving circuit having two choices of on and off at every coarse driving time period, and thus 2 in total8A switching sequence of 28The rough driving current levels are selectable, the selectivity is high, more expected driving waveforms can be met, and meanwhile the problem of poor controllability caused by excessive main driving circuits is solved.
Further, the period counting circuit is used for generating a short pulse by using the edge detection circuit after detecting that the transition of the PWM square wave signal occurs, the period count is cleared, the output from the output port L0 to the output port L2 is 000, which represents the first coarse driving time period, then the clock signal clk starts to be counted eight times, the output port L0 to the output port L2 sequentially increases from 000 to 111, namely the counting is stopped and the output is kept at 111, which represents that the eight coarse clock periods are counted completely.
Furthermore, each main driving circuit comprises a level shift circuit, a delay matching circuit, a first buffer circuit, a second buffer circuit, a driving PMOS tube and a driving NMOS tube;
the level shift circuit is used for improving the level of a logic signal input from the logic control circuit, the first buffer circuit is used for amplifying the driving capability of the logic signal output by the level shift circuit and driving the grid electrode of the driving PMOS tube, and the GaN grid electrode is charged when the driving PMOS tube is opened to open the GaN;
the delay matching circuit is used for ensuring that the delay from the logic signal input by the logic control circuit to the drive NMOS tube is the same as that of the drive PMOS tube; the second buffer circuit is used for amplifying the driving capability of the logic signal output by the delay matching circuit and driving the grid electrode of the driving NMOS tube; when the drive NMOS tube is opened, discharging the GaN grid electrode, and closing the GaN;
the first to eighth control main drive logic circuits are the same and each include a control main drive PMOS logic circuit and a control main drive NMOS logic circuit, and respectively control the switches of the drive PMOS transistors and the drive NMOS transistors of the first to eighth main drive circuits correspondingly.
The invention has the further beneficial effects that: each main driving circuit is divided into two paths of driving and is used for realizing the opening and closing of the GaN respectively, and each main driving circuit is provided with a level shift circuit, a delay matching circuit, a first buffer circuit and a second buffer circuit which realize the functions, so that the driving capability and the driving precision are ensured.
Further, taking the size of the driving PMOS transistor of the first main driving circuit as a unit, the sizes of the driving PMOS transistors of the first to eighth main driving circuits are respectively: 1. 2, 4, 16, 32, 64, 128, 256, the first to eighth main driving circuits are all selectable switches, and the rough driving circuit has 2 in its entirety in the process of driving GaN to be turned on8A coarse drive circuit current level;
taking the size of the drive NMOS tube of the first main drive circuit as a unit, the sizes of the drive NMOS tubes of the first to eighth main drive circuits are respectively as follows: 1. 2, 4, 16, 32, 64, 128, 256, the first to eighth main driving circuits can all select switches, and the rough driving circuit has 2 in the whole during driving the GaN to be turned off8A coarse drive circuit current level.
The invention has the further beneficial effects that: through the size design of the MOS tube, eight main driving circuits with different current output capacities are realized, and the circuit is simple and low in cost.
Further, the fine driving circuit comprises first to sixth auxiliary driving circuits, wherein each auxiliary driving circuit has the same structure as each main driving circuit, and the unit driving PMOS tube and the unit driving NMOS tube in each auxiliary driving circuit have different sizes from those of the unit driving PMOS tube and the unit driving NMOS tube in the main driving circuit;
the logic control circuit further includes first to sixth fine driving logic control circuits with the same structure, which respectively control the switches of the driving PMOS transistors and the driving NMOS transistors of the first to sixth sub-driving circuits correspondingly, so that when each coarse driving time period starts, after the fine driving delay time in the driving data corresponding to the period, the switches of the driving PMOS transistors and the driving NMOS transistors in the first to sixth sub-driving circuits are controlled according to the current levels of the fine driving circuits in the driving data, the duration of the fine driving pulse in the driving data corresponding to the period continues, and finally, all the fine driving circuits are turned off after the coarse driving time period ends.
Further, each of the fine drive logic control circuits includes first to seventh fine drive register logic circuits, a fine drive pulse generating circuit;
the first to seventh fine driving register logic circuits are used for selecting corresponding driving data according to the coarse driving time period indicated by the period indication circuit;
the fine driving pulse generating circuit is used for judging whether to generate a control pulse according to the selected driving data, if so, selecting and outputting the pulse width and the pulse delay to generate a fine driving pulse with adjustable width and delay.
The invention has the further beneficial effects that: different from the first to eighth control main driving logic circuits, the first to sixth fine driving logic control circuits are not divided into two circuits to respectively control the switches of the driving PMOS tube and the driving NMOS tube, so that fine trimming of the driving current is realized.
Further, the clock generation circuit comprises a ring oscillator circuit, a current generation circuit positively correlated with temperature and a current trimming circuit;
the ring oscillator circuit is used for generating a clock signal, and the precision of the clock signal is deviated due to temperature and a process angle;
the temperature positive correlation current generation circuit is used for generating a temperature positive correlation current to offset the deviation of the precision of the clock signal generated by the ring oscillator circuit along with the temperature;
the current trimming circuit is used for offsetting the deviation of the precision of the clock signal generated by the ring oscillator circuit along with the process angle in the temperature compensated clock signal output by the temperature positive correlation current generating circuit.
The invention has the further beneficial effects that: the current generation circuit and the current trimming circuit which are positively correlated with the temperature are adopted to trim the generated clock signal, so that the accuracy of driving on time is further ensured, and an expected driving waveform is obtained.
The invention also provides a dynamic driving method of the GaN power switch device, which adopts any one of the circuits for driving the GaN in a programmable high-precision dynamic mode to actively drive the GaN power switch device, so as to realize the dynamic driving of the GaN power switch device.
The invention has the beneficial effects that: by adopting the circuit for dynamically driving the GaN in the programmable high-precision manner, the driving of the GaN switch in the programmable high-precision manner is realized, the ringing and the overshoot are effectively reduced, the switch loss is not increased, and the practicability is high.
Drawings
FIG. 1 is a block diagram of a programmable high-precision dynamically-driven GaN circuit according to an embodiment of the invention;
FIG. 2 is a circuit diagram of a main driving circuit and a sub-driving circuit in a programmable high-precision dynamic GaN driving circuit according to an embodiment of the invention;
FIG. 3 is a diagram of a cycle counting circuit in a logic control module of the programmable high-precision dynamic GaN driving circuit according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a main driving logic circuit in a logic control module of the programmable high-precision dynamic GaN driving circuit according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a fine driving logic circuit in a logic control module of a programmable high-precision dynamic GaN driving circuit according to an embodiment of the invention;
fig. 6 is a schematic diagram of a fine driving period indication circuit in a fine driving logic circuit in a logic control module in a programmable high-precision dynamic GaN driving circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a fine driver register logic circuit in a fine driver logic circuit in a logic control module in a programmable high precision dynamic driver GaN driver circuit according to an embodiment of the invention;
fig. 8 is a timing diagram of the driving output current of the programmable high-precision GaN driving circuit according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example one
A programmable high-precision dynamic GaN driving circuit is shown in FIG. 1 and comprises: the device comprises a programmable digital module, a driving module and a clock generating module; the programmable digital module comprises an EEPROM reading circuit, a register circuit and a logic control circuit; the driving module comprises a rough driving circuit and a fine driving circuit, wherein the outputs of the rough driving circuit and the fine driving circuit are electrically connected with a GaN grid electrode to be driven;
the control driving process of the logic control circuit is divided into a plurality of rough driving time periods, whether fine trimming is carried out once or not can be selected in each rough driving time period to change the driving current of the time period, and the driving data is stored in the programmable EEPROM outside the chip in a programmable mode;
after the power-on, the EEPROM reading circuit is used for reading out the drive data in the EEPROM and storing the drive data in the register circuit, an externally input PWM square wave signal is electrically connected with the input of the logic control circuit, and the drive module is closed and has no drive current until the action of the PWM square wave signal in the power-on process; after the PWM square wave signal acts, the logic control circuit transmits the driving data in the register circuit to the coarse driving circuit and the fine driving circuit according to the clock signal clk of the clock generating circuit, and controls the currents of the coarse driving and the fine driving for the plurality of coarse driving time periods, thereby achieving the desired dynamic driving waveform.
The circuit divides the driving process into eight time periods of rough driving, wherein each period has a plurality of selectable main driving current levels, and each section can select whether to perform one fine trimming to change the driving current, and the currents of the rough driving and the fine driving in the eight time periods are controlled in a programmable mode to achieve the expected driving waveform.
Preferably, each coarse driving time period has a plurality of coarse driving circuit current levels selectable, each fine driving also has a plurality of fine driving circuit current levels selectable, and the driving data includes coarse driving circuit current levels for a plurality of coarse driving time periods, a fine driving delay time, a fine driving pulse duration, and fine driving circuit current levels for a plurality of coarse driving time periods.
Preferably, the coarse driving circuit includes first to eighth main driving circuits, and the fine driving circuit includes first to sixth sub driving circuits. The first to eighth main driving circuits have the same structure as the first to sixth sub-driving circuits. As shown in fig. 2, each main driving circuit includes a level shift circuit, a delay matching circuit, a first buffer circuit, a second buffer circuit, a driving PMOS transistor and a driving NMOS transistor, wherein the level shift circuit inputs a logic control circuit output, the level shift circuit outputs a current amplified step by the first buffer circuit and then is electrically connected to a gate of the driving PMOS transistor, the delay matching circuit inputs a logic control circuit output, the delay matching circuit outputs a current amplified step by the second buffer circuit and then is electrically connected to a gate of the driving NMOS transistor, and the driving PMOS transistor is electrically connected to a drain of the driving NMOS transistor.
The level shift circuit realizes the following functions: the logic signal level does not accord with the grid working range of the driving PMOS tube, and the level of the logic signals 0 and 1 is raised to VCC-5V and VCC, so that the switch of the driving PMOS tube can be effectively controlled; the level shift circuits of the different first to eighth main driving circuits are the same. The function that the time delay matching circuit realized does: the level shift circuit has time delay, and in order to ensure that the time delay from the logic signal to the driving PMOS tube is the same as the time delay from the logic signal to the driving NMOS tube, the level shift circuit is added before the driving NMOS tube; the delay matching circuits of the different first to eighth main driving circuits are the same. The first to second buffer circuits realize the functions of: the first buffer circuit amplifies the driving capability of the logic signal output by the level shift circuit and is used for driving the grid electrode of the PMOS tube; the second buffer circuit amplifies the driving capability of the logic signal output by the delay circuit and is used for driving the grid electrode of the NMOS tube; the first to the second buffer circuits of the first to the eighth main driving circuits have different buffer stages, and the larger the driving PMOS/NMOS transistor size is, the more the buffer stages are.
The fine drive circuit comprises first to sixth sub-drive circuits, except that the unit drive PMOS transistor and the drive NMOS transistor are different in size, only six sub-drive circuits are provided, so that the unit drive PMOS transistor and the unit drive NMOS transistor have 26Besides the driving capability grade, the rest circuits of the auxiliary driving circuit have the same structure as the main driving circuit.
Preferably, the driving capacities of the driving PMOS transistors and the driving NMOS transistors of the first to eighth main driving circuits are divided into eight output current levels: 1. 2, 4, 16, 32, 64, 128, 256, the coarse drive circuit has 2 as a whole8And output current level. The driving capability of the driving PMOS tube and the driving NMOS tube of the first to sixth secondary driving circuits is divided into six output current grades: 1. 2, 4, 16, 32, 64, the fine drive as a whole has 26And output current level. The concrete implementation is as follows:
with the first principalThe size of a driving PMOS tube of the driving circuit is one unit, and the sizes of the driving PMOS tubes of the first main driving circuit to the eighth main driving circuit are respectively as follows: 1. 2, 4, 16, 32, 64, 128, 256, the first to eighth main driving circuits can all select switches, and the rough driving circuit has 2 in the whole in the process of driving the GaN to be turned on8A coarse drive circuit current level. Taking the size of the drive NMOS tube of the first main drive circuit as a unit, the sizes of the drive NMOS tubes of the first to eighth main drive circuits are respectively as follows: 1. 2, 4, 16, 32, 64, 128, 256, the first to eighth main driving circuits can all select switches, and the rough driving circuit has 2 in the whole in the process of driving the GaN to be turned off8A driving capability level. The first to sixth auxiliary driving output current grades are realized to be the same as the main driving, but the size of a driving PMOS tube and the size of a driving NMOS tube of the first auxiliary driving are different from that of the first main driving, namely the unit driving current capacities of the main driving circuit and the auxiliary driving circuit are different.
When the PWM square wave signal jumps, the clock generation module is timed to output eight 2.5ns clock signals clk until the eight clock signals clk are generated, when each clock (period) starts, the logic control circuit takes out data corresponding to the current grade selection sequence of the rough driving circuit in the register circuit, controls the first to eighth main driving circuits to be switched, and keeps the switching state of the main driving circuit at the moment in the last rough driving period until the PWM square wave signal jumps again.
In each coarse driving period, whether fine driving fine adjustment is performed once can be selected, corresponding data in the register circuit is taken out by the logic control circuit, the data comprises fine driving pulse delay time, fine driving pulse duration and a fine driving current level selection sequence (a sequence formed by switching signals of six auxiliary driving circuits), when each coarse driving period starts, the fine driving delay time is passed, the first to sixth fine driving circuit switches are controlled according to the fine driving circuit current level selection sequence, the fine driving pulse duration in driving data corresponding to the period is continued, and finally all fine driving circuits are closed after the coarse driving period is ended.
Preferably, the register circuit is composed of DFFs (D flip-flops), and each bit data is latched by one DFF; the first to eighth main driving circuits comprise driving PMOS tubes and driving NMOS tubes, different switch states are possible in eight periods of the rough driving, and the rough driving module needs 8 × 2 to 128 DFFs for storing data; the first to sixth fine driving modules can select whether to generate a control pulse (1DFF), whether the pulse is a pull-up or a pull-down pulse, whether the pulse delay time is divided into eight levels (3DFF, output from a decoder circuit which converts 3 input into 8 output), and whether the pulse width time is divided into four levels (2DFF, output from a decoder circuit which converts 2 input into 4 output) in each coarse driving period, and have different switching states in eight periods of the coarse driving in the rising edge and the falling edge of the PWM square wave signal, so that 8 (1+1+3+2) × 6 × 2 is needed in total to be 672 DFFs; in addition, 4 bits of the coarse driving clock generation circuit need to be trimmed for the coarse driving clock generation circuit to be more accurate; the total required registers are thus 128+672+ 4-804 DFFs.
Preferably, the logic control circuit includes first to eighth control main drive logic circuits, first to sixth fine drive logic control circuits, and a cycle count circuit; the first to eighth control main drive logic circuits are the same and respectively comprise a control main drive PMOS logic circuit and a control main drive NMOS logic circuit which respectively control the switches of the drive PMOS tube and the drive NMOS tube of the first to eighth main drive circuits correspondingly; the first to sixth fine driving logic control circuits are also the same, and are used for controlling the switches of the driving PMOS transistors and the driving NMOS transistors of the first to sixth sub-driving circuits respectively, and are different from the first to eighth main driving logic circuits, and are not divided into two circuits for controlling the switches of the driving PMOS transistors and the driving NMOS transistors respectively.
As shown in fig. 3, the cycle counting circuit structure is: the input PWM square wave signal is electrically connected with a counter input clear signal CLR after passing through the edge detection circuit, a counter input clock signal clk is electrically connected with the output of the clock generation circuit, a counter output carry signal C is electrically connected with an input HOLD signal HOLD, and counters L0-L2 represent counting values.
As shown in fig. 4, the main driving PMOS logic circuit is controlled to implement the following functions: when the PWM square wave signal is low, the PWM square wave signal does not work, the output is high, and the main driving PMOS tube is controlled to be switched off; when the PWM square wave signal is high, the DFFs in the corresponding register circuits are selected to control their switching in eight coarse clock cycles according to 000 to 111 outputs of the cycle count circuits L0 to L2. The control main drive NMOS logic circuit has the same structure and similar function as the control main drive PMOS logic circuit, but does not work when the PWM square wave signal is high, the output is low, and the control main drive NMOS tube is switched off; the PWM square wave signal operates at low. Specifically, the structure of the control main drive PMOS logic circuit is as follows: the three-bit data input of the 3-8 decoder is electrically connected with the output signals L0-L2 of the period counting circuit, the enable input signal EN is electrically connected with the PWM square wave signal, each output and the DFF output of the PMOS driving tube switch corresponding to each eight rough driving periods of the main driving module in the register circuit are used as the input of a first AND gate, an eighth AND gate, the output of the eight AND gates and the input of the OR gate are electrically connected, the output of the OR gate and the input of the delay circuit are electrically connected, the output of the delay circuit and the PWM square wave signal are used as the input of the NAND gate and then are electrically connected with the input of the level shift circuit of the main driving circuit after passing through the NAND gate so as to control and drive the PMOS tube; the control main drive NMOS logic circuit structure is as follows: the data input of the 3-8 decoder is electrically connected with the output signals L0-L2 of the period counting circuit, the PWM square wave signals are electrically connected with an enable input signal EN after passing through a non-gate, each output and DFF output of the NMOS driving tube switch corresponding to each eight rough driving periods of the main driving module in the register circuit are used as first to eighth AND gate inputs, the eight AND gate outputs are electrically connected with an OR gate input, the OR gate output is electrically connected with a delay circuit input, the delay circuit output and the PWM square wave signals are used as the AND gate inputs and then are electrically connected with the delay matching circuit input of the main driving circuit after passing through the AND gate to control the driving of the NMOS tube.
The first to sixth fine driving logic control circuits are the same and respectively control the switches of the driving PMOS tube and the driving NMOS tube of the first to sixth fine driving circuits correspondingly. Each fine driving logic control circuit comprises a fine driving period indicating circuit, first to seventh fine driving register logic circuits and a fine driving pulse generating circuit, and the functions of the fine driving logic control circuit are realized as follows: and according to the coarse clock period indicated by the period counter, the first to seventh fine driving register logic circuits respectively select corresponding DFFs from the register circuits, and the values of the corresponding registers are used for controlling the eight clock periods to generate fine driving pulses with adjustable widths and delays. Wherein, the fine driving period indicating circuit realizes the following functions: according to the rough clock period indicated by the period counting circuit, different output channels are selected to be high, for example, the output channel 0 is high in the first rough clock period and the other is low, the output channel 1 is high in the second rough clock period and the other is low, and so on until the next rough clock period of the eighth rough clock period, all the output channels are cleared. The first to seventh fine drive register logic circuits implement the functions of: corresponding different DFFs are selected according to different coarse clock periods indicated by the fine driving period indication circuit and output. The fine driving pulse generating circuit realizes the following functions: and selecting whether to generate a control pulse according to the values output by the first to seventh fine driving register logic circuits, and if so, selecting the pulse width and the pulse length and outputting the pulse.
Specifically, as shown in fig. 5, the clock input of the 2-4 decoder in the pulse width generating circuit is electrically connected to the output of the clock generating module, the output of the first and second fine driving register logic circuits selects one of four different pulse units through the output of the 2-4 decoder, the four pulse units are connected in parallel, the output of the first and second fine driving register logic circuits is connected with the output of the third fine driving register logic circuit and the output of the clock generating module as the input of the clock generating module through the or gate and the not gate, the third fine driving register logic circuit determines whether to use fine driving, the output of the and gate is electrically connected with the clock input of the 3-8 decoder thereof as the input of the pulse delay generating circuit, the fourth to fifth fine driving register logic circuits select one of eight different delay units through the output of the 3-8 decoder, the eight delay units are connected in parallel, and the output of the seventh fine driving register logic circuit after the or gate and the input signal of the pulse delay generating circuit passes the or gate The logic circuit is used as the input of a 1-2 decoder, the seventh fine driving register logic circuit determines whether the output VP or VN generates pulses, the first output of the 1-2 decoder is electrically connected with the input of a level shift circuit in the secondary driving circuit to control the switch of a driving PMOS tube of the secondary driving circuit, and the second output is electrically connected with the input of a delay matching circuit in the secondary driving circuit to control the switch of a driving NMOS tube of the secondary driving circuit.
As shown in fig. 6, the fine drive period indication circuit structure is: the output signals from L0 to L2 of the period counting circuit are electrically connected with the three-bit data input of the 3-8 decoder, and the carry signal C is electrically connected with the enabling input signal EN of the 3-8 decoder after passing through the NOT gate; outputs 0-7 are shown during the corresponding coarse drive period.
As shown in fig. 7, the first to seventh fine drive register logic circuit structures are: the first to seventh fine driving register logic circuit inputs 0-7 are electrically connected with the fine driving period indicating circuit outputs 0-7, the other input is a PWM square wave signal, DFF (P0) to DFF (P7) store the switching states of the fine driving circuit in eight coarse driving periods after the PWM square wave signal jumps high, DFF (N0) to DFF (N7) store the switching states of the fine driving circuit in eight coarse driving periods after the PWM square wave signal jumps low, the PWM square wave signal is ANDed with DFF (P0) and inverted with PWM square wave signal PWM' and the DFF (N0) is ANDed, the two AND gate outputs are ANDed with the input signal 0 or gate, the switching state of the fine driving circuit in the first coarse driving period is represented, and the following seven circuits represent the switching state of the fine driving circuit in the following seven coarse driving periods, the eight AND gate outputs are the outputs of the fine driving register logic circuit through an OR gate.
A current generation circuit and a current trimming circuit which are positively correlated with the temperature; preferably, the clock generation module includes a ring oscillator circuit, a positive temperature correlation (PTAT) current generation circuit, and a current trimming circuit, and the clock generation module implements the following functions: a 400MHz clock signal clk is generated to generate a coarse clock period for use by the logic control module. Specifically, the ring oscillator circuit performs the function of generating an inaccurate 400MHz clock signal, the accuracy of which deviates with temperature and process angle; the PTAT current generating circuit has the function of generating current positively correlated with temperature and offsetting the deviation of the precision of a 400MHz clock signal generated by the ring oscillator circuit along with the temperature; the PTAT current generating circuit mirrors the PTAT current to the current trimming circuit, the trimming circuit is divided into four paths controlled by 4 DFFs, the step length is 1/21 of the main PTAT current, the four paths of currents are 1/21, 2 (1/21), 4 (1/21) and 8 (1/21) times of the PTAT current when being switched on, the trimming current and the PTAT current are added and then mirrored to the tail current of the ring oscillator circuit, and the deviation of the precision of a 400MHz clock signal generated by the ring oscillator circuit along with a process angle is counteracted, so that a stable clock period is obtained under different Corner and temperatures.
To better explain the circuit, a control method of the programmable high-precision dynamic GaN driving circuit is described as follows, including:
after the power is on, the EEPROM reading circuit reads data in the EEPROM and stores the data in the register circuit, wherein the data comprise current levels, fine driving delay time and fine driving pulse duration in a coarse driving circuit for roughly driving eight time periods; and in the power-on process, the driving circuit is closed and no driving current exists until the PWM square wave signal acts.
After the PWM square wave signal jumps, the period counting circuit counts the output clock of the clock generating circuit, wherein the edge detecting circuit generates short pulses, the counter is cleared, the outputs L0 to L2 of the counter are counted from 000 to 111 in sequence along with the rising edge of the clk signal, when the count reaches 111, the carry signal C is inverted to 1, the input signal HOLD is also 1, and the output keeps 111 unchanged, which indicates that eight coarse clock periods are ended;
in a first period of PWM square wave signal jumping, the output of a period counting circuit is L0-L2 is 000, for a main driving logic circuit, if the PWM square wave signal is high, a 3-8 decoder in the main driving PMOS logic circuit starts to work, an output channel is 0 jump high, a DFF (on0) register is selected, the register indicates whether a PMOS driving tube of a rough driving circuit corresponding to the main driving logic circuit is opened in the first rough driving period, the output VP is DFF (on0) data, in a second rough driving period, the main driving PMOS logic circuit selects DFF (on1) until the output of the period counting circuit is L0-L2 is 111, the DFF (on7) is gated, and when the PWM square wave signal is high, the PMOS driving tube of the rough driving circuit keeps the state of the last rough driving period; when the PWM square wave signal jumps to be low, the 3-8 decoder in the main drive NMOS logic circuit starts to work, the working principle and the process are similar to those of the main drive PMOS logic circuit, and VN is output to control the state of an NMOS drive tube of the rough drive circuit.
For the fine driving logic circuit, after the PWM square wave signal jumps, in the fine driving period indicating circuit, the period counting circuit is cleared, the EN signal of the 3-8 decoder is high, the output channel 0 is high, the output channel 1 of the second coarse driving period is high until the outputs of the period counting circuits L0-L1 are 111, and then the next clk jump, the output carry signal C jumps high, the EN signal of the 3-8 decoder is low, and the output channels 0-7 are all 0; for the first to seventh fine driving register logic circuits, if the PWM square wave signal jumps on the rising edge, the DFF (P0) register in the corresponding circuit is selected to output the data of the DFF (P0), and if the PWM square wave signal jumps on the falling edge, the DFF (N0) register in the corresponding circuit is selected to output the data of the DFF (N0) until eight coarse driving cycles are completed; the output of the clock generating circuit is electrically connected with an enable input EN signal, after the clock generating circuit jumps high, a 2-4 decoder in the pulse generating circuit works, selects a corresponding pulse unit according to the output of the first fine driving register logic circuit and the second fine driving register logic circuit, and outputs the pulse unit after passing through an OR gate; in addition, the third fine driving register logic circuit outputs to determine whether the coarse driving period is fine trimmed, if not, the coarse driving period is output to be 0, namely, a pulse wave with the pulse width length of 0 is output, and if the fine driving is used, the output time sequence of the pulse width generating circuit is the input time sequence of the pulse delay circuit; the pulse width generating circuit and the third fine driving register logic circuit are input into the pulse delay generating circuit after passing through an AND gate, after the pulse width generating circuit and the third fine driving register logic circuit jump to be high, the 3-8 decoder starts to work, corresponding delay units are selected according to the output of the fourth to sixth fine driving register logic circuits, and the delay units are output after passing through an OR gate; in addition, the seventh fine driving register logic output determines whether the coarse driving period is a pull-up or a pull-down, if its output is 0, it means pull-down, output VP is low, VN is high, if its output is 1, it means pull-up, output VP is high, VN is low; VP controls the switch of PMOS driving tube of the sub-driving circuit, VN controls the switch of NMOS driving tube of the sub-driving circuit.
The main drive circuit and the auxiliary drive circuit have the same structure, the output VP of the logic control circuit promotes the level displacement of logic signals 0 and 1 to VCC and VCC-5V after passing through the level displacement circuit of the main drive circuit and the auxiliary drive circuit, the output VP is electrically connected with the grid electrode of the drive PMOS after amplifying the current step by step through the buffer circuit, and the GaN grid electrode is charged when the drive PMOS is switched on; after the output VN of the logic control circuit is matched with the time delay of the main driving circuit and the auxiliary driving circuit, the output VN is electrically connected with the grid electrode of the driving NMOS after the current is amplified step by step through the buffer circuit, and when the driving NMOS is conducted, the GaN grid electrode is discharged.
As shown in fig. 8, the timing diagram of the driving output current of the programmable high-precision dynamic GaN driving circuit is as follows: after the PWM square wave signal jumps to be high, in a first rough driving time period, selecting which main driving circuit in the first to eighth main driving circuits to drive a PMOS tube to be opened according to the value of the corresponding DFF in the register circuit, thereby selecting the main driving circuit driving current in the first rough driving time period to charge a GaN grid electrode, and simultaneously selecting whether to generate a fine driving pulse, the duration of the fine driving pulse, the delay time of the fine driving pulse, and which auxiliary driving circuits in the first to sixth auxiliary driving circuits to drive the PMOS tube and a switch of an NMOS tube according to the value of the corresponding DFF in the register circuit; during the second to eighth coarse driving time periods, the magnitude of the main driving current and the fine driving pulse width, delay and current can be selected similarly; the driving current time sequence after the PWM square wave signal jumps to be low is the same as that when the PWM square wave signal jumps to be high, and the difference is that the first to eighth main driving circuit selection switches are driving NMOS tubes. The driving currents shown in fig. 8 are an example, and in practice, the magnitude of the main driving current, the fine driving delay, the duration and the current magnitude can be selected according to the requirement every coarse driving time period.
The control method is characterized in that the on-off process is processed in a segmented mode, and in each segment, different driving currents are selected through logic programming, so that the gate driving process is controlled to achieve the optimal driving waveform.
Example two
A dynamic driving method of a GaN power switch device adopts any one of the circuits for driving GaN in a programmable high-precision dynamic mode to actively drive the GaN power switch device, so that the dynamic driving of the GaN power switch device is realized.
By adopting the circuit for dynamically driving the GaN in the programmable high-precision manner, the driving of the GaN switch in the programmable high-precision manner is realized, the ringing and the overshoot are effectively reduced, the switch loss is not increased, and the practicability is high.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (9)

1. A programmable high-precision dynamic GaN driving circuit, comprising: the device comprises a programmable digital module, a driving module and a clock generating module; the programmable digital module comprises an EEPROM reading circuit, a register circuit and a logic control circuit; the driving module comprises a rough driving circuit and a fine driving circuit, wherein the outputs of the rough driving circuit and the fine driving circuit are electrically connected with a GaN grid electrode to be driven;
the control driving process of the logic control circuit is divided into a plurality of rough driving time periods, whether fine trimming is carried out once or not can be selected in each rough driving time period to change the driving current of the rough driving time period, and the driving data is stored in an off-chip programmable EEPROM in a programmable mode;
after the power-on, the EEPROM reading circuit is used for reading out the drive data in the EEPROM and storing the drive data in the register circuit, an externally input PWM square wave signal is electrically connected with the input of the logic control circuit, and the drive module is closed and has no drive current until the action of the PWM square wave signal in the power-on process; after the PWM square wave signal acts, the logic control circuit transmits the driving data in the register circuit to the coarse driving circuit and the fine driving circuit according to the clock signal clk of the clock generation module, and controls the currents of the coarse driving and the fine driving for the plurality of coarse driving time periods, so as to achieve the desired dynamic driving waveform;
each coarse driving time period has a plurality of coarse driving circuit current levels selectable, each fine driving also has a plurality of fine driving circuit current levels selectable, and the driving data includes the coarse driving circuit current levels of the plurality of coarse driving time periods, the fine driving delay time, the fine driving pulse duration, and the fine driving circuit current levels of the plurality of coarse driving time periods.
2. The circuit of claim 1, wherein the coarse driving circuit comprises first to eighth main driving circuits with different output current levels, and the logic control circuit comprises a cycle counting circuit, first to eighth control main driving logic circuits;
the period counting circuit is used for counting the period of the rough driving time period after the PWM square wave signal is detected to jump; the first to eighth control main driving logic circuits are used for selecting corresponding driving data to control the first to eighth main driving circuits according to the rough driving time period indicated by the period counting circuit, so that the total current output by the rough driving circuit meets the current level of the rough driving circuit corresponding to the driving data.
3. The programmable high-precision dynamic driving GaN circuit of claim 2, wherein the period counting circuit is configured to generate a short pulse by using the edge detection circuit after detecting a transition of the PWM square wave signal, the period count is cleared, the output from the output L0 to the output L2 port is 000 to indicate a first coarse driving time period, then the clock signal clk starts to be counted eight times, the output from the output L0 to the output L2 port is sequentially incremented from 000 to 111, and the counting is stopped and the output is kept at 111 to indicate that eight coarse clock periods are counted.
4. The circuit of claim 2, wherein each of the main driving circuits comprises a level shift circuit, a delay matching circuit, a first buffer circuit, a second buffer circuit, a driving PMOS transistor and a driving NMOS transistor;
the level shift circuit is used for improving the level of a logic signal input from the logic control circuit, the first buffer circuit is used for amplifying the driving capability of the logic signal output by the level shift circuit and driving the grid electrode of the driving PMOS tube, and the GaN grid electrode is charged when the driving PMOS tube is opened to open the GaN;
the delay matching circuit is used for ensuring that the delay from the logic signal input by the logic control circuit to the drive NMOS tube is the same as that of the drive PMOS tube; the second buffer circuit is used for amplifying the driving capability of the logic signal output by the delay matching circuit and driving the grid electrode of the driving NMOS tube; when the drive NMOS tube is opened, discharging the GaN grid electrode, and closing the GaN;
the first to eighth control main drive logic circuits are the same and each include a control main drive PMOS logic circuit and a control main drive NMOS logic circuit, and respectively control the switches of the drive PMOS transistors and the drive NMOS transistors of the first to eighth main drive circuits correspondingly.
5. The programmable high-precision dynamic GaN driving circuit of claim 4, wherein the driving PMOS transistor sizes of the first to eighth main driving circuits are respectively, in units of the driving PMOS transistor size of the first main driving circuit: 1. 2, 4, 16, 32, 64, 128, 256, first to eighth main driving circuits each select a switch, and the coarse driving circuit has 2 as a whole in driving the GaN on8A coarse drive circuit current level;
the size of a drive NMOS tube of the first main drive circuit is oneThe unit, the drive NMOS pipe size of first to eighth main drive circuit is respectively: 1. 2, 4, 16, 32, 64, 128, 256, first to eighth main driving circuits all select switches, and the coarse driving circuit has 2 as a whole in driving the GaN off8A coarse drive circuit current level.
6. The circuit of claim 5, wherein the fine driving circuit comprises first to sixth sub-driving circuits, wherein each sub-driving circuit has the same structure as each main driving circuit, and the unit driving PMOS transistor and the unit driving NMOS transistor in each sub-driving circuit have different sizes from those of the unit driving PMOS transistor and the unit driving NMOS transistor in the main driving circuit;
the logic control circuit further includes first to sixth fine driving logic control circuits with the same structure, which respectively control the switches of the driving PMOS transistors and the driving NMOS transistors of the first to sixth sub-driving circuits correspondingly, so that when each coarse driving time period starts, after the fine driving delay time in the driving data corresponding to the period, the switches of the driving PMOS transistors and the driving NMOS transistors in the first to sixth sub-driving circuits are controlled according to the current levels of the fine driving circuits in the driving data, the duration of the fine driving pulse in the driving data corresponding to the period continues, and finally, all the fine driving circuits are turned off after the coarse driving time period ends.
7. The circuit of claim 6, wherein each of said fine drive logic control circuits comprises first through seventh fine drive register logic circuits, a fine drive pulse generation circuit;
the first to seventh fine driving register logic circuits are used for selecting corresponding driving data according to the coarse driving time period indicated by the period indication circuit;
the fine driving pulse generating circuit is used for judging whether to generate a control pulse according to the selected driving data, if so, selecting and outputting the pulse width and the pulse delay to generate a fine driving pulse with adjustable width and delay.
8. The circuit of any one of claims 1 to 7, wherein the clock generation module comprises a ring oscillator circuit, a current generation circuit positively correlated to temperature, and a current trimming circuit;
the ring oscillator circuit is used for generating a clock signal, and the precision of the clock signal is deviated due to temperature and a process angle;
the temperature positive correlation current generation circuit is used for generating a temperature positive correlation current to offset the deviation of the precision of the clock signal generated by the ring oscillator circuit along with the temperature;
the current trimming circuit is used for offsetting the deviation of the precision of the clock signal generated by the ring oscillator circuit along with the process angle in the temperature compensated clock signal output by the temperature positive correlation current generating circuit.
9. A dynamic driving method of a GaN power switch device is characterized in that the circuit of programmable high-precision dynamic driving GaN according to any one of claims 1 to 8 is adopted to actively drive the GaN power switch device, so as to realize the dynamic driving of the GaN power switch device.
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