CN111403293A - Preparation method of JFET (junction field effect transistor) device and JFET device - Google Patents
Preparation method of JFET (junction field effect transistor) device and JFET device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Abstract
The application discloses a preparation method of a JFET device and the JFET device, wherein the method comprises the following steps: providing a substrate, wherein the substrate is a P-type substrate, and a deep N-type well is formed in the substrate; forming a field oxide layer on the substrate, wherein the deep N-type well covers the bottom of the field oxide layer; forming at least two N-type wells in the deep N-type well, and forming a first P-type well and a second P-type well on the outer periphery side of the deep N-type well; forming a PTOP in the deep N-well, the PTOP separating the deep N-well into an upper region and a lower region, two ends of the PTOP contacting the first P-well and the second P-well, respectively, at least two N-wells located in the upper region; and forming a P-type heavily doped region outside the N-type well in the deep N-type well, forming a first N-type heavily doped region in the first N-type well, and forming a second N-type heavily doped region in the second N-type well. According to the method, the N-type trap is formed in the deep N-type trap of the JFET device, so that the problem that the conduction current of the JFET device is small due to the fact that the carrier concentration of the deep N-type trap is low is solved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a JFET device and the JFET device.
Background
A Junction Field-Effect Transistor (JFET) is a three-terminal active device with an amplifying function, which is composed of a Gate (Gate), a Source (Source), and a Drain (Drain) of a PN Junction, and its operating principle is to control an output current by changing the conductivity of a channel through a voltage.
The BCD (Bipolar-CMOS-DMOS) process is a process of fabricating a Bipolar Junction Transistor (BJT) device, a Complementary Metal-oxide semiconductor (CMOS) device, and a DMOS device on the same chip (Die). The device manufactured by adopting the BCD process is widely applied to the fields of power management, display driving, automobile electronics, industrial control and the like.
Referring to fig. 1, a schematic cross-sectional view of a JFET device prepared based on a BCD process is shown, and as shown in fig. 1, the JFET device includes a P-type substrate 101, a deep N-type Well (DNW) 102 is formed in the P-type substrate 101, a P-type Well (PW) 104 is formed in the deep N-type Well, floating P-type structures (PTOP, P-type ion implantation) 1051, 1052 are formed between the P-type 104 and the deep N-type Well 102, a field oxide (L organic oxidation of Silicon, L OCOS) layer 103 is formed on the P-type substrate 101, and heavily doped N-type regions 1071, 1072 are formed in the P-type substrate 101 on both sides of the field oxide layer 103.
As shown in fig. 1, the JFET device pinches off the P-well and the deep N-well by providing a structure of P-well-PTOP-deep N-well, which may be modified to a P-heavily doped region-PTOP-deep N-well in the related art to make the depth of the deep N-well shallow to obtain a lower pinch-off voltage, however, in the modified structure, the on-current of the JFET device is smaller.
Disclosure of Invention
The application provides a preparation method of a JFET device and the JFET device, and the problem that the conducting current of the JFET device provided in the related technology is small can be solved.
In one aspect, an embodiment of the present application provides a method for manufacturing a JFET device, including:
providing a substrate, wherein the substrate is a P-type substrate, and a deep N-type well is formed in the substrate;
forming a field oxide (L cal Oxidation of Silicon, L OCOS) layer on the substrate, the deep N-well covering the bottom of the field oxide layer;
forming at least two N-type wells in the deep N-type well, and forming a first P-type well and a second P-type well on the outer periphery side of the deep N-type well;
forming a PTOP in the deep N-well, the PTOP separating the deep N-well into an upper region and a lower region, two ends of the PTOP contacting a first P-well and a second P-well, respectively, the at least two N-wells located in the upper region;
and forming a P-type heavily doped region outside the N-type well in the deep N-type well, forming a first N-type heavily doped region in the first N-type well, and forming a second N-type heavily doped region in the second N-type well.
Optionally, at least four field oxide layers are formed on the substrate;
the substrate is formed with the field oxide layer formed on the substrate, including:
covering a photoresist in a first target area through a photoetching process, wherein the first target area is the other area on the substrate except the areas corresponding to the at least four field oxide layers;
growing a field oxide layer on the exposed area on the substrate through a field oxide process to form the at least four field oxide layers;
and removing the photoresist.
Optionally, along a long direction of a cross section of the substrate, the at least four field oxide layers include a first field oxide layer, a second field oxide layer, a third field oxide layer, and a fourth field oxide layer in sequence, and the at least two N-type wells include a first N-type well and a second N-type well in sequence;
the first field oxide layer and the second field oxide layer are formed on the first N-type well, and the third field oxide layer and the fourth field oxide layer are formed on the second N-type well.
Optionally, the P-type heavily doped region is formed between the second field oxide layer and the third field oxide layer, the first N-type heavily doped region is formed between the first field oxide layer and the second field oxide layer, and the second N-type heavily doped region is formed between the third field oxide layer and the fourth field oxide layer.
Optionally, the forming a P-type heavily doped region in the upper region, forming a first N-type heavily doped region in the first N-type well, and forming a second N-type heavily doped region in the second N-type well further includes:
and forming metal electrodes on the P-type heavily doped region, the first N-type heavily doped region and the second N-type heavily doped region.
Optionally, before forming the field oxide layer on the substrate, the method further includes:
and carrying out N-type ion implantation on the substrate to form the deep N-type well.
Optionally, the forming at least two N-type wells in the deep N-type well includes:
covering a second target area with a light resistance through a photoetching process, wherein the second target area is the other area on the substrate except the areas corresponding to the at least two N-type wells;
carrying out N-type ion implantation on the exposed area on the substrate to form at least two N-type wells;
and removing the photoresist.
Optionally, the forming a first P-type well and a second P-type well on an outer periphery side of the deep N-type well includes:
covering a photoresist in a third target area through a photoetching process, wherein the third target area is the other area on the substrate except the area corresponding to the first P-type well and the second P-type well;
performing P-type ion implantation on the exposed region on the substrate to form the first P-type well and the second P-type well;
and removing the photoresist.
In another aspect, the present application provides a JFET device comprising:
the substrate is a P-type substrate, a deep N-type well is formed in the substrate, at least two N-type wells and a PTOP are formed in the deep N-type well, a first P-type well and a second P-type well are formed on the outer peripheral side of the deep N-type well in the substrate, the PTOP divides the deep N-type well into an upper area and a lower area, two ends of the PTOP are respectively contacted with the first P-type well and the second P-type well, and the at least two N-type wells are located in the upper area;
the field oxide layer is formed on the deep N-type well, and the bottom of the field oxide layer is covered by the deep N-type well;
the P-type heavily doped region is formed in the deep N-type well and is positioned outside the N-type well;
the first N-type heavily doped region is formed in the first N-type well;
and the second N-type heavily doped region is formed in the second N-type well.
Optionally, at least four field oxide layers are formed on the substrate, and along a long direction of a cross section of the substrate, the at least four field oxide layers include a first field oxide layer, a second field oxide layer, a third field oxide layer and a fourth field oxide layer in sequence, and the at least two N-type wells include a first N-type well and a second N-type well in sequence;
the first field oxide layer and the second field oxide layer are formed on the first N-type well, and the third field oxide layer and the fourth field oxide layer are formed on the second N-type well.
Optionally, the P-type heavily doped region is formed between the second field oxide layer and the third field oxide layer, the first N-type heavily doped region is formed between the first field oxide layer and the second field oxide layer, and the second N-type heavily doped region is formed between the third field oxide layer and the fourth field oxide layer.
Optionally, metal electrodes are formed on the P-type heavily doped region, the first N-type heavily doped region and the second N-type heavily doped region.
The technical scheme at least comprises the following advantages:
at least two N-type wells are formed in the deep N-type well of the JFET device, and due to the fact that the carrier concentration of the N-type wells is high, the problem that the conducting current of the JFET device is small due to the fact that the carrier concentration of the deep N-type wells is low is solved, and the conducting current of the JFET device is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional view showing a JFET device fabricated based on a BCD process;
fig. 2 is a flow chart of a method of making a JFET device provided by an exemplary embodiment of the present application;
fig. 3-7 are flow diagrams of the fabrication of a JFET device provided by an exemplary embodiment of the present application;
figure 8 is a simulation result of a JFET device provided by an exemplary embodiment of the present application;
fig. 9-11 are schematic diagrams of pinch-off voltages for JFET devices of different inter-well spacings.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flow chart of a method for manufacturing a JFET device according to an exemplary embodiment of the present application is shown, the method can be applied to a manufacturing process of a wafer for manufacturing the JFET device by using a BCD process, as shown in fig. 2, the method includes:
Referring to fig. 3, a schematic cross-sectional view of a deep N-well 302 formed on a substrate 301 is shown. Illustratively, as shown in fig. 3, the substrate 301 is a P-type substrate, and a deep N-well 302 may be formed by performing N-type ion implantation on the substrate 301. For example, the photoresist may be covered on the substrate 301 except the region corresponding to the deep N-well 302 by a photolithography process, N-type ion implantation may be performed on the exposed region of the substrate 301 to form the deep N-well 302, and the photoresist may be removed.
Referring to fig. 4, a schematic cross-sectional view of forming a field oxide layer on a substrate 301 is shown. Illustratively, as shown in fig. 4, at least four field oxide layers (illustratively, four field oxide layers, i.e., a first field oxide layer 3031, a second field oxide layer 3032, a third field oxide layer 3033, and a fourth field oxide layer 3034, which are sequentially formed in a longitudinal direction of a cross section of the substrate 101 (a direction indicated by an arrow in fig. 4)) are formed on the substrate 301, and the bottom of the formed field oxide layers is covered by the deep N-type well 302.
Optionally, in step 202, "forming a field oxide layer on the substrate" includes, but is not limited to: covering a photoresist in a first target area through a photoetching process, wherein the first target area is the other area except the area corresponding to at least four field oxide layers on the substrate 301; growing a field oxide layer on the exposed area of the substrate 301 through a field oxide process to form at least four field oxide layers; and removing the photoresist.
Referring to FIG. 5, a cross-sectional schematic of forming an N-well and a P-well is shown. As shown in fig. 5, at least two N-wells are formed in deep N-well 302 (exemplarily illustrated in fig. 5 by two N- wells 3041, 3042 formed in order in a direction along a length of a cross section of substrate 101), and in substrate 301, first P-well 3051 and second P-well 3052 are formed on an outer peripheral side of deep N-well 302.
Optionally, in step 203, the "forming at least two N-wells in a deep N-well" includes but is not limited to: covering a photoresist in a second target area by a photoetching process, wherein the second target area is the other area except the area corresponding to the at least two N-type wells on the substrate 301; performing N-type ion implantation on the exposed area on the substrate 301 to form at least two N-type wells; and removing the photoresist.
Alternatively, in step 203, "forming the first P-well and the second P-well on the outer periphery side of the deep N-well" includes, but is not limited to: covering a photoresist in a third target area by a photoetching process, wherein the third target area is the other area on the substrate 301 except for the area corresponding to the first P-type well 3051 and the second P-type well 3052; performing P-type ion implantation on the exposed region on the substrate 301 to form a first P-type well 3051 and a second P-type well 3052; and removing the photoresist.
And 204, forming a PTOP in the deep N-well, wherein the PTOP separates the deep N-well into an upper region and a lower region, two ends of the PTOP are respectively contacted with the first P-well and the second P-well, and at least two N-wells are positioned in the upper region.
Referring to fig. 6, a cross-sectional schematic of forming a PTOP306 in a deep N-well 302 is shown. As shown in fig. 6, PTOP306 separates deep N-well 302 into an upper region 3021 and a lower region 3022, with one end of PTOP306 in contact with a first P-well 3051, the other end of PTOP306 in contact with a second P-well 3052, the N-well located in upper region 3021, and PTOP306 may be grounded via first P-well 3051 and second P-well 3052.
Referring to fig. 7, a cross-sectional view of forming the first N-type heavily doped region 3071, the second N-type heavily doped region 3072 and the P-type heavily doped region 308 is shown. Illustratively, as shown in fig. 7, a first heavily doped N-type region 3071 is formed in the first N-type well 3041 and a second heavily doped N-type region 3072 is formed in the second N-type well 3042 by N-type ion implantation; by P-type ion implantation, a P-type heavily doped region 308 is formed in the deep N-well 302, in the regions outside the first N-well 3041 and the second N-well 3042. The first N-type heavily doped region 3071 can be led out to be used as a drain electrode of the JFET device, the second N-type heavily doped region 3072 can be led out to be used as a source electrode of the JFET device, and the P-type heavily doped region 308 can be led out to be used as a grid electrode of the JFET device.
Optionally, the P-type heavily doped region is formed 308 between the second field oxide layer 3032 and the third field oxide layer 3033, the first N-type heavily doped region 3071 is formed between the first field oxide layer 3031 and the second field oxide layer 3032, and the second N-type heavily doped region 3072 is formed between the third field oxide layer 3033 and the fourth field oxide layer 3034.
Optionally, as shown in fig. 7, after step 205, the method further includes: a metal electrode 309 is formed on the P-type heavily doped region 308, the first N-type heavily doped region 3071, and the second N-type heavily doped region 3072. For example, the metal electrode 309 may be formed by covering the substrate 101 with photoresist except for the region corresponding to the metal electrode 309, filling the exposed region with a metal layer by electroplating or deposition, and removing the photoresist. The metal electrode 309 is made of at least one of aluminum, tungsten, and copper.
To sum up, in the embodiment of the application, at least two N-type traps are formed in the deep N-type trap of the JFET device, and due to the fact that the carrier concentration of the N-type traps is high, the problem that the conducting current of the JFET device is small due to the fact that the carrier concentration of the deep N-type traps is low is solved, and the conducting current of the JFET device is improved.
Referring to fig. 7, there is shown a schematic cross-sectional view of a JFET device provided by an exemplary embodiment of the present application, the device being fabricated by the method described above, the device comprising:
A field oxide layer (exemplarily illustrated as a first field oxide layer 3031, a second field oxide layer 3032, a third field oxide layer 3033, and a fourth field oxide layer 3034 in fig. 7) is formed on the deep N-well 302, and the deep N-well 302 covers the bottom of the field oxide layer.
A heavily P-doped region 308 formed in the deep N-well 302 and outside the N-well.
A first N-type heavily doped region 3071 formed in the first N-well 3041.
A second heavily N-doped region 3072 formed in the second N-well 3042.
Optionally, as shown in fig. 7, at least four field oxide layers are formed on the substrate 301, and along a long direction of the cross section of the substrate 301 (as shown by arrows in fig. 4), the at least four field oxide layers include a first field oxide layer 3031, a second field oxide layer 3032, a third field oxide layer 3033, and a fourth field oxide layer 3034, the at least two N-type wells include a first N-type well 3041 and a second N-type well 3042, the first field oxide layer 3031 and the second field oxide layer 3032 are formed on the first N-type well 3041, and the third field oxide layer 3033 and the fourth field oxide layer 3034 are formed on the second N-type well 3042.
Optionally, as shown in fig. 7, the P-type heavily doped layer is formed between the second field oxide layer 3032 and the third field oxide layer 3033, the first N-type heavily doped region 3071 is formed between the first field oxide layer 3031 and the second field oxide layer 3032, and the second N-type heavily doped region 3072 is formed between the third field oxide layer 3033 and the fourth field oxide layer 3034.
Optionally, as shown in fig. 7, a metal electrode 309 is formed on the P-type heavily doped region 308, the first N-type heavily doped region 3071, and the second N-type heavily doped region 3072.
Referring to fig. 8, simulation results of a JFET device provided by an exemplary embodiment of the present application are shown. As shown in fig. 8, the depletion region of the JFET device at pinch-off is 800 (dark gray area in fig. 8).
Optionally, in the above embodiment, a value range of an inter-well distance between the first N-type well and the second N-type well is 2 to 4 micrometers, and the clamping voltage may be adjusted by adjusting the inter-well distance between the first N-type well and the second N-type well.
Referring to fig. 9-11, there are shown schematic diagrams of pinch-off voltages for JFET devices of different inter-well spacings. As shown in fig. 9, the pinch-off voltage is 3.5 volts when the inter-well spacing is 4 microns; as shown in fig. 10, the pinch-off voltage is 4 volts when the inter-well spacing is 3 microns; as shown in fig. 11, the pinch-off voltage is 4.5 volts when the inter-well spacing is 2 microns.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (12)
1. A method of fabricating a JFET device, comprising:
providing a substrate, wherein the substrate is a P-type substrate, and a deep N-type well is formed in the substrate;
forming a field oxide layer on the substrate, wherein the deep N-type well covers the bottom of the field oxide layer;
forming at least two N-type wells in the deep N-type well, and forming a first P-type well and a second P-type well on the outer periphery side of the deep N-type well;
forming a PTOP in the deep N-well, the PTOP separating the deep N-well into an upper region and a lower region, two ends of the PTOP contacting a first P-well and a second P-well, respectively, the at least two N-wells located in the upper region;
and forming a P-type heavily doped region outside the N-type well in the deep N-type well, forming a first N-type heavily doped region in the first N-type well, and forming a second N-type heavily doped region in the second N-type well.
2. The production method according to claim 1, wherein at least four field oxide layers are formed on the substrate;
the substrate is formed with the field oxide layer formed on the substrate, including:
covering a photoresist in a first target area through a photoetching process, wherein the first target area is the other area on the substrate except the areas corresponding to the at least four field oxide layers;
growing a field oxide layer on the exposed area on the substrate through a field oxide process to form the at least four field oxide layers;
and removing the photoresist.
3. The production method according to claim 2, wherein, in a direction of a length of a cross section of the substrate, the at least four field oxide layers include a first field oxide layer, a second field oxide layer, a third field oxide layer, and a fourth field oxide layer in this order, and the at least two N-type wells include a first N-type well and a second N-type well in this order;
the first field oxide layer and the second field oxide layer are formed on the first N-type well, and the third field oxide layer and the fourth field oxide layer are formed on the second N-type well.
4. The method according to claim 3, wherein the P-type heavily doped region is formed between the second field oxide layer and the third field oxide layer, the first N-type heavily doped region is formed between the first field oxide layer and the second field oxide layer, and the second N-type heavily doped region is formed between the third field oxide layer and the fourth field oxide layer.
5. The method as claimed in any one of claims 1 to 4, wherein the forming of the P-type heavily doped region in the upper region, the forming of the first N-type heavily doped region in the first N-type well, and the forming of the second N-type heavily doped region in the second N-type well further comprise:
and forming metal electrodes on the P-type heavily doped region, the first N-type heavily doped region and the second N-type heavily doped region.
6. The method according to claim 5, wherein before forming the field oxide layer on the substrate, the method further comprises:
and carrying out N-type ion implantation on the substrate to form the deep N-type well.
7. The method of claim 6, wherein forming at least two N-wells in the deep N-well comprises:
covering a second target area with a light resistance through a photoetching process, wherein the second target area is the other area on the substrate except the areas corresponding to the at least two N-type wells;
carrying out N-type ion implantation on the exposed area on the substrate to form at least two N-type wells;
and removing the photoresist.
8. The method of claim 7, wherein forming a first P-well and a second P-well on an outer periphery side of the deep N-well comprises:
covering a photoresist in a third target area through a photoetching process, wherein the third target area is the other area on the substrate except the area corresponding to the first P-type well and the second P-type well;
performing P-type ion implantation on the exposed region on the substrate to form the first P-type well and the second P-type well;
and removing the photoresist.
9. A JFET device, comprising:
the substrate is a P-type substrate, a deep N-type well is formed in the substrate, at least two N-type wells and a PTOP are formed in the deep N-type well, a first P-type well and a second P-type well are formed on the outer peripheral side of the deep N-type well in the substrate, the PTOP divides the deep N-type well into an upper area and a lower area, two ends of the PTOP are respectively contacted with the first P-type well and the second P-type well, and the at least two N-type wells are located in the upper area;
the field oxide layer is formed on the deep N-type well, and the bottom of the field oxide layer is covered by the deep N-type well;
the P-type heavily doped region is formed in the deep N-type well and is positioned outside the N-type well;
the first N-type heavily doped region is formed in the first N-type well;
and the second N-type heavily doped region is formed in the second N-type well.
10. The device of claim 9, wherein at least four field oxide layers are formed on the substrate, the at least four field oxide layers including, in order, a first field oxide layer, a second field oxide layer, a third field oxide layer, and a fourth field oxide layer along a length direction of a cross section of the substrate, the at least two N-type wells including, in order, a first N-type well and a second N-type well;
the first field oxide layer and the second field oxide layer are formed on the first N-type well, and the third field oxide layer and the fourth field oxide layer are formed on the second N-type well.
11. The device of claim 10, wherein the P-type heavily doped region is formed between the second and third field oxide layers, the first N-type heavily doped region is formed between the first and second field oxide layers, and the second N-type heavily doped region is formed between the third and fourth field oxide layers.
12. The device of claim 11, wherein metal electrodes are formed on the heavily P-doped region, the heavily first N-doped region, and the heavily second N-doped region.
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| US20150102391A1 (en) * | 2013-10-16 | 2015-04-16 | Analog Devices Technology | Junction field effect transistor, and method of manufacture thereof |
| TWI594334B (en) * | 2015-11-12 | 2017-08-01 | 世界先進積體電路股份有限公司 | Semiconductor device and method of manufacturing the same |
| CN110350018A (en) * | 2018-04-02 | 2019-10-18 | 世界先进积体电路股份有限公司 | Semiconductor structure and its manufacturing method |
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| US20150102391A1 (en) * | 2013-10-16 | 2015-04-16 | Analog Devices Technology | Junction field effect transistor, and method of manufacture thereof |
| TWI594334B (en) * | 2015-11-12 | 2017-08-01 | 世界先進積體電路股份有限公司 | Semiconductor device and method of manufacturing the same |
| CN110350018A (en) * | 2018-04-02 | 2019-10-18 | 世界先进积体电路股份有限公司 | Semiconductor structure and its manufacturing method |
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