CN111384943B - Flexible neuron-like circuit and pulse neural network based on same - Google Patents
Flexible neuron-like circuit and pulse neural network based on same Download PDFInfo
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Abstract
The invention belongs to the field of artificial neural networks, and discloses a flexible neuron-imitating circuit and a pulse neural network based on the same, wherein the flexible neuron-imitating circuit comprises a first thin film transistor, a first CMOS (complementary metal oxide semiconductor) phase inverter, a second CMOS phase inverter, a first bias resistor, a second bias resistor and a mutant memristor; the impulse neural network comprises an artificial synapse array and a plurality of flexible artificial neuron circuits; and one end of the simulated synapse array is used for inputting signals, the other end of the simulated synapse array is connected with a plurality of flexible simulated neuron circuits, and the simulated synapse array and the flexible simulated neuron circuits are prepared in an integrated mode. The flexible simulated neuron circuit overcomes the defects that the flexible simulated neuron circuit in the prior art is complex in structure, high in circuit power consumption and incapable of being integrated with a memristor simulated synapse array, is very simple in structure, needs few transistors, is low in power consumption, reduces production and use costs, and achieves integrated preparation of the flexible simulated neuron circuit and the simulated synapse array.
Description
Technical Field
The invention belongs to the field of artificial neural networks, and relates to a flexible neuron-like circuit and a pulse neural network based on the same.
Background
Spiking neural Networks (SNN-Spiking neural Networks) are often known as third generation artificial neural Networks. In addition to the fact that the pulse neural network simulates neurons much closer to reality, the influence of temporal information is taken into account, the idea being that a neuron in a dynamic neural network is not activated in each iteration (as in a typical multi-layered perceptron network), but only when its membrane potential reaches a certain value. When a neuron is activated, it generates a signal that is transmitted to other neurons to raise or lower its membrane potential. In a spiking neural network, the current activation level of a neuron (modeled as some sort of differential equation) is generally considered to be the current state, and an input pulse causes the current value to rise, last for a period of time, and then gradually decay. Many coding schemes have emerged that interpret these output pulse sequences as a practical number, taking into account both pulse frequency and pulse interval time. By means of research of neuroscience, people can accurately establish a neural network model based on pulse generation time, the novel neural network adopts pulse coding (spike coding), and the novel neural network can obtain more information and stronger computing power by obtaining the accurate pulse generation time.
However, the existing hardware pulse neural network (SNN) with different functions realized by the simulated synapse device array based on the graded memristor adopts the functions of information integration, feedback, nerve pulse generation and output and the like of the simulated neurons of the CMOS FET circuit, which results in complex structure of the flexible simulated neuron circuit, numerous required transistors, high power consumption, and easy pollution of metal elements commonly used for memristors, such as W, Ti, Ag, Nb and the like, to the CMOS FET in the manufacturing process, so the flexible simulated neuron circuit and the simulated synapse array of the memristor are manufactured separately, and integrated preparation cannot be realized.
Disclosure of Invention
The invention aims to overcome the defects that a flexible simulated neuron circuit in the prior art is complex in structure, high in circuit power consumption and incapable of being integrated with a memristor simulated synapse array for preparation, and provides the flexible simulated neuron circuit and a pulse neural network system based on the same.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
on one hand, the invention discloses a flexible neuron-imitating circuit which comprises a first thin film transistor, a first CMOS inverter, a second CMOS inverter, a first bias resistor, a second bias resistor and a mutant memristor, wherein the first thin film transistor is connected with the first CMOS inverter; one end of the first bias resistor is grounded, the other end of the first bias resistor serves as the input end of the flexible neuron-imitating circuit and is connected with one end of the mutant memristor, the other end of the mutant memristor is connected with the input end of the first CMOS phase inverter, the output end of the first CMOS phase inverter is connected with the input end of the second CMOS phase inverter, and the output end of the second CMOS phase inverter serves as the output end of the flexible neuron-imitating circuit; the drain electrode of the first thin film transistor is connected with a connecting wire of the first bias resistor and the mutant memristor, the source electrode of the first thin film transistor is connected with negative working voltage, and the grid electrode of the first thin film transistor is connected with the output end of the second CMOS inverter to form a feedback loop.
The flexible neuron-like circuit is further improved in that:
the first CMOS inverter and the second CMOS inverter have the same structure, the first CMOS inverter comprises a second thin film transistor and a third thin film transistor, the grid electrode of the second thin film transistor and the grid electrode of the third thin film transistor are interconnected to serve as the input end of the first CMOS inverter, the drain electrode of the second thin film transistor and the drain electrode of the third thin film transistor are interconnected to serve as the output end of the first CMOS inverter, the source electrode of the second thin film transistor is connected with positive working voltage, and the source electrode of the third thin film transistor is grounded.
The first thin film transistor and the third thin film transistor are N-type thin film transistors, and the second thin film transistor is a P-type thin film transistor.
The channel material of the P-type thin film transistor is pentacene or SnO, and the channel material of the N-type thin film transistor is F18CuPC or IGZO; and gate dielectric materials of the P-type thin film transistor and the N-type thin film transistor are both HfLaO.
The resistance change layer of the mutant memristor is made of lanthanum-based oxide, and the top electrode is made of Mg or Ag.
In another aspect of the invention, a spiking neural network comprises an artificial synapse array and a plurality of flexible artificial neuron circuits; and one end of the simulated synapse array is used for inputting signals, the other end of the simulated synapse array is connected with a plurality of flexible simulated neuron circuits, and the simulated synapse array and the flexible simulated neuron circuits are prepared in an integrated mode.
The impulse neural network of the invention is further improved in that:
the simulated synapse array comprises a plurality of graded memristors, a plurality of first connecting wires and a plurality of second connecting wires; the gradual-change type memristors form a gradual-change type memristor array, each gradual-change type memristor comprises a first connecting end and a second connecting end, each row of the gradual-change type memristor array comprises n gradual-change type memristors, the first connecting ends of the n gradual-change type memristors are connected with each other through first connecting wires, each column comprises m gradual-change type memristors, and the second connecting ends of the m gradual-change type memristors are connected with each other through second connecting wires; wherein m and n are integers more than 0; one end of each first connecting line is used as an input end to carry out signal input, one end of each second connecting line is used as an output end of the simulated synapse array to be connected with the input end of the flexible simulated neuron circuit, and the plurality of second connecting lines are arranged in one-to-one correspondence with the plurality of flexible simulated neuron circuits.
The resistance change layer of the gradient memristor is made of Nb, Ta or Ti doped lanthanum-based oxide.
Compared with the prior art, the invention has the following beneficial effects:
the flexible neuron-imitating circuit of the invention is provided with the mutant memristor, the resistance of the mutant memristor changes suddenly when reaching a certain threshold value along with the accumulation of the action of the current passing amount, similar to the change process of the neuron membrane potential under the continuous stimulation of the nerve pulse, thereby having the function of simulating the information integration of neurons, then two CMOS inverters are cascaded to realize the generation and output of nerve pulse, the feedback of the neuron is realized by a thin film transistor, the problems that when the functions of information integration, feedback, nerve pulse generation and output and the like of the neuron are simulated by adopting a CMOS FET in the existing research are solved, the flexible neuron-imitating circuit has the advantages of simple structure, few required transistors and low power consumption of the whole flexible neuron-imitating circuit, thereby reducing the production and use cost. Meanwhile, the existing CMOS FET needs higher preparation process temperature and has complex process, so that the existing CMOS FET is not suitable for a flexible substrate; however, the mutant memristor and the thin film transistor adopted by the invention are both suitable for being prepared on the flexible substrate, so that the flexible neuron-like circuit can be prepared on the flexible substrate.
Furthermore, the channel material of the P-type thin film transistor is pentacene or SnO, and the channel material of the N-type thin film transistor is F18CuPC or IGZO; the gate dielectric materials of the P-type thin film transistor and the N-type thin film transistor are both made of high-k material HfLaO, so that the low threshold voltage and the high carrier mobility can be obtained, and the power consumption of the system can be reduced
Furthermore, a resistance change layer of the mutant memristor is made of lanthanum-based oxide with a large amount of oxygen ions, a top electrode is made of Mg or Ag, the oxygen ions move to the top electrode under the action of positive bias pulses to oxidize the top electrode, and after the oxygen ions are accumulated to a certain degree, the device is suddenly changed from a low resistance state to a high resistance state to form the mutant memristor. The lanthanum-based oxide is used as the resistance change layer, so that the integration with a thin film transistor device is facilitated, and the cross contamination can be avoided.
The pulse neural network is realized by combining the flexible simulated neuron circuit with the simulated synapse array, the problem that a CMOS FET cannot be integrated with the simulated synapse array due to the fact that the preparation process is complex, the CMOS FET is easily polluted by metal elements such as W, Ti, Ag and Nb which are commonly used for the graded memristor in the manufacturing process, and the thin film transistor adopted by the flexible simulated neuron circuit has the advantages of being simple in device structure, low in preparation cost, easy to prepare in a large area, compatible in the preparation process and the graded memristor and the like, and the pulse neural network with low power consumption is obtained by being integrated with the simulated synapse array.
Furthermore, a resistance change layer of the gradient memristor is made of Nb, Ta or Ti doped lanthanum-based oxide, conductive filaments are formed in the resistance change layer by Nb, Ta or Ti ions under the driving of an electric field, the shapes of the conductive filaments can be regulated and controlled by external voltage, the gradient memristor is formed, and the materials are used for facilitating integration and avoiding cross contamination of the gradient memristor.
Drawings
FIG. 1 is a schematic diagram of a flexible neuron-like circuit of the present invention;
FIG. 2 is a schematic diagram of a spiking neural network according to the present invention;
FIG. 3 is a schematic diagram of an equivalent structure of the spiking neural network of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the accompanying drawings:
referring to fig. 1, the flexible neuron-like circuit of the invention is prepared by using a mutant memristor and a thin film transistor, and comprises a first thin film transistor T1, a first CMOS inverter, a second CMOS inverter, and a first bias resistor RGA second bias resistor RLAnd mutant memristor RA。
A first bias resistor RGOne end of the resistor is grounded, and the other end of the resistor is connected with a mutant memristor RAIs connected to the mutant memristor RAThe other end of the first CMOS phase inverter is connected with the input end of the first CMOS phase inverter, the output end of the first CMOS phase inverter is connected with the input end of the second CMOS phase inverter, and the output end of the second CMOS phase inverter is used as the output end of the flexible neuron-imitating circuit; the drain of the first thin film transistor T1 is connected with a first bias resistor RGAnd mutant memristor RAThe source of the first thin film transistor T1 is connected to the negative working voltage, the gate of the first thin film transistor T1 and the second CMOS inverterThe output end of the feedback loop is connected with the first thin film transistor T1 which is an N-type thin film transistor.
The first CMOS inverter includes a second thin film transistor T2 and a third thin film transistor T3, a gate of the second thin film transistor T2 is interconnected with a gate of the third thin film transistor T3 as an input terminal of the first CMOS inverter, a drain of the second thin film transistor T2 is interconnected with a drain of the third thin film transistor T3 as an output terminal of the first CMOS inverter, a source of the second thin film transistor T2 is connected to a positive operating voltage, a source of the third thin film transistor T3 is grounded, the second thin film transistor T2 is a P-type thin film transistor, the third thin film transistor T3 is an N-type thin film transistor, one P-type thin film transistor is used as a load device, and one N-type thin film transistor is used as a drive device.
The second CMOS inverter includes a fourth thin film transistor T4 and a fifth thin film transistor T5, a gate of the fourth thin film transistor T4 is interconnected with a gate of the fifth thin film transistor T5 as an input terminal of the second CMOS inverter, a drain of the fourth thin film transistor T4 is interconnected with a drain of the fifth thin film transistor T5 as an output terminal of the second CMOS inverter, a source of the fourth thin film transistor T4 is connected to a positive operating voltage, a source of the fifth thin film transistor T5 is grounded, the fourth thin film transistor T4 is a P-type thin film transistor, the fifth thin film transistor T5 is an N-type thin film transistor, one P-type thin film transistor is used as a load device, and one N-type thin film transistor is used as a drive device.
Wherein, the mutant memristor RAThe resistance change layer is made of lanthanum-based oxide, and the top electrode is made of Mg or Ag; the channel material of the P-type thin film transistor is pentacene or SnO, and the channel material of the N-type thin film transistor is F18CuPC or IGZO; both the P-type thin film transistor and the N-type thin film transistor adopt HfLaO as gate dielectrics.
Mutant memristors R in flexible neuron-like circuitsAThe resistance of the analog neuron can be suddenly changed when reaching a certain threshold value along with the accumulation of the action of the current passing amount, and the change process is similar to the change process of the neuron membrane potential under the continuous stimulation of the nerve pulse, so that the analog neuron has the function of simulating the information integration of neurons, and then two CMOS phase invertersThe cascade connection realizes the generation and output of nerve pulse, and the feedback of the neuron can be realized through an N-type thin film transistor. In particular, by means of a first biasing resistor RGConverting the input current signal into a voltage signal, and inputting the voltage signal into the mutant memristor RAEnabling the mutant memristor R according to the magnitude of the voltage valueAThe resistance of the memristor is correspondingly changed, and the resistance is changed through the mutant memristor RAThe abrupt change of the resistance value of the resistor integrates the voltage signal when R isAWhen the resistance value of (1) is changed from a high resistance state to a low resistance state, RLThe upper end level is changed into a high level, and then the high level is output to a two-stage cascaded CMOS inverter to process the integrated voltage signal, and the output high level working voltage is generated in a pulse mode; the output end of the two-stage cascaded CMOS inverter is connected with the gate of the first thin film transistor T1 to form negative feedback, and the negative feedback acts on the first bias resistor RGThe generated voltage signal forms an output pulse at the output end of the two-stage cascaded CMOS inverter.
Referring to fig. 2, the spiking neural network based on the flexible neuron-like circuit of the present invention includes a synapse-like array and a plurality of flexible neuron-like circuits, wherein one end of the synapse-like array is used for signal input, and the other end of the synapse-like array is connected to the flexible neuron-like circuits, and the flexible neuron-like circuits are represented by pentagons in the figure. The simulated synapse array is prepared by using a graded memristor, adopts a cross matrix structure and is used for identifying input signals, different current signals are generated by the simulated synapse array according to different input signals and are transmitted to the flexible simulated neuron circuit, and different pulse signals are generated by the flexible simulated neuron circuit according to received signals and are output.
Specifically, the simulated synapse array comprises a plurality of graded memristors, a plurality of first connecting wires and a plurality of second connecting wires; the gradual-change type memristors form a gradual-change type memristor array, each gradual-change type memristor in the gradual-change type memristors comprises a first connecting end and a second connecting end, the first connecting wires are transversely arranged, the second connecting wires are longitudinally arranged to form a cross matrix structure, each row of the gradual-change type memristor array comprises n gradual-change type memristors, the first connecting ends of the n gradual-change type memristors are connected with each other through the first connecting wires, each column comprises m gradual-change type memristors, and the second connecting ends of the m gradual-change type memristors are connected with each other through the second connecting wires; wherein m and n are integers more than 0; one end of each first connecting line is used as an input end to carry out signal input, one end of each second connecting line is used as an output end of the simulated synapse array to be connected with an input end of one flexible simulated neuron circuit, and a generated current signal is transmitted to the corresponding flexible simulated neuron circuit.
The resistive layer of the graded memristor in the synapse-like array is made of lanthanum-based oxide doped with Nb, Ta or Ti and the like.
The working process of the invention is further illustrated below with reference to examples:
for the whole impulse neural network, in the first step, the content to be identified is encoded, the number of inputs is determined according to the accuracy requirement, and taking the image of identifying the content as the handwritten figures 0 to 9 as an example, the number of outputs can be determined to be 10, specifically y1To y10From this, the size of the entire simulated synapse array may be determined. And secondly, training a neural network on the image of the handwritten digit through corresponding software to obtain a weight value of the whole simulated synapse array, wherein the weight value corresponds to the resistance value of the corresponding hardware simulated synapse array. And thirdly, obtaining a setting pulse of each gradual-change type memristor according to the voltage-resistance relation of the gradual-change type memristor, and setting each gradual-change type memristor to be a corresponding resistance value. Fourthly, inputting the image to obtain an output result and obtaining y according to the obtained y1To y10Determining the number in the input image, e.g. y1If the voltage value is high and the other output voltage values are low, the input number is 0, and the other conditions are similar, so that the identification of the handwritten numbers 0 to 9 is realized.
In which y is obtained1To y10The principle of the pulse of (a) is explained in detail below, in y1For example, the other cases are similar. Generating y1The neuron is connected with a plurality of synapses, namely a flexible neuron-imitating circuit is connected with a plurality of gradient type memristors, each gradient type memristor is connected with an input, and the circuit is simplifiedSee fig. 3. Firstly, an input voltage is converted into a current signal through a graded memristor and then is converted into a current signal through a first bias resistor RGThe voltage is converted into a voltage signal, namely the voltage at the point A, and then the voltage is input into the flexible neuron-imitating circuit. Second, during the initial work, the mutant memristor RAIn a high resistance state, the second bias resistor RLThe upper level is a low level, and the output is a low level after the action of the two cascaded CMOS inverters, and at the moment, the first thin film transistor T1 is in a cut-off state; when the voltage at the A point is higher than the voltage of the mutant memristor RAAt the threshold voltage of (3), the mutant memristor RATo a low resistance state, the second bias resistor RLThe high level is output after the action of the two cascaded CMOS inverters, the first thin film transistor T1 connected with the output end is turned on through feedback, and the negative working voltage-VDD is loaded to the mutant memristor RAIn the above, the mutant memristor RAAnd changes back to the high impedance state, at which point the output goes low, thereby generating a pulse.
Compared with the existing research in which CMOS FETs are adopted to simulate the functions of information integration, feedback, nerve pulse generation and output and the like of neurons, the flexible neuron-imitating circuit and the pulse neural network based on the flexible neuron-imitating circuit bring the defects of complex circuit structure and numerous required transistors, and the flexible neuron-imitating circuit in the scheme has the advantages of very simple structure, few required transistors and low power consumption; the CMOS FET is complex in preparation process, is very easily polluted by W, Ti, Ag, Nb and other metal elements commonly used for memristors in the manufacturing process, cannot be integrally prepared with the simulated synapse array, and the thin film transistor adopted in the invention has the advantages of simple device structure, low preparation cost, easiness in large-area preparation, compatibility of the preparation process and the graded memristor and the like, and can be integrally prepared with the simulated synapse array. Based on the mutant memristor and the thin film transistor, a flexible simulated neuron circuit with low cost, simple circuit structure and low power consumption can be manufactured, and then the flexible simulated neuron circuit and the simulated synapse array are integrated to prepare the low-power-consumption pulse neural network.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (4)
1. A flexible neuron-imitating circuit is characterized by comprising a first thin film transistor, a first CMOS inverter, a second CMOS inverter, a first bias resistor, a second bias resistor and a mutant memristor;
one end of the first bias resistor is grounded, the other end of the first bias resistor serves as the input end of the flexible neuron-imitating circuit and is connected with one end of the mutant memristor, the other end of the mutant memristor is connected with the input end of the first CMOS phase inverter, the output end of the first CMOS phase inverter is connected with the input end of the second CMOS phase inverter, and the output end of the second CMOS phase inverter serves as the output end of the flexible neuron-imitating circuit; the drain electrode of the first thin film transistor is connected with a connecting wire of the first bias resistor and the mutant memristor, the source electrode of the first thin film transistor is connected with negative working voltage, and the grid electrode of the first thin film transistor is connected with the output end of the second CMOS inverter to form a feedback loop;
the first CMOS inverter and the second CMOS inverter have the same structure, the first CMOS inverter comprises a second thin film transistor and a third thin film transistor, the grid electrode of the second thin film transistor and the grid electrode of the third thin film transistor are interconnected to be used as the input end of the first CMOS inverter, the drain electrode of the second thin film transistor and the drain electrode of the third thin film transistor are interconnected to be used as the output end of the first CMOS inverter, the source electrode of the second thin film transistor is connected with positive working voltage, and the source electrode of the third thin film transistor is grounded;
the first thin film transistor and the third thin film transistor are N-type thin film transistors, and the second thin film transistor is a P-type thin film transistor;
the channel material of the P-type thin film transistor is pentacene or SnO, and the channel material of the N-type thin film transistor is F18CuPC or IGZO; gate dielectric for P-type and N-type thin film transistorsThe materials are all HfLaO;
the resistance change layer of the mutant memristor is made of lanthanum-based oxide, and the top electrode is made of Mg or Ag.
2. A spiking neural network, comprising an artificial synapse array and a number of flexible artificial neuron circuits of claim 1; and one end of the simulated synapse array is used for inputting signals, the other end of the simulated synapse array is connected with a plurality of flexible simulated neuron circuits, and the simulated synapse array and the flexible simulated neuron circuits are prepared in an integrated mode.
3. The spiking neural network of claim 2, wherein the simulated synapse array comprises graded memristors, first connection lines, and second connection lines;
the gradual-change type memristors form a gradual-change type memristor array, each gradual-change type memristor comprises a first connecting end and a second connecting end, each row of the gradual-change type memristor array comprises n gradual-change type memristors, the first connecting ends of the n gradual-change type memristors are connected with each other through first connecting wires, each column comprises m gradual-change type memristors, and the second connecting ends of the m gradual-change type memristors are connected with each other through second connecting wires; wherein m and n are integers more than 0; one end of each first connecting line is used as an input end to carry out signal input, one end of each second connecting line is used as an output end of the simulated synapse array to be connected with the input end of the flexible simulated neuron circuit, and the plurality of second connecting lines are arranged in one-to-one correspondence with the plurality of flexible simulated neuron circuits.
4. The spiking neural network of claim 3, wherein the resistive layer of the graded memristor is fabricated using Nb, Ta, or Ti doped lanthanum-based oxides.
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