CN111359910A

CN111359910A - Integrated circuit product testing method

Info

Publication number: CN111359910A
Application number: CN202010185424.5A
Authority: CN
Inventors: 吴晨; 柏艳
Original assignee: Suzhou ASEN Semiconductors Co Ltd
Current assignee: Riyuexin Semiconductor Suzhou Co ltd
Priority date: 2020-03-17
Filing date: 2020-03-17
Publication date: 2020-07-03
Anticipated expiration: 2040-03-17
Also published as: CN111359910B

Abstract

The application relates to an integrated circuit product testing method. Specifically, the present application provides a method for testing an integrated circuit product, comprising: providing a number of integrated circuit products to a test station; performing an electrical test on the plurality of integrated circuit products at the test station; performing an online quality assurance test on the integrated circuit products passing the electrical test in the plurality of integrated circuit products at the test station; and sampling the integrated circuit products which pass the electrical property test and the online quality assurance test in the plurality of integrated circuit products at the test station.

Description

Integrated circuit product testing method

Technical Field

The present application relates generally to integrated circuit product testing methods and, more particularly, to methods for 100% on-line quality assurance testing of integrated circuit products.

Background

Within the semiconductor industry, it is often desirable to perform various tests on integrated circuit products, such as integrated circuit chips, that have already been manufactured. When testing a common integrated circuit product, it is usually only necessary to perform an electrical test (hereinafter referred to as "100% electrical test") and a sampling test on each of all the integrated circuit products to be tested to meet the test requirements. For example, a 100% electrical test is first performed on an integrated circuit product at a test station, and then the integrated circuit product that passes the electrical test is immediately sampled at the same test station according to a sampling test program, and if so, the sampling test is immediately performed on the integrated circuit product.

However, in addition to the above-mentioned general integrated circuit products, there are special integrated circuit products that have higher requirements for reliability. For example, in transmitting data and power between high and low voltage circuits, digital isolation integrated circuit products may be used to enable the transmission of data and power between high and low voltage circuits while preventing dangerous direct current or uncontrolled transient currents from flowing between the high and low voltage circuits. The special application scenarios set forth above place high reliability requirements on digital isolated integrated circuit products. Accordingly, it is necessary for digital isolated integrated circuit products to undergo more rigorous testing including quality assurance testing (hereinafter "quality assurance testing") to ensure that they meet high reliability requirements.

For various special integrated circuit products including the above-mentioned digital isolation integrated circuit products, it is generally desired to be able to perform 100% electrical test, on-line quality assurance test (hereinafter referred to as "100% on-line quality assurance test") performed on each of all the integrated circuit products to be tested, and sampling test at one time in the same test station. However, existing test systems, including testers and sorters, for example, have not been able to meet the above test requirements.

In view of the above, there is a strong need in the art to provide improved solutions to the above-mentioned problems.

Disclosure of Invention

Embodiments of the present application seek to address, at least in part, at least one of the problems presented in the related art by providing a method for integrated circuit product testing.

In one embodiment, the present application provides a method for testing an integrated circuit product, comprising: providing a number of integrated circuit products to a test station; performing an electrical test on the plurality of integrated circuit products at the test station; performing an online quality assurance test on the integrated circuit products passing the electrical test in the plurality of integrated circuit products at the test station; and sampling the integrated circuit products which pass the electrical property test and the online quality assurance test in the plurality of integrated circuit products at the test station.

According to an embodiment of the present application, it further comprises performing appearance detection on the integrated circuit products of the number of integrated circuit products that pass the electrical test and the warranty test but are not sampled.

According to an embodiment of the present application, wherein the appearance detection includes at least one of a print detection and a pin face detection.

According to an embodiment of the application, further comprising taping packaging of ones of the number of integrated circuit products that pass the appearance detection.

According to an embodiment of the present application, it further comprises providing the integrated circuit products that fail the electrical test of the integrated circuit products to a waste material pipe device.

According to an embodiment of the present application, it further comprises providing the integrated circuit products of the number of integrated circuit products that pass the electrical test but do not pass the in-line quality assurance test to a quality assurance test waste bin.

According to the embodiment of the application, the method further comprises the step of providing the integrated circuit products which pass the electrical test and the online quality assurance test and are selected by the sampling to a quality assurance test waste material pipe.

According to an embodiment of the present application, further comprising providing the integrated circuit products subjected to the in-line quality assurance test to a quality assurance test waste bin.

According to an embodiment of the present application, providing the integrated circuit products subjected to the in-line quality assurance test to a quality assurance test waste bin includes adjusting or setting one or more test parameters to disable the integrated circuit products from passing the in-line quality assurance test.

According to an embodiment of the present application, further comprising providing the integrated circuit products in the warranty test waste bin to the test station for acceptable quality level testing.

According to an embodiment of the application, wherein the acceptable quality level test is the same as the test content of the online quality assurance test.

According to an embodiment of the present application, further comprising providing the integrated circuit product that passes the acceptable quality level test to a quality assurance supply tube.

According to an embodiment of the present application, further comprising providing the integrated circuit products that fail the acceptable quality level test to a quality assurance waste pipe for further analysis.

According to an embodiment of the application, wherein the quality assurance waste pipe is coupled to the waste pipe arrangement via a quality assurance test waste container.

According to an embodiment of the present application, wherein the further analysis comprises analyzing a reason why the integrated circuit product provided to the quality assurance waste tube failed the acceptable quality level test.

Additional aspects and advantages of embodiments of the present application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of the present application.

Drawings

Drawings necessary for describing embodiments of the present application or the prior art will be briefly described below in order to describe the embodiments of the present application. It is to be understood that the drawings in the following description are only some of the embodiments of the present application. It will be apparent to those skilled in the art that other embodiments of the drawings can be obtained from the structures illustrated in these drawings without the need for inventive work.

Fig. 1A shows a top view of the overall structure of a turret type sorter according to the prior art.

FIG. 1B shows a flow chart for integrated circuit product testing based on a tester and turret sorter 100 shown in FIG. 1A.

FIG. 2 shows a schematic diagram of the operation of connecting a tester to a test station of a turret sorter.

FIG. 3 shows a schematic diagram of a 100% on-line quality assurance test of an integrated circuit product based on a multi-tester configuration according to the prior art.

FIG. 4 shows a flow chart for 100% in-line quality assurance testing of an integrated circuit product based on the multi-tester configuration of FIG. 3.

FIG. 5 shows a flow diagram for a prior art human-assisted 100% in-line quality assurance test of integrated circuit products based on a single tester configuration.

FIG. 6 shows a test flow according to an embodiment of the present application.

Fig. 7 shows a waste pipe arrangement according to an embodiment of the application.

Figure 8 shows the results of a warranty test according to an embodiment of the present application.

Detailed Description

In order that the spirit of the application may be better understood, some preferred embodiments of the application are described below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

In this application, unless specified or limited otherwise, when a first feature is located "on" or "under" a second feature in a structure, the structure may comprise an embodiment in which the first feature is in direct contact with the second feature, and may comprise another embodiment in which the first feature is not in direct contact with the second feature, but is in contact with an additional feature formed therebetween. Furthermore, when a first feature is located "on," over "or" on top of "a second feature, it can include embodiments in which the first feature is located" on, "over" or "on top" the second feature, directly or obliquely, or merely represents that the height of the first feature is higher than that of the second feature; when a first feature is located "under," under "or" at the bottom of "a second feature, embodiments may be included in which the first feature is located" under, "under" or "at the bottom of" the second feature, either directly or obliquely, or simply represents that the height of the first feature is lower than the height of the second feature. Directional phrases used in this application, such as, for example, upper, lower, left, right, front, back, side, horizontal, lateral, vertical, and the like, refer only to the orientation of the appended drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting.

Various embodiments of the present application are discussed in detail below. While specific implementations are discussed, it should be understood that these implementations are for illustrative purposes only. One skilled in the relevant art will recognize that other components and configurations may be used without departing from the spirit and scope of the present application.

Fig. 1A shows a top view of the overall structure of a turret type sorter according to the prior art. The conventional turret-type sorter 100 includes a feeding device 101, a testing station 102, a printing detection device 103, a pin face detection device 104, a waste pipe device 105, and a braid sealing device 106. In the prior art, the feeding device 101 is used to feed or supply the ic products to be tested to the test stations 102 of the turret-type handler 100. The test stations 102 are used to load integrated circuit products that are subjected to 100% electrical testing, sampling and sampling testing, and the number of test stations 102 may be four as is common or any other positive integer. The print detection device 103 and the lead surface detection device 104 are used for appearance detection of the print on the surface of the integrated circuit product and the lead surface, respectively. The braid sealing apparatus 106 is used to braid package the integrated circuit products that pass each test. The waste pipe 105 is used for sorting and receiving any of the integrated circuit products which fail the test. The conventional turret sorter 100 shown in fig. 1A may be connected to a tester to jointly test an ic product under test.

FIG. 1B shows a flow chart for integrated circuit product testing based on a tester and turret sorter 100 shown in FIG. 1A. In step 111, the feeding device 101 in the turret-type handler 100 feeds or provides the ic product to be tested to the testing station 102, and the tester loads the electrical test program and the on-line sample assurance test program. In step 112, the tester performs 100% electrical testing and sampling of the integrated circuit product via the test station 102. The integrated circuit products that pass the 100% electrical test but are not selected by sampling in step 112 are directly subjected to appearance inspection performed by turret sorter 100 in step 114, wherein the appearance inspection may include print inspection and lead face inspection, and the print inspection and the lead face inspection are performed by print inspection apparatus 103 and lead face inspection apparatus 104 shown in fig. 1A, respectively. The selected integrated circuit products that pass the electrical test in step 112 and are sampled will be subjected to an online sample assurance test performed thereon by the turret sorter 100 in step 113. The integrated circuit products that pass the online sample assurance test in step 113 will receive appearance detections performed thereon by the turret sorter 100 in step 114, wherein the appearance detections may also include print detections and pin face detections, and the print detections and the pin face detections may also be performed by the print detection device 103 and the pin face detection device 104 shown in fig. 1A, respectively. The integrated circuit product visually inspected by step 114 will be taped by tape sealing apparatus 106 of fig. 1A in step 115. The ic products that fail any of the tests in

steps

112, 113, and 114 are transferred to step 116 where they are fed from turret sorter 100 into waste pipe 105.

FIG. 2 shows a schematic diagram of the operation of connecting a tester to a test station of a turret sorter. The tester 220 may be coupled to and communicate with the turret sorter 210 via a communication line 219. When a test is required, the handler nozzle (Contact blade)212 of the turret-type handler 210 pushes the ic product to be tested down into the test Socket 213 of the test station under the control of the push-down rudder 211(Contact drawer), so that the PINs of the ic product and the corresponding test Probes (PINs) in the test Socket 213 are connected to each other, and the ic product is connected to the tester 220 through the test Socket 213, the Device Under Test (DUT) board 214, the test load board (Loadboard)215, the test head 216, the communication line 217, and other hardware, and sends a test start signal to the tester 220 through the communication line 219. In response to the test initiation signal, the tester 220 initiates a test procedure and controls the test head 216 via the test load board 215 and the device under test board 214 to perform a test on the integrated circuit product 218 under test in the test fixture 213 via the communication line 217. After the designated test items are completed, the tester 220 obtains the test results and sends a test end signal to the turret-type sorter 210. The turret sorter 210 places the tested ic products at corresponding locations on the turret sorter 210 according to a predetermined sorting procedure, thereby completing the testing.

The prior art test platform shown in fig. 1A or fig. 2 has a single tester configuration. However, on the test platform, the test flow shown in fig. 1B can only achieve 100% electrical test and on-line sample guarantee test for a common integrated circuit product in the same test station, but cannot achieve 100% electrical test, 100% on-line sample guarantee test and sample test for an integrated circuit product in one step in the same test station, and thus cannot meet the test requirements for special integrated circuit products with high reliability requirements, such as digital isolation integrated circuit products. Taking an MS7000 testing machine commonly used in the art as an example, the existing configuration of the testing machine cannot support 100% online quality assurance testing, because it can only set one sample from every 100 integrated circuit products for online sampling quality assurance testing, and it is more difficult to realize quality assurance testing by sample size (by sample size).

In order to perform quality assurance testing on all integrated circuit products under test based on 100% electrical testing and sampling testing, the following solutions exist in the prior art, for example.

FIG. 3 is a schematic diagram of a 100% in-line quality assurance test of an integrated circuit product based on a multi-tester configuration according to the prior art to meet test requirements for a particular integrated circuit product having high reliability requirements. Figure 3 shows the addition of a single tester 306 to a single tester 305 to form a multi-tester configuration to perform parallel testing. Tester 305 is connected to test

stations

301 and 302 on sorter turret 300 and performs 100% electrical testing and on-line sample assurance testing on the integrated circuit products at

test stations

301 and 302, and tester 306 is connected to test

stations

303 and 304 on sorter turret 300 and performs 100% on-line quality assurance testing on the integrated circuit products at

test stations

303 and 304. Prior art multi-tester configurations also allow series testing of integrated circuit products at test stations.

FIG. 4 shows a flow chart for 100% in-line quality assurance testing of an integrated circuit product based on the multi-tester configuration of FIG. 3. In step 401, the tester loads a test program and the feeder loads or provides to the

test stations

301, 302, 303, 304 of the sorter. In step 402, tester 305 performs electrical tests and on-line sample assurance tests on the integrated circuit products at

test stations

301 and 302, while tester 306 performs 100% on-line quality assurance tests on the integrated circuit products at

test stations

303 and 304. In step 403, the sorting machine further performs appearance inspection, which may include printing and pin face inspection, on the integrated circuit products that pass the electrical test, the on-line sample quality assurance test, and the 100% on-line quality assurance test. In step 404, the braid sealing apparatus of the sorter performs braid packaging of the integrated circuit product passing the appearance inspection. The ic products that fail any of

steps

402, 403 are transferred to step 405 where they are fed by a sorter into a waste pipe assembly.

However, the prior art shown in fig. 3 and 4 disadvantageously occupies a work site and significantly increases test costs due to the need to add at least one additional tester.

FIG. 5 shows a flow diagram for a prior art human-assisted 100% in-line quality assurance test of integrated circuit products based on a single tester configuration. As an alternative to the prior art shown in fig. 3 and 4, the prior art shown in fig. 5 does not employ a multi-tester configuration, but rather a single tester configuration combined with manual assistance to meet the test requirements for a particular integrated circuit product with high reliability requirements. In step 501, a test program is loaded by a tester and a feeder is loaded or provided to a test station of a handler. In step 502, the tester performs 100% electrical testing and on-line sample assurance testing on the integrated circuit products at the test stations. In step 503, the sorter performs appearance inspection on the integrated circuit products that pass the 100% electrical test and the on-line sample assurance test. In step 504, the taping and sealing device of the sorter performs taping and packaging of the integrated circuit products passing the appearance inspection. In step 505, the operator unwraps the taped integrated circuit product and performs a 100% in-line quality assurance test on the unwrapped integrated circuit product. In step 506, the sorter performs a visual inspection of the integrated circuit products that pass the 100% on-line warranty test. In step 507, the braid sealing module performs braid packaging on the integrated circuit products that pass the 100% online quality assurance test and pass the appearance inspection. The ic products that fail any of

steps

502, 503, 505, 506 are diverted to step 508 where they are fed by a sorter into a waste pipe assembly.

Although the prior art shown in fig. 5 avoids occupying space and increasing equipment cost, the appearance test needs to be performed twice, and the strip removing operation in step 505 thereof has many adverse effects. For example, to further perform the necessary 100% in-line quality assurance testing, it is also necessary for an operator or associated equipment to perform a taping operation on the integrated circuit products that have been completed and thus are well enclosed within the tape to release the integrated circuit products within the tape. This operation will inevitably cause the injury to the integrated circuit product to very easily appear losing the material, compounding, carrying and covering tape waste etc. phenomenon, still can influence the yield of product simultaneously and lead to the cost-push.

FIG. 6 shows a test flow according to an embodiment of the present application. The test flow begins at step 600 where a feeding device feeds an integrated circuit product to be tested to a test station of a handler. In step 601, the tester performs program loading. In some embodiments, the loaded programs may include 100% electrical tests, 100% in-line warranty tests, and sampling programs, with the 100% in-line warranty test program being embedded into an existing 100% electrical test program. A quality protection waste material pipe and a corresponding quality protection test waste container can be additionally arranged in a waste material pipe device of the existing sorting machine, and the quality protection waste material pipe is coupled to the waste material pipe device through the quality protection test waste container. After the program load is complete, testing of the integrated circuit product at the test station is initiated in step 602. In step 603, the tester performs a 100% electrical test on the integrated circuit product at the test station. The ic products failing the 100% electrical test in step 603 are transferred to step 604 and sent to a waste material pipe device by a sorting machine. In step 605, the tester performs a 100% in-line quality assurance test on the integrated circuit products that pass the 100% electrical test at the same test station. The ic products that fail the 100% in-line qualification test in step 605 are fed from the sorter into a qualification test reject bin in step 607. In step 606, the tester then samples the integrated circuit products that pass the 100% in-line warranty test at the same test station. The selected integrated circuit products sampled at 606 are fed by the sorter into a quality assurance test reject line at 607. The non-sampled selected integrated circuit products may be further subjected to appearance testing in step 606, and the integrated circuit products passing the appearance testing may be further taped and packaged. In step 608, the sorter repositions the IC products, which have been fed into the quality assurance test reject bin in step 607, into the feed apparatus of the sorter for the tester to perform an Acceptable Quality Level (AQL) test on the IC products. In some embodiments, the test content of the Acceptable Quality Level (AQL) test may be the same as the test content of the 100% online quality assurance test in step 605. In step 609, the sorter feeds the integrated circuit products that pass the Acceptable Quality Level (AQL) test directly into a quality assurance supply line of the sorter. The appearance test can be performed on the integrated circuit products in the quality assurance qualified tube and the integrated circuit products passing the appearance test can be packaged in a braid mode. The integrated circuit products that fail the Acceptable Quality Level (AQL) test at step 608 are transferred to a quality assurance waste line to the sorter at step 610 for further analysis. As an embodiment, the further analysis includes analyzing the specific reasons that the integrated circuit products provided to the product warranty waste pipe fail the Acceptable Quality Level (AQL) test, so as to specifically propose improvement measures, thereby further improving the test yield and reducing the cost.

In other embodiments, one or more test parameters may be adjusted or set in step 605 of the test flow shown in fig. 6, so that all the ic products under test may not pass the 100% on-line quality assurance test under the one or more test parameters, and the step may be directly shifted to step 607 to be fed into the quality assurance test waste bin by the sorter. In this manner, all integrated circuit products under test will be forced to accept Acceptable Quality Level (AQL) testing in step 608.

The embodiment shown in fig. 6 can achieve the 100% electrical test, the 100% on-line quality assurance test and the sampling operation sequentially at one time in the same test station without adding an additional tester and performing a taping-off operation on the integrated circuit product with the taped package completed, thereby meeting the test requirements for the special integrated circuit product. Also, the embodiment shown in FIG. 6 provides "double assurance" for product quality by re-performing the quality assurance test or Acceptable Quality Level (AQL) test on some or all of the integrated circuit products under test.

Fig. 7 shows a waste pipe arrangement according to an embodiment of the application. In some embodiments, the waste material pipe apparatus 700 may include the material pipes 711 to 716 and the corresponding test waste containers 701 to 706 in the existing waste material pipe apparatus, and only the quality assurance waste material pipe 717 and the corresponding quality assurance test waste container 707 are added on the basis, so that the existing waste material pipe apparatus does not need to be modified on a large scale, and the cost is saved. The warranty test waste container 707 contains integrated circuit products that fail the warranty test or are Acceptable for Quality Level (AQL) testing. However, the number of containers and pipes of the waste pipe apparatus 700 is not limited to the seven pairs shown in fig. 7. In other embodiments, the body of the warranty test waste container 707 may display "QA Fail", "warranty test failed", or words indicating similar meaning.

Figure 8 shows the results of a warranty test according to an embodiment of the present application. In some embodiments, the warranty test results may be presented in a list format within the results of the finished product test. In the embodiment shown in FIG. 8, in the row where the column SBin-HBin has values of 4-7, the values corresponding to the four testing stations Site 1, Site 2, Site 3, Site 4 of the sorting machine are all shown as 0, indicating that the 100% in-line yield test failed quantity performed on the batch of IC products is 0, i.e., the batch of IC products all passes the 100% in-line yield test. In other embodiments, the warranty test results according to embodiments of the present application may be obtained through factory existing search engine queries.

Reference throughout this specification to "an embodiment," "some embodiments," "one embodiment," "another example," "an example," "a specific example," or "some examples" means that at least one embodiment or example in this application includes a particular feature, structure, material, or characteristic described in the embodiment or example. Thus, throughout the specification, descriptions appear, for example: "in some embodiments," "in an embodiment," "in one embodiment," "in another example," "in one example," "in a particular example," or "by example," which do not necessarily refer to the same embodiment or example in this application.

The technical content and the technical features of the present application have been described in the above related embodiments, however, the above embodiments are only examples for implementing the present application. Those skilled in the art may still make various alterations and modifications based on the teachings and disclosures of this application without departing from the spirit of this application. Accordingly, the disclosed embodiments of the present application do not limit the scope of the present application. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the present application.

Claims

1. A method of testing an integrated circuit product, comprising:

providing a number of integrated circuit products to a test station;

performing an electrical test on the plurality of integrated circuit products at the test station;

performing an online quality assurance test on the integrated circuit products passing the electrical test in the plurality of integrated circuit products at the test station; and

and sampling the integrated circuit products which pass the electrical property test and the online quality assurance test in the plurality of integrated circuit products at the test station.

2. The method of claim 1, further comprising performing appearance detection on the integrated circuit products of the number of integrated circuit products that pass the electrical test and warranty test but are not sampled.

3. The method of claim 2, wherein the appearance detection includes at least one of a print detection and a pin face detection.

4. The method of claim 2, further comprising taping packaging ones of the number of integrated circuit products that pass the appearance detection.

5. The method of claim 1, further comprising providing integrated circuit products of the number of integrated circuit products that fail the electrical test to a waste pig.

6. The method of claim 1, further comprising providing integrated circuit products of the number of integrated circuit products that pass the electrical test but do not pass the in-line quality assurance test to a quality assurance test waste bin.

7. The method of claim 1, further comprising providing the selected ones of the number of integrated circuit products that pass the electrical test and the in-line quality assurance test and are selected by the sampling to a quality assurance test waste bin.

8. The method of claim 1, further comprising providing the integrated circuit products subjected to the in-line quality assurance test to a quality assurance test waste bin.

9. The method of claim 8, wherein providing the integrated circuit products undergoing the in-line warranty test to a warranty test reject bin includes adjusting or setting one or more test parameters to disable the integrated circuit products from passing the in-line warranty test.

10. The method of any one of claims 6-9, further comprising providing the integrated circuit products in the warranty test waste bin to the test station for acceptable quality level testing.

11. The method of claim 10, wherein the acceptable quality level test is the same test content as the online quality assurance test.

12. The method of claim 10, further comprising providing the integrated circuit product that passes the acceptable quality level test to a quality assurance supply tube.

13. The method of claim 10, further comprising providing the integrated circuit products that fail the acceptable quality level test to a quality assurance waste pipe for further analysis.

14. The method of claim 13, wherein the quality assurance waste hose is coupled to a waste hose apparatus via a quality assurance test waste container.

15. The method of claim 13, wherein the further analyzing comprises analyzing a reason why the integrated circuit product provided to the quality assurance waste tube failed the acceptable quality level test.