CN111355491B - Single-channel analog signal sampling method and device - Google Patents
Single-channel analog signal sampling method and device Download PDFInfo
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Abstract
The invention provides a single-channel analog signal sampling method and a single-channel analog signal sampling device, wherein the method comprises the following steps: sending analog-to-digital conversion operation signals to an analog-to-digital converter according to a preset number of operation states so that the analog-to-digital converter converts the sampling signals of the single channel into corresponding digital signals; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state; and receiving the digital signal sent by the analog-to-digital converter as a sampling signal. The device is used for executing the method. The single-channel analog signal sampling method and the single-channel analog signal sampling device improve the operating efficiency of the processor.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to a single-channel analog signal sampling method and device.
Background
In the field of applications such as instruments and meters and switching power supplies, analog quantity signals such as sensor output, output voltage and output current are often required to be acquired.
In the prior art, an analog sampling device for converting analog quantity into digital quantity generally adopts a Serial Peripheral Interface (SPI for short) to reduce the area occupied by a circuit. Each sampling of the analog quantity sampling device adopting the SPI is sequentially completed in various stages of sampling, for example: a processor of the analog quantity sampling device firstly gives a Chip select signal (CS for short), waits for a certain time specified by a Chip, then sends a conversion instruction, waits for the completion of conversion, and reads data after the conversion is completed. In the existing application, when the above conversion process is performed, the processor adopts a waiting mode, so that the processor cannot process other events in the whole conversion process. For example, in an analog-to-digital conversion device with a conversion rate of 100kpbs, one sampling is completed for at least 10us, and if the sampling is performed for multiple times, the time is multiple times of the sampling period, so that the operating efficiency of the processor is reduced, and the response efficiency to external events is also reduced.
Disclosure of Invention
To solve the problems in the prior art, embodiments of the present invention provide a method and an apparatus for sampling a single-channel analog signal, which can at least partially solve the problems in the prior art.
In one aspect, the present invention provides a single-channel analog signal sampling method, including:
sending analog-to-digital conversion operation signals to an analog-to-digital converter according to a preset number of operation states so that the analog-to-digital converter converts the sampling signals of the single channel into corresponding digital signals; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state;
and receiving the digital signal sent by the analog-to-digital converter as a sampling signal.
In another aspect, the present invention provides a single-channel analog signal sampling apparatus, including:
the sampling unit is used for sending an analog-to-digital conversion operation signal to the analog-to-digital converter according to a preset number of operation states so that the analog-to-digital converter converts a single-channel sampling signal into a corresponding digital signal; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state;
and the receiving unit is used for receiving the digital signal sent by the analog-to-digital converter as a sampling signal.
In another aspect, the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the steps of the single-channel analog signal sampling method according to any of the above embodiments are implemented.
In yet another aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the single-channel analog signal sampling method according to any one of the above embodiments.
According to the single-channel analog signal sampling method and device provided by the embodiment of the invention, the analog-to-digital conversion operation signals are sent to the analog-to-digital converter according to the preset number of operation states, so that the analog-to-digital converter converts the single-channel sampling signals into corresponding digital signals, each operation state corresponds to one state flag quantity and one state processing function, the state flag quantity is used for starting the corresponding operation state, the state processing functions are used for processing the operation in the corresponding operation state, the digital signals sent by the analog-to-digital converter are received as the sampling signals, the sequential operation of the analog-to-digital conversion is realized in an operation state conversion mode, the waiting of the sequential operation is avoided, and the operation efficiency of the processor is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts. In the drawings:
fig. 1 is a schematic structural diagram of an analog sampling apparatus according to an embodiment of the present invention.
Fig. 2 is a schematic flow chart of a single-channel analog signal sampling method according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a single-channel analog signal sampling apparatus according to an embodiment of the present invention.
Fig. 4 is a schematic physical structure diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
Fig. 1 is a schematic structural diagram of an analog quantity sampling apparatus according to an embodiment of the present invention, and as shown in fig. 1, the analog quantity sampling apparatus according to the embodiment of the present invention includes an amplifying circuit 1, an analog-to-digital converter 2, a reference voltage generator 3, and a processor 4, where the amplifying circuit 1 is connected to the analog-to-digital converter 2, the reference voltage generator 3 is connected to the analog-to-digital converter 2, and a digital control interface of the analog-to-digital converter 2 is connected to an SPI of the processor 4. After an analog quantity signal acquired by a sensor and other devices is input into the amplifying circuit 1, the amplifying circuit 1 amplifies the input analog quantity signal, and then the sampling signal is transmitted to the analog-to-digital converter 2 through one channel of the analog-to-digital converter 2, the analog-to-digital converter 2 is used for converting the analog quantity into a digital quantity under the control of the processor 4 and uploading the digital quantity obtained by conversion to the processor 4, the reference voltage generator 3 is used for providing a reference voltage for the analog-to-digital converter 2, and the processor 4 is used for executing the single-channel analog signal sampling method provided by the embodiment of the invention, and the single-channel analog quantity signal is sampled through the analog-to-digital converter 2, so that the operating efficiency of the processor and the response speed of an external event can be improved. The processor 4 includes, but is not limited to, a Microcontroller (MCU for short), a signal processor, and a single chip microcomputer.
Fig. 2 is a schematic flowchart of a single-channel analog signal sampling method according to an embodiment of the present invention, and as shown in fig. 2, the single-channel analog signal sampling method according to the embodiment of the present invention includes:
s201, sending an analog-to-digital conversion operation signal to an analog-to-digital converter according to a preset number of operation states, so that the analog-to-digital converter converts a single-channel sampling signal into a corresponding digital signal; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state;
specifically, single-channel analog quantity signal sampling is initiated by a processor, the processor sends analog-to-digital conversion operation signals to an analog-to-digital converter according to a preset number of operation states, the analog-to-digital converter performs analog-to-digital conversion on the received analog quantity signals after receiving the analog-to-digital conversion operation signals, converts the received single-channel analog quantity signals into digital signals, and then sends the digital signals obtained through conversion to the processor. Each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state. The preset number may be set according to a conversion timing sequence of SPI interface communication required by the analog-to-digital converter, which is not limited in the embodiment of the present invention. The state processing function is set according to actual needs, and the embodiment of the invention is not limited. The order of state transitions between the preset number of operating states is predetermined.
And S202, receiving the digital signal sent by the analog-to-digital converter as a sampling signal.
Specifically, the processor receives the digital signal sent by the analog-to-digital converter, and uses the received digital signal as a sampling signal of a single-channel analog signal, thereby completing one sampling of the single-channel analog signal.
For example, an SPI interface of a processor connected to a certain analog-to-digital converter needs to pass through n timing operations during analog-to-digital conversion, each timing operation corresponds to one operation state, and an idle operation state can be defined, each operation state corresponds to one state flag amount, which is n +1 state flag amounts, and n +1 state flag amounts are sequentially expressed as: CONVERT _ STATE _0, CONVERT _ STATE _1, CONVERT _ STATE _2, \ 8230, \\ 8230; CONVERT _ STATE _ n-1, CONVERT _ STATE _ IDLE. The device comprises a device body, a device body and a device body, wherein the device body comprises a CONVERT _ STATE _0, a CONVERT _ STATE _1, a CONVERT _ STATE _2, a CONVERT _ 8230, a CONVERT _ STATE _ n-1 and a CONVERT _ STATE _ IDLE, the CONVERT _ STATE _ N-1 and the CONVERT _ STATE _ IDLE are respectively STATE flag quantities of operation STATEs corresponding to n time sequence operations, and the CONVERT _ STATE _ IDLE corresponds to an IDLE STATE flag quantity of an IDLE operation STATE.
The STATE flag quantities correspond to STATE processing functions, wherein the n STATE flag quantities are CONVERT _ STATE _0, CONVERT _ STATE _1, CONVERT _ STATE _2 \8230, the STATE processing functions corresponding to the CONVERT _ STATE _ n-1 are ad _ CONVERT _ STATE _0_fun (), ad _ CONVERT _ STATE _1_fun (), ad _ CONVERT _2_fun (), 8230, ad _ CONVERT _ 8230, and the STATE processing functions corresponding to the n STATE flag quantities are ad _ CONVERT _ STATE _0_ fun (), ad _ CONVERT _2_ fun (), and the STATE processing functions corresponding to the n STATE flag quantities are ad _ CONVERT _ STATE _1_ fun (), respectively.
And when the processor processes the sampling signal, sequentially calling a state processing function corresponding to each operation state through the state flag quantity corresponding to each operation state. The method comprises the steps of defining a STATE variable in advance, assigning the STATE variable to CONVERT _ STATE _0 when analog-digital conversion is needed, executing a STATE processing function ad _ CONVERT _ STATE _0 \\ \ u fun (), assigning the STATE variable to CONVERT _ STATE _1 after the STATE processing function ad _ CONVERT _ STATE _0 \ u fun () is completed, executing a STATE processing function ad _ CONVERT _ STATE _1 \\ \ u fun (), assigning the STATE variable to CONT _ STATE _2 after the STATE processing function ad _ CONVERT _ STATE _2 \\ \ u fun () is completed, and analogizing in sequence until the STATE processing function ad _ CONVERT _ STATE _ n-1 \\\ \ u fun () is completed, so that the sampling signal is converted into a digital signal. After the STATE processing function ad _ CONVERT _ STATE _ n-1_fun () has completed execution, the STATE variable may be set to CONVERT _ STATE _ IDLE, indicating that the transition is complete, in a wait STATE. And if analog-to-digital conversion is needed again, assigning the STATE variable as CONVERT _ STATE _0, and repeating the process. Due to the sequential conversion of the state variables, the correct conversion time sequence of the operation state is ensured, and the operation in the next operation state cannot be set when the operation in a certain operation state of the analog-digital conversion is not completed. By dividing a series of time sequence operations of analog-digital conversion into different states and realizing the execution process of the whole time sequence operation through the conversion of the operation states, the waiting between the time sequence operations is avoided, and the efficiency of the analog-digital conversion is improved.
According to the single-channel analog signal sampling method provided by the embodiment of the invention, the analog-to-digital conversion operation signals are sent to the analog-to-digital converter according to the preset number of operation states, so that the analog-to-digital converter converts the single-channel sampling signals into the corresponding digital signals, each operation state corresponds to one state flag quantity and one state processing function, the state flag quantity is used for starting the corresponding operation state, the state processing function is used for processing the operation in the corresponding operation state, the digital signals sent by the analog-to-digital converter are received as the sampling signals, the sequential operation of the analog-to-digital conversion is realized in an operation state conversion mode, the waiting of the sequential operation is avoided, and the operation efficiency of the processor is improved.
On the basis of the foregoing embodiments, further, each state processing function includes a state variable, and the state variable is used to start or stop execution of the state processing function.
Specifically, each state processing function includes a state variable, where the state variable is used to start execution of the state processing function or stop execution of the state processing function, for example, if the state variable is 1, the state processing function is executed to perform a subsequent processing procedure, and if the state variable is 0, the state processing function is stopped from being executed, and the state processing function is exited. This means that when executing the state processing function, it is necessary to determine whether or not the state processing function has an execution condition, and if the condition is satisfied, the state processing function is executed, and if not, the state processing function is exited, and there is no waiting operation.
On the basis of the foregoing embodiments, further, the operating state includes an idle state, and the idle state is used to indicate that sampling is stopped.
Specifically, the operating state includes an idle state, where the idle state corresponds to a state flag amount and a state processing function to indicate that sampling is completed, and the operating state enters the idle state to wait for next sampling.
On the basis of the foregoing embodiments, further, the sending an analog-to-digital conversion operation signal to the analog-to-digital converter according to a preset number of operation state changes includes:
and periodically sending the analog-to-digital conversion operation signal to the analog-to-digital converter.
In particular, the sampling of the single-channel analog signal may be periodic, that is, the single-channel analog signal may be sampled once at regular intervals and fixed time, and the processor may periodically send an analog-to-digital conversion operation signal to the analog-to-digital converter to implement the periodic sampling. The period is set according to actual needs, and the embodiment of the invention is not limited.
The ADS8344 chip is taken as an example to describe the implementation process of the single-channel analog signal sampling method provided by the embodiment of the invention. The SPI of the processor of the ADS8344 chip needs to output a 32-bit CLK waveform to complete sampling of a single-channel analog signal once, the 32-bit CLK waveform is divided into 4 bytes, and a plurality of sequential operations of analog-to-digital conversion include giving a chip select signal, sending a command byte, performing operation 1, performing operation 2, performing operation 3, and releasing the chip select signal, so that the analog-to-digital conversion process can be divided into six operating states, namely, an idle state, a chip select state, a command sending state, a conversion 1 state, a conversion 2 state, and a conversion 3 state. Giving a corresponding state flag quantity CS1 corresponding to the chip selection state and the chip selection signal; the sending command byte corresponds to a command sending state, and the corresponding state flag quantity is send; operation 1 corresponds to the transition 1 state, and the corresponding state flag amount is CON1; operation 2 corresponds to transition 2 state, and the corresponding state flag amount is CON2; operation 3 corresponds to transition 3, with the corresponding state flag amount being CON3; the chip select signal releases the corresponding status flag CS0 corresponding to the idle status. The processor executes the conversion sequence of six operation states as follows: chip selection state, command sending state, conversion 1 state, conversion 2 state, conversion 3 state and idle state.
When single-channel analog signal sampling is needed, the processor firstly sets a state variable as a state flag quantity CS1, then executes a state processing function corresponding to a chip selection state, sets a chip selection signal as a low level to select an analog-to-digital converter, and then starts a timer for timing, for example, timing for 100 microseconds; after the timing is finished, the state variable is set to send, and the execution of the state processing function corresponding to the chip selection state is finished. The timer is a functional module in the single chip microcomputer, a flag quantity is set after timing is finished, and whether the state processing function corresponding to the chip selection state is executed or not can be judged by accessing the flag quantity of the timer. If the status flag CS1 is 1, the status processing function corresponding to the chip selection status is not executed.
And when the state variable is send 1, the processor executes a state processing function corresponding to the command sending state, accesses the flag quantity of the timer, judges whether the flag quantity of the timer is set, if the setting indicates that the timer completes timing, the state processing function corresponding to the chip selection state is executed, and then sends a command byte to the analog-to-digital converter so as to set an analog channel and a working mode of the analog-to-digital converter and set the state variable as CON1. If the flag of the timer is not set, it indicates that the timer has not finished timing, and the execution of the state processing function corresponding to the command sending state will be skipped, and the state variable is sent, and it is determined in the next program cycle whether the timer has finished timing.
When the state variable is CON1, the processor executes a state processing function corresponding to the conversion 1 state, inquires a data transmission completion flag bit of an SPI module of a single chip microcomputer, judges whether a command byte is transmitted completely, and if the command byte is judged to be transmitted completely, transmits a byte with a first numerical value of zero to the analog-to-digital converter, so that DCLK of ADS8344 has 8 conversion clock pulses, the 8 conversion clock pulses enable the analog-to-digital converter to convert a received single-channel analog quantity signal into a digital signal, and then returns the digital signal to the processor, and the processor reads the received first byte and sets the state variable to be CON2. And if the command byte is judged not to be completely sent, jumping out the state processing function corresponding to the conversion 1 state, keeping the state variable as CON1, and judging whether the command byte is completely sent in the next program cycle.
When the state variable is CON2, the processor executes a state processing function corresponding to the conversion 2 state, inquires a data transmission completion flag bit of an SPI module of a singlechip peripheral module, judges whether a byte with a first value of zero is transmitted, and if the byte with the first value of zero is judged to be transmitted, transmits a byte with a second value of zero to the analog-to-digital converter, so that DCLK of ADS8344 has 8 conversion clock pulses, the 8 conversion clock pulses enable the analog-to-digital converter to convert a received single-channel analog quantity signal into a digital signal, and then returns the digital signal to the processor, and the processor reads the received second byte and sets the state variable to CON3. And if the first byte with the value of zero is judged not to be sent completely, jumping out of the state processing function corresponding to the conversion 2 state, keeping the state variable as CON2, and judging whether the first byte with the value of zero is sent completely or not in the next program cycle.
When the state variable is CON3, the processor executes a state processing function corresponding to the conversion 3 state, inquires a data transmission completion flag bit of an SPI module of the single chip microcomputer, judges whether a byte with a second value of zero is transmitted, and transmits a byte with a third value of zero to the analog-to-digital converter if the byte with the second value of zero is transmitted, so that DCLK of ADS8344 has 8 conversion clock pulses, the 8 conversion clock pulses enable the analog-to-digital converter to convert a received single-channel analog quantity signal into a digital signal, and then the digital signal is returned to the processor, the processor reads the received third byte, and the state variable is set to be CS0. If the second byte with the value of zero is not sent completely, the state processing function corresponding to the conversion 3 state is skipped, and the state variable is kept as CON3, and then the first byte with the value of zero is judged to be sent completely or not in the next program cycle.
When the state variable is CS0, the processor executes a state processing function corresponding to the idle state, inquires a data transmission completion flag bit of an SPI module of the single chip microcomputer, judges whether the transmission of a byte with a third numerical value of zero is completed or not, and if the transmission of the byte with the third numerical value of zero is completed, the processor reads the received fourth byte, processes the received four bytes to obtain a binary digital signal with 16 bits, and enters the idle state. And if the third byte with the value of zero is not sent completely, jumping out the state processing function corresponding to the idle state, keeping the state variable as CS0, and judging whether the third byte with the value of zero is sent completely in the next program cycle.
So far, after the execution of the state processing functions corresponding to the six operating states is completed, the ADS8344 chip completes one-time sampling of the single-channel analog signal.
Fig. 3 is a schematic structural diagram of a single-channel analog signal sampling apparatus according to an embodiment of the present invention, and as shown in fig. 3, the single-channel analog signal sampling apparatus according to the embodiment of the present invention includes a sampling unit 301 and a receiving unit 302, where:
the sampling unit 301 is configured to send an analog-to-digital conversion operation signal to the analog-to-digital converter according to a preset number of operation states, so that the analog-to-digital converter converts a single-channel sampling signal into a corresponding digital signal; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state; the receiving unit 302 is configured to receive the digital signal sent by the analog-to-digital converter as a sampling signal.
Specifically, sampling of the single-channel analog quantity signal is initiated by the sampling unit 301, the sampling unit 301 sends an analog-to-digital conversion operation signal to the analog-to-digital converter according to a preset number of operation states, after receiving the analog-to-digital conversion operation signal, the analog-to-digital converter performs analog-to-digital conversion on the received analog quantity signal, converts the received single-channel analog quantity signal into a digital signal, and then sends the converted digital signal to the receiving unit 302. Each operation state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operation state, and the state processing function is used for processing the operation in the corresponding operation state. The preset number may be set according to a conversion timing sequence of SPI interface communication required by the analog-to-digital converter, which is not limited in the embodiment of the present invention. The state processing function is set according to actual needs, and the embodiment of the invention is not limited. The order of state transitions between the preset number of operating states is predetermined.
The receiving unit 302 receives the digital signal sent by the analog-to-digital converter, and uses the received digital signal as a sampling signal of a single-channel analog signal, thereby completing one sampling of the single-channel analog signal.
The single-channel analog signal sampling device provided by the embodiment of the invention sends analog-to-digital conversion operation signals to the analog-to-digital converter according to the preset number of operation states, so that the analog-to-digital converter converts the single-channel sampling signals into corresponding digital signals, each operation state corresponds to one state flag quantity and one state processing function, the state flag quantity is used for starting the corresponding operation state, the state processing function is used for processing the operation in the corresponding operation state, the digital signals sent by the analog-to-digital converter are received as the sampling signals, and the sequential operation of the analog-to-digital conversion is realized in an operation state conversion mode, so that the waiting of the sequential operation is avoided, and the operation efficiency of the processor is improved.
On the basis of the foregoing embodiments, further, each state processing function includes a state variable, and the state variable is used to start or stop execution of the state processing function.
Specifically, each state processing function includes a state variable, where the state variable is used to start execution of the state processing function or stop execution of the state processing function, for example, if the state variable is 1, the state processing function is executed to perform a subsequent processing procedure, and if the state variable is 0, the state processing function is stopped from being executed, and the state processing function is exited. This means that when executing the state processing function, it is necessary to determine whether or not the state processing function has an execution condition, and if the condition is satisfied, the state processing function is executed, and if not, the state processing function is exited, and there is no waiting operation.
On the basis of the foregoing embodiments, further, the operating state includes an idle state, and the idle state is used to indicate that sampling is stopped.
Specifically, the operating state includes an idle state, and the idle state corresponds to a state flag amount and a state processing function to indicate that sampling is completed, and enters the idle state to wait for next sampling.
On the basis of the foregoing embodiments, further, the sampling unit 301 is specifically configured to:
and periodically sending the analog-to-digital conversion operation signal to the analog-to-digital converter.
Specifically, the sampling of the single-channel analog signal may be periodic, that is, the single-channel analog signal may be sampled once at regular intervals and fixed time, and the sampling unit 301 may periodically send the analog-to-digital conversion operation signal to the analog-to-digital converter to implement the periodic sampling. The period is set according to actual needs, and the embodiment of the invention is not limited.
The embodiment of the single-channel analog signal sampling apparatus provided in the embodiment of the present invention may be specifically configured to execute the processing flows of the above method embodiments, and the functions of the embodiment are not described herein again, and reference may be made to the detailed description of the method embodiments.
Fig. 4 is a schematic physical structure diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 4, the electronic device may include: a processor (processor) 401, a communication Interface (communication Interface) 402, a memory (memory) 403 and a communication bus 404, wherein the processor 401, the communication Interface 402 and the memory 403 complete communication with each other through the communication bus 404. Processor 401 may call logic instructions in memory 403 to perform the following method: sending analog-to-digital conversion operation signals to an analog-to-digital converter according to a preset number of operation states so that the analog-to-digital converter converts the sampling signals of the single channel into corresponding digital signals; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state; and receiving the digital signal sent by the analog-to-digital converter as a sampling signal.
In addition, the logic instructions in the memory 403 may be implemented in the form of software functional units and stored in a computer readable storage medium when the software functional units are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The present embodiment discloses a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, enable the computer to perform the method provided by the above-mentioned method embodiments, for example, comprising: sending an analog-to-digital conversion operation signal to an analog-to-digital converter according to a preset number of operation states, so that the analog-to-digital converter converts a single-channel sampling signal into a corresponding digital signal; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state; and receiving the digital signal sent by the analog-to-digital converter as a sampling signal.
The present embodiment provides a computer-readable storage medium, which stores a computer program, where the computer program causes the computer to execute the method provided by the above method embodiments, for example, the method includes: sending analog-to-digital conversion operation signals to an analog-to-digital converter according to a preset number of operation states so that the analog-to-digital converter converts the sampling signals of the single channel into corresponding digital signals; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state; and receiving the digital signal sent by the analog-to-digital converter as a sampling signal.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the description herein, reference to the description of the terms "one embodiment," "a particular embodiment," "some embodiments," "for example," "an example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for sampling a single-channel analog signal, comprising:
sending analog-to-digital conversion operation signals to an analog-to-digital converter according to a preset number of operation states so that the analog-to-digital converter converts the sampling signals of the single channel into corresponding digital signals; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state;
and receiving the digital signal sent by the analog-to-digital converter as a sampling signal.
2. The method of claim 1, wherein each state processing function includes a state variable that is used to start or stop execution of the state processing function.
3. The method of claim 1, wherein the operating state comprises an idle state, and wherein the idle state is used to indicate that sampling is stopped.
4. The method of any one of claims 1 to 3, wherein sending an analog-to-digital conversion operation signal to an analog-to-digital converter according to a preset number of operation states comprises:
and periodically sending the analog-to-digital conversion operation signal to the analog-to-digital converter.
5. A single-channel analog signal sampling apparatus, comprising:
the sampling unit is used for sending an analog-to-digital conversion operation signal to the analog-to-digital converter according to a preset number of operation states so that the analog-to-digital converter converts a single-channel sampling signal into a corresponding digital signal; each operating state corresponds to a state flag quantity and a state processing function, the state flag quantity is used for starting the corresponding operating state, and the state processing function is used for processing the operation in the corresponding operating state;
and the receiving unit is used for receiving the digital signal sent by the analog-to-digital converter as a sampling signal.
6. The apparatus of claim 5, wherein each state processing function comprises a state variable that is used to start or stop execution of the state processing function.
7. The apparatus of claim 5, wherein the operating state comprises an idle state, and wherein the idle state is used to indicate that sampling is stopped.
8. The device according to any one of claims 5 to 7, characterized in that the sampling unit is specifically configured to:
and periodically sending the analog-to-digital conversion operation signal to the analog-to-digital converter.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the method of any one of claims 1 to 4 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1746838A (en) * | 2005-10-17 | 2006-03-15 | 张金贵 | Sampling method and system for multi-channel analog signal |
| CN105720986A (en) * | 2016-01-22 | 2016-06-29 | 山西大学 | Multi-channel data collection system with unified time stamp |
| CN109752986A (en) * | 2017-11-08 | 2019-05-14 | 南京天擎汽车电子有限公司 | Sampling control method and sampling control mechanism, electronic equipment and storage medium |
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| KR100583723B1 (en) * | 2003-09-16 | 2006-05-25 | 삼성전자주식회사 | Apparatus for sampling a plurality of analog signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1746838A (en) * | 2005-10-17 | 2006-03-15 | 张金贵 | Sampling method and system for multi-channel analog signal |
| CN105720986A (en) * | 2016-01-22 | 2016-06-29 | 山西大学 | Multi-channel data collection system with unified time stamp |
| CN109752986A (en) * | 2017-11-08 | 2019-05-14 | 南京天擎汽车电子有限公司 | Sampling control method and sampling control mechanism, electronic equipment and storage medium |
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