CN111354816A - Semiconductor device with a plurality of transistors - Google Patents

Semiconductor device with a plurality of transistors Download PDF

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CN111354816A
CN111354816A CN201811567572.2A CN201811567572A CN111354816A CN 111354816 A CN111354816 A CN 111354816A CN 201811567572 A CN201811567572 A CN 201811567572A CN 111354816 A CN111354816 A CN 111354816A
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layer
detector
gesn
doped
light source
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左瑜
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Xian Keruisheng Innovative Technology Co Ltd
Xian Cresun Innovation Technology Co Ltd
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Xian Keruisheng Innovative Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/125—Composite devices with photosensitive elements and electroluminescent elements within one single body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0328—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032
    • H01L31/0336—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032 in different semiconductor regions, e.g. Cu2X/CdX hetero-junctions, X being an element of Group VI of the Periodic System
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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Abstract

The invention relates to a semiconductor device which comprises a Si substrate, a Ge layer, a light source GeSn layer, a waveguide GeSn layer, a detector GeSn layer, a light source p + Ge-doped layer, a detector p + Ge-doped layer, a light source p + Si-doped layer, a detector p + Si-doped layer, a light source protective layer, a detector protective layer, a first oxidation layer, a second oxidation layer, an α -Si layer and electrode layers, wherein the electrode layers are sequentially stacked on the Si substrate from bottom to top, first stress films are arranged on the first oxidation layer, the second oxidation layer, the α -Si layer, the two sides of the waveguide GeSn layer and the two sides of the waveguide GeSn layer, and second stress films are arranged on the detector GeSn layer, the detector p + Ge-doped layer, the detector p + Si-doped layer, the two sides of the detector protective layer and the detector protective layer.

Description

Semiconductor device with a plurality of transistors
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a semiconductor device.
Background
Integrated optoelectronics is one of the development fronts in the field of optoelectronics nowadays, and mainly studies theories, technologies and applications of optoelectronics devices and optoelectronic systems integrated on a plane, so that the integrated optoelectronics is a necessary route and a high-level stage for the development of optoelectronics. The concept of photovoltaic integration has been proposed for over twenty years to date. With the development of optical communication, optical information processing, optical computing, optical display, and other disciplines, there is a strong interest in Optoelectronic integration with small size, light weight, stable and reliable operation, low power consumption, and high-speed operation, and together with the progress of material science and advanced manufacturing technology, it becomes possible to integrate optical, optical/electrical, and electronic elements on a single-structure or monolithic n + doped Si substrate, and to construct Optoelectronic Integrated circuits (OEICs) with single or multiple functions. With the continuous progress of semiconductor technology, the integration scale and circuit speed are doubled, and therefore, a series of electrical interconnection and optical interconnection problems are caused.
However, the optical and electronic devices prepared by the existing preparation process are not compatible in structure, high in production cost and long in process period.
Therefore, it is important to fabricate a semiconductor device that allows easy structural compatibility between optical and electronic devices.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a semiconductor device. The technical problem to be solved by the invention is realized by the following technical scheme:
an embodiment of the present invention provides a semiconductor device, including:
a Si substrate;
the Ge layer is arranged on the Si substrate;
the light source GeSn layer, the light source p + doped Ge layer, the light source p + doped Si layer and the light source protective layer are sequentially arranged on the Ge layer in a stacking mode from bottom to top;
the waveguide GeSn layer is arranged on the Ge layer;
the detector comprises a detector GeSn layer, a detector p + doped Ge layer, a detector p + doped Si layer and a detector protective layer, wherein the detector GeSn layer, the detector p + doped Ge layer, the detector p + doped Si layer and the detector protective layer are sequentially arranged on the Ge layer in a stacking mode from bottom to top;
a first oxide layer and a second oxide layer, both disposed on the Ge layer, wherein the first oxide layer is disposed between the light source GeSn layer and the waveguide GeSn layer, and the second oxide layer is disposed between the waveguide GeSn layer and the detector GeSn layer;
α -Si layer disposed on the waveguide GeSn layer;
the first stress film is arranged on the first oxide layer, the second oxide layer, the α -Si layer, on the two sides of the first oxide layer, on the two sides of the waveguide GeSn layer;
the second stress film is arranged on the detector GeSn layer, the detector p + doped Ge layer, the detector p + doped Si layer, two sides of the detector protective layer and the detector protective layer;
the electrode is arranged on the Ge layer, the light source protection layer and the second stress film.
In one embodiment of the invention, the Si substrate is formed of an n + doped Si material and has a thickness of 30nm to 750 nm.
In an embodiment of the invention, the thickness of each of the light source GeSn layer and the detector GeSn layer is 250nm, and the thickness of the waveguide GeSn layer is 160nm-200 nm.
In one embodiment of the invention, the light source GeSn layer, the waveguide GeSn layer and the detector GeSn layer are all formed by GeSn materials, and the Sn component in the GeSn materials is 3% -5%.
In one embodiment of the invention, the thickness of the light source p + doped Ge layer and the thickness of the detector p + doped Ge layer are both 100 nm.
In one embodiment of the invention, the thickness of the light source p + doped Si layer and the thickness of the detector p + doped Si layer are both 300 nm.
In one embodiment of the invention, the thickness of the light source protective layer and the thickness of the detector protective layer are both 900 nm.
In one embodiment of the present invention, the first oxide layer and the second oxide layer are both SiO2The material is formed, and the width of the material is 20nm-50 nm.
In one embodiment of the present invention, the α -Si layer is formed of α -Si material and has a thickness of 800nm to 840 nm.
In one embodiment of the present invention, the first stress film and the second stress film are both formed of SiN material and have a thickness of 10nm to 20 nm.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the Si-based modified Ge material is used, and the light source, the waveguide and the detector are integrated on the same layer to form the semiconductor device, and the semiconductor device has the advantages of easily compatible structure between the optical device and the electronic device, novel structure, high integration level, low production cost and short process period.
Drawings
Fig. 1 is a schematic front view of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating transmittance simulation of a first oxide layer and a second oxide layer with different thicknesses at different wavelengths according to an embodiment of the present invention;
FIG. 3 is a graph showing simulated transmittance of a waveguide region at different wavelengths without α -Si layer and with α -Si layer according to an embodiment of the present invention;
FIG. 4-1 is a schematic top view of a linear tapered transition waveguide region according to an embodiment of the present invention;
fig. 4-2 is a schematic top view of a convex tapered transition waveguide region according to an embodiment of the present invention;
fig. 4-3 are schematic top-view structural diagrams of concave tapered transition waveguide regions according to embodiments of the present invention;
FIG. 5-1 is a schematic diagram of a simulation of the effect of different shapes of tapered transition waveguide regions on the throw ratio under different wavelength conditions according to an embodiment of the present invention;
fig. 5-2 is a simulation diagram illustrating the effect of different tapered transition waveguide lengths on transmittance under different wavelength conditions according to an embodiment of the present invention;
FIG. 6-1 is a schematic diagram of a right-view structure of a first stress film according to an embodiment of the present invention;
FIG. 6-2 is a schematic diagram of a right-view principle of a waveguide for generating intrinsic compressive stress by a first stress film according to an embodiment of the present invention;
FIG. 6-3 is a schematic top view of a waveguide for generating intrinsic compressive stress by a first stressed film according to an embodiment of the invention;
FIG. 7-1 is a schematic diagram of a right-view structure of a second stress film according to an embodiment of the invention;
FIG. 7-2 is a schematic diagram of a right view of a detector under tensile stress generated by a second stress film according to an embodiment of the present invention;
fig. 8a to 8f, fig. 8g, fig. 8i, fig. 8k, fig. 8m, fig. 8o, and fig. 8q are schematic process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 8h is a schematic diagram illustrating a top view of a semiconductor device fabricated by a process corresponding to FIG. 8g in accordance with an embodiment of the present invention;
fig. 8j is a schematic top view of a semiconductor device fabricated by a process corresponding to fig. 8i according to an embodiment of the present invention;
FIG. 8l is a schematic diagram illustrating a top view of a semiconductor device fabricated by a process corresponding to FIG. 8k according to an embodiment of the present invention;
fig. 8n is a schematic top view of a semiconductor device fabricated by a process corresponding to fig. 8m according to an embodiment of the present invention;
FIG. 8p is a schematic top view of a semiconductor device fabricated by the process corresponding to FIG. 8o in accordance with an embodiment of the present invention;
fig. 8r is a schematic top view of a semiconductor device manufactured by the process corresponding to fig. 8q according to an embodiment of the present invention.
In the figure, a 001-Si substrate, a 002-Ge layer, a 0031-light source GeSn layer, a 0032-waveguide GeSn layer, a 0033-detector GeSn layer, a 0041-light source p + doped Ge layer, a 0042-detector p + doped Ge layer, a 0051-light source p + doped Si layer, a 0052-detector p + doped Si layer, a 0061-light source protective layer, a 0062-detector protective layer, a 0071-first oxidation layer, a 0072-second oxidation layer, a 008- α -Si layer, a 009-first stress film, a 010-second stress film and a 011-electrode.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Fig. 1 is a schematic front view of a semiconductor device according to an embodiment of the present invention, and as shown in fig. 1, the semiconductor device includes:
a Si substrate 001;
wherein the Si substrate 001 is formed of an n + -doped Si material and has a thickness of 30nm to 750 nm.
A Ge layer (002) provided on the Si substrate (001);
the light source GeSn layer (0031), the light source p + doped Ge layer (0041), the light source p + doped Si layer (0051) and the light source protective layer (0061), wherein the light source GeSn layer (0031), the light source p + doped Ge layer (0041), the light source p + doped Si layer (0051) and the light source protective layer (0061) are sequentially arranged on the Ge layer (002) in a stacking mode from bottom to top;
a waveguide GeSn layer (0032) disposed on the Ge layer (002);
the detector comprises a detector GeSn layer (0033), a detector p + doped Ge layer (0042), a detector p + doped Si layer (0052) and a detector protective layer (0062), wherein the detector GeSn layer (0033), the detector p + doped Ge layer (0042), the detector p + doped Si layer (0052) and the detector protective layer (0062) are sequentially arranged on the Ge layer (002) in a stacking mode from bottom to top;
the thickness of the light source GeSn layer (0031) and the thickness of the detector GeSn layer (0033) are both 250nm, and the thickness of the waveguide GeSn layer (0032) is 160nm-200 nm; the light source GeSn layer (0031), the waveguide GeSn layer (0032) and the detector GeSn layer (0033) are all formed by GeSn materials, and the Sn component in the GeSn materials is 3% -5%.
The thicknesses of the light source p + doped Ge layer (0041) and the detector p + doped Ge layer (0042) are both 100 nm.
Wherein, the thicknesses of the light source p + doped Si layer (0051) and the detector p + doped Si layer (0052) are both 300 nm.
Wherein, the thickness of the light source protection layer (0061) and the detector protection layer (0062) is 900 nm.
The first oxide layer (0071) and the second oxide layer (0072) are arranged on the Ge layer (002), wherein the first oxide layer (0071) is arranged between the light source GeSn layer (0031) and the waveguide GeSn layer (0032), and the second oxide layer (0072) is arranged between the waveguide GeSn layer (0032) and the detector GeSn layer (0033);
wherein the first oxide layer (0071) and the second oxide layer (0072) are both made of SiO2The material is formed with a thickness of 20nm to 50nm, preferably 20 nm. The first oxide layer (0071) and the second oxide layer (0072) have an electric isolation effect on the light source GeSn layer (0031), the waveguide GeSn layer (0032) and the detector GeSn layer (0033), and a parasitic effect of photoelectric devices at two ends is prevented.
Fig. 2 is a schematic diagram illustrating transmittance simulation of the first oxide layer (0071) and the second oxide layer (0072) with different thicknesses according to an embodiment of the present invention at different wavelengths, as shown in fig. 2, the longer the wavelength is, the less the influence of the interface is; the effect of the first oxide layer (0071) and the second oxide layer (0072) substantially 20nm thick on light transmission is the same as that without the first oxide layer (0071) and the second oxide layer (0072), and the effect on the whole light transmission is very small and can be substantially ignored; when the first oxide layer (0071) and the second oxide layer (0072) are gradually thickened, the transmittance is gradually decreased, and the transmittance is more decreased as the thickness is increased.
The above conclusion is that the coupling loss increases because the scattering loss and reflection of the first oxide layer (0071) and the second oxide layer (0072) become larger as the thickness increases. When the wavelength is about 1.75 μm, the coupling efficiency between the device without the first oxide layer (0071) and the second oxide layer (0072) and the waveguide with the first oxide layer (0071) and the second oxide layer (0072) and the thickness of 20nm is basically 84% -85%, and the coupling efficiency between the device with the thickness of 50nm of the first oxide layer (0071) and the second oxide layer (0072) is basically 81% -82%, which shows that the influence of the first oxide layer (0071) and the second oxide layer (0072) on the loss between the device and the waveguide is not negligible.
α -Si layer (008) disposed on the waveguide GeSn layer (0032);
wherein, the thickness of the α -Si layer (008) is 800nm-840nm, fig. 3 is a simulation diagram of the transmittance of the waveguide region under different wavelengths when no α -Si layer and α -Si layer are provided according to the embodiment of the present invention, and as shown in fig. 3, the addition of the α -Si layer (008) can reduce the coupling loss, which is substantially the same as the coupling condition between the optical fiber and the device, and can reduce the loss more than the design of the side wall.
In addition, the light source GeSn layer 0031, the light source p + Ge-doped layer 0041, the light source p + Si-doped layer 0051 and the light source protection layer 0061 form a light source region, the waveguide GeSn layer 0032, the first oxidation layer 0071, the second oxidation layer 0072 and the α -Si layer 008 form a waveguide region, and the detector GeSn layer 0033, the detector p + Ge-doped layer 0042, the detector p + Si-doped layer 0052 and the detector protection layer 0062 form a detector region.
Wherein the light source region constitutes a laser together with the substrate 001 and the Ge layer 002.
The waveguide region comprises a conical transition waveguide region and a rectangular waveguide region, and two sides of the conical transition waveguide region can be in different shapes, such as a linear type, a convex type and a concave type. As shown in figure 4-1 of the drawings,
fig. 4-1 is a schematic top-view structure diagram of a linear tapered transition waveguide region provided in an embodiment of the present invention, as shown in fig. 4-2, fig. 4-2 is a schematic top-view structure diagram of a convex tapered transition waveguide region provided in an embodiment of the present invention, as shown in fig. 4-3, and fig. 4-3 is a schematic top-view structure diagram of a concave tapered transition waveguide region provided in an embodiment of the present invention. The longer the length of the tapered transition waveguide, the smaller the change size in the propagation direction, but the nonlinear increase, and the loss decreases less and less with the increase of the length, so the transmission loss of light is less affected.
Fig. 5-1 is a schematic diagram illustrating simulation of influence of different shapes of tapered transition waveguide regions on transmittance under different wavelength conditions according to an embodiment of the present invention, where as shown in fig. 5-1, a concave transition waveguide increases transmission loss, and a convex transition waveguide is advantageous in transmission with a fixed transition length, and a longer transition wavelength is selected as much as possible when the actual application allows.
Fig. 5-2 is a schematic diagram illustrating simulation of influence of different tapered transition waveguide lengths on transmittance under different wavelength conditions according to an embodiment of the present invention, as shown in fig. 5-2, a tapered transition waveguide length L ranges from 5 μm to 15 μm, and transmittance is the best when the tapered transition waveguide length L is 15 μm, but in a device design process, the tapered transition waveguide length L is not too long, and therefore the tapered transition waveguide length L is preferably 10 μm.
The first stress films (009) are arranged on the first oxide layer (0071), the second oxide layer (0072) and the α -Si layer (008) and on two sides of the waveguide GeSn layer (0032);
fig. 6-1 is a schematic right view of the first stressor film (009) according to an embodiment of the present invention, as shown in fig. 6-1, the first stressor film (009) is disposed in the waveguide region and on both sides thereof, and has a thickness of 10nm to 20 nm. Fig. 6-2 and 6-3 are a schematic diagram illustrating a right view and a schematic diagram illustrating a top view of the first stressor film 009 for generating intrinsic compressive stress in the waveguide according to an embodiment of the present invention, as shown in fig. 6-2 and 6-3, respectively, and a low frequency power source is used to introduce high energy particle bombardment, which causes atoms or ions of the first stressor film 009 to combine or redistribute, i.e., cause the first stressor film 009 to become compressive and to stretch or expand, thereby generating intrinsic compressive stress in the first stressor film 009.
The intrinsic stress is also called internal stress, and is generated in the film deposition growth environment (such as temperature, pressure, gas flow rate, etc.). If the film has a tendency to shrink along the film surface, the matrix generates tensile stress on the film, and conversely, the expansion tendency of the film along the film surface causes compressive stress. The intrinsic stress is closely related to the preparation method and the process of the thin film, and is different with the difference of the thin film and the base material.
Under the condition that other process conditions are not changed, the higher the first temperature is, the larger the formed waveguide compressive stress is; under the condition that other process conditions are not changed, the higher the first pressure is, the smaller the formed waveguide compressive stress is; under the condition that other process conditions are unchanged, the higher the low-frequency power is, the higher the formed waveguide compressive stress is. And the magnitude of the pressure stress has a certain linear relation with the first temperature, the first pressure, the low-frequency power and the first gas flow rate. The compressive stress satisfies the following formula:
the first temperature is related to the compressive stress, Tc is-1.0 × T-463.6;
the first pressure intensity is related to the pressure stress, Tc is 1.03 × P-1363.5;
tc is-0.7 × R-813.4;
the first gas flow rate is related to the compressive stress, Tc 24 × X2-167×X-560；
Wherein Tc is compressive stress in Pa; t is a first temperature in units of; p is a first pressure in mTorr; r is low-frequency power and has the unit of W; x is the first gas flow ratio.
The second stress film 010 is arranged on a detector GeSn layer (0033), a detector p + doped Ge layer (0042), a detector p + doped Si layer (0052), two sides of a detector protection layer (0062) and the detector protection layer (0062);
fig. 7-1 is a schematic right-view structural diagram of the second stress film 010 according to the embodiment of the present invention, and as shown in fig. 7-1, the second stress film 010 is disposed on the Si substrate 001, the detector region, and both sides, and has a thickness of 10nm to 20 nm. Fig. 7-2 is a schematic diagram of a right view principle of the second stressed film 010 enabling the detector to generate tensile stress, as shown in fig. 7-2, a high-energy particle bombardment is introduced by using a radio frequency power source, so that atoms or ions of the second stressed film 010 are combined or redistributed, that is, the second stressed film 010 becomes tensile, and thus the detector generates intrinsic tensile stress. Under the condition that other process conditions are not changed, the higher the second temperature is, the larger the formed detector tensile stress is; under the condition that other process conditions are not changed, the higher the second pressure, the smaller the tensile stress of the formed detector is; under the condition that other process conditions are unchanged, the larger the radio frequency power is, the larger the tensile stress of the formed detector is. And the magnitude of the tensile stress has a certain linear relation with the second temperature, the second pressure, the radio frequency power and the second gas flow rate. The tensile stress satisfies the following formula:
the second temperature is related to the tensile stress Ts, wherein Ts is 1.2 × T' -34.1;
the second pressure is related to the tensile stress Ts, wherein Ts is 0.3 × P' -28.5;
radio frequency power and tensile stress Ts relation, Ts (-2.48 × 10)-6)×R′2+0.26×R′+134.1；
The second gas flow ratio is related to the tensile stress Ts, wherein Ts is-265.4 × X'2+574.6×X′+140.3；
Wherein Ts is tensile stress with the unit of Pa; t' is a second temperature in units of; p' is a second pressure in mTorr; r' is radio frequency power and has the unit of W; and X' is the second gas flow ratio.
Because the first stress film 009 wraps the waveguide region, the stress directly acts on the waveguide, so that the waveguide is subjected to compressive stress, and the forbidden bandwidth of the waveguide is increased; because the second stress film 010 wraps the detector area and the Si substrate, stress directly acts on the detector, so that the detector is subjected to tensile stress along the direction perpendicular to the optical transmission direction, and the forbidden bandwidth of the detector is reduced. Thereby satisfying the forbidden band relation: eg waveguide > Eg light source > Eg detector, where Eg represents the forbidden band width. The integration of the light source, the waveguide and the detector is realized on the same layer by modulating the forbidden band relation of the light source, the waveguide and the detector, and the device has the advantages of novel structure, high integration level and low process cost.
The first stress film 009 and the second stress film 010 have a thickness of 10nm-20 nm.
The electrode (011) is arranged on the Ge layer (002), the light source GeSn layer (0031) and the second stress film (010).
Wherein the electrode 011 is formed of metallic Al and has a thickness of 10nm-20 nm.
In addition, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
s1, selecting an n + doped Si substrate 001;
specifically, referring to fig. 8a, fig. 8a is a schematic front view of a semiconductor device according to an embodiment of the present invention.
S2, sequentially growing a Ge layer 002, a GeSn layer 003, a p + Ge-doped layer 004, a p + Si-doped layer 005 and a protective layer 006 on the n + Si-doped substrate;
referring to fig. 8b to 8f, fig. 8b to 8f are schematic process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Wherein, step S2 includes:
s21, epitaxially growing a Ge layer 002 on the substrate 001 by CVD (Chemical Vapor Deposition) process at a temperature of 330 ℃;
referring to fig. 8b, the Ge layer 002 is formed of n + + doped Ge material, the thickness of the Ge layer 002 is 50nm, and the doping concentration is 1020cm-3。
The CVD process is a method of forming a thin film by performing a chemical reaction on a substrate using one or more gas-phase compounds or simple substances containing thin film elements.
S22, introducing H2And growing a GeSn layer 003 with a thickness of 150nm-200nm on the buried layer 002 by a reduced pressure CVD process at a temperature of 350 ℃ or below, wherein the Sn component in the GeSn material is controlled to be 3% -5%.
In addition, since the solid solubility of Sn is low, Sn does not overflow due to the Sn component.
The solid solubility refers to the maximum content of solute in solid solution, i.e., the limit solubility of solute in a solvent.
Referring to fig. 8c, step S22 includes:
s221, growing a Ge virtual substrate on the Ge layer 002, wherein the thickness is 50 nm;
s222, performing rapid thermal annealing on the Ge virtual substrate to form thermal mismatch, and introducing 0.2% of tensile stress;
among them, thermal annealing is a conventional technique in semiconductor processing, and is generally used to activate doping elements in semiconductor materials and restore amorphous structures caused by ion implantation into complete lattice structures.
S223 with SnCl4As Sn source, GeH4As a Ge source, epitaxially growing Ge on a Ge dummy substrate0.97Sn0.03A layer having a thickness of 150nm to 200 nm.
Wherein, due to Ge0.97Sn0.03Lattice-matched with both Ge-dummy substrates, Ge0.97Sn0.030.2% tensile stress is also present in the epitaxial layer.
S23, growing a p + Ge-doped layer 004 on the GeSn layer 003 by using a CVD process at the temperature of 160 ℃;
referring to FIG. 8d, the thickness of the p + Ge-doped layer 004 is 100nm, and the doping concentration is 3 × 1019cm-3。
S24, growing a p + doped Si layer 005 on the p + doped Ge layer 004 by utilizing a CVD process at the temperature of 275-325 ℃;
in particular, referring to FIG. 8e, the p + doped Si layer 005 is 300nm thick and dopedImpurity concentration of 1020cm-3。
S25, depositing a protective layer 006 on the p + doped Si layer 005 by LPCVD (Low Pressure Chemical Vapor Deposition), as shown in fig. 8 f.
Wherein, step S25 includes:
depositing a first Ti layer on the p + doped Si layer 005 by an LPCVD (low pressure chemical vapor deposition) process, wherein the thickness of the first Ti layer is 300 nm;
depositing an Al layer on the first Ti layer by using an LPCVD (low pressure chemical vapor deposition) process, wherein the thickness of the Al layer is 300 nm;
and depositing a second Ti layer on the Al layer by an LPCVD process, wherein the thickness of the second Ti layer is 300 nm.
The basic principle of the LPCVD process is to activate one or more gaseous substances with heat energy under a relatively low pressure to cause thermal decomposition or chemical reaction, and deposit the substances on the surface of a material to form a desired thin film.
S3, an etching protective layer 006, a p + doped Si layer 005, a p + doped Ge layer 004 and a GeSn layer 003 form a light source region, a waveguide region and a detector region which are sequentially isolated;
referring to fig. 8g and 8h, fig. 8g is a schematic process flow diagram of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention, and fig. 8h is a schematic top view structure diagram of the monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 8g according to the embodiment of the present invention.
Wherein, step S3 includes:
s31, introducing the HF etching protective layer 006 and the p + doped Si layer 005 by using a dry etching process;
the dry etching refers to a technique of performing thin film etching using plasma.
S32, dry etching process is adopted, and HF: HNO with concentration ratio of 1:2.5:10 is adopted3:CH3And etching the p + Ge-doped layer 004 and the GeSn layer 003 by COOH to form a light source region, a waveguide region and a detector region which are isolated in sequence, wherein isolation grooves are formed between the waveguide region and the light source region and between the waveguide region and the detector region.
Wherein the light source region includes: a light source GeSn layer 0031, a light source p + doped Ge layer 0041, a light source p + doped Si layer 0051 and a light source protective layer 0061; the waveguide region includes a waveguide GeSn layer 0032; the detector region includes: a detector GeSn layer 0033, a detector p + doped Ge layer 0042, a detector p + doped Si layer 0052 and a detector protection layer 0062.
S4, introducing SiH4And O2Depositing a first oxide layer 0071 and a second oxide layer 0072 in the isolation trench, wherein the widths of the first oxide layer 0071 and the second oxide layer 0072 are 20nm-50nm, preferably 20 nm;
referring to fig. 8i and 8j specifically, fig. 8i is a schematic process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 8j is a schematic top view structure diagram of the semiconductor device manufactured by the process corresponding to fig. 8i according to the embodiment of the present invention.
S5, depositing α -Si layer 008 on the waveguide area;
specifically, referring to fig. 8k and fig. 8l, fig. 8k is a schematic process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 8l is a schematic top view structure diagram of the semiconductor device manufactured by the process corresponding to fig. 8k according to the embodiment of the present invention.
S6, depositing a first stress film 009 on the first oxide layer 0071, the second oxide layer 0072, the α -Si layer 008 and both sides of the waveguide region;
referring to fig. 8m and 8n, fig. 8m is a schematic process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 8n is a schematic top view structure diagram of the semiconductor device manufactured by the process corresponding to fig. 8m according to the embodiment of the present invention.
Wherein, step S6 includes:
s61, introducing SiH under the first preset condition4And NH3The first stress film 009 is deposited on and at both sides of the waveguide region with a thickness of 10nm to 20nm using a PECVD (Plasma Enhanced chemical vapor Deposition) process.
The first preset condition includes: a first temperature, a first pressure, a low frequency power, a first gas flow ratio. Wherein the first temperature is 340-360 deg.C, the first pressure is 500mTorr, and the low frequency work is performedRate 150W, SiH4And NH3Has a first gas flow ratio of 2.
The PECVD process is a process in which a gas containing atoms constituting a thin film is ionized by microwaves or radio frequencies to locally form a plasma, which has strong chemical activity and is easily reacted to deposit a desired thin film on a substrate. In order to allow the chemical reaction to proceed at a relatively low temperature, the activity of the plasma is utilized to promote the reaction.
S7, depositing a second stress film 010 on the detector area and the n + doped Si substrate;
wherein, step S7 includes:
referring to fig. 8o and fig. 8p, fig. 8o is a schematic process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 8p is a schematic top view structure diagram of the semiconductor device manufactured by the process corresponding to fig. 8o according to the embodiment of the present invention.
S71, introducing SiH under a second preset condition4And NH3And depositing a second stress film 010 with the thickness of 10nm-20nm on the detector region and the n + doped Si substrate by utilizing a PECVD (plasma enhanced chemical vapor deposition) process.
The second preset condition includes: a second temperature, a second pressure, a radio frequency power, a second gas flow ratio. Wherein the second temperature is 240-280 deg.C, the second pressure is 1500mTorr, the radio frequency power is 200W, and SiH4And NH3Is 0.75.
S8, forming an electrode on the light emitting device region, on the n + -doped Si substrate, and on the second stress film 010. Wherein, step S8 includes:
referring to fig. 8q and 8r specifically, fig. 8q is a schematic process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 8r is a schematic top view structure diagram of the semiconductor device manufactured by the process corresponding to fig. 8q according to the embodiment of the present invention.
S81, evaporating and depositing metal Al on the light-emitting device region, the n + doped Si substrate and the second stress film 010 by using an electron beam evaporation process, wherein the thickness is 10nm-20nm, and forming metal contact;
s82, selectively etching the metal Al in the designated area by using an etching process to form an electrode 011.
The electron beam evaporation is a method of directly evaporating a material by using an electron beam under a vacuum condition, vaporizing the evaporated material and transporting the vaporized material to a substrate, and condensing the vaporized material on the substrate to form a thin film.
The semiconductor device provided by the embodiment of the invention realizes the preparation of the light source device, the waveguide and the detector at the same layer by utilizing the Si-based modified Ge material, thereby reducing the production cost of the device and shortening the process period.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A semiconductor device, comprising:
a Si substrate (001);
a Ge layer (002) provided on the Si substrate (001);
the light source GeSn layer (0031), the light source p + doped Ge layer (0041), the light source p + doped Si layer (0051) and the light source protective layer (0061), wherein the light source GeSn layer (0031), the light source p + doped Ge layer (0041), the light source p + doped Si layer (0051) and the light source protective layer (0061) are sequentially arranged on the Ge layer (002) in a stacking mode from bottom to top;
a waveguide GeSn layer (0032) disposed on the Ge layer (002);
the detector comprises a detector GeSn layer (0033), a detector p + doped Ge layer (0042), a detector p + doped Si layer (0052) and a detector protective layer (0062), wherein the detector GeSn layer (0033), the detector p + doped Ge layer (0042), the detector p + doped Si layer (0052) and the detector protective layer (0062) are sequentially arranged on the Ge layer (002) in a stacking mode from bottom to top;
a first oxide layer (0071) and a second oxide layer (0072) which are both arranged on the Ge layer (002), wherein the first oxide layer (0071) is arranged between the light source GeSn layer (0031) and the waveguide GeSn layer (0032), and the second oxide layer (0072) is arranged between the waveguide GeSn layer (0032) and the detector GeSn layer (0033);
α -Si layer (008) disposed on the waveguide GeSn layer (0032);
a first stress film (009), the first stress film (009) being disposed on and on both sides of the first oxide layer (0071), the second oxide layer (0072), the α -Si layer (008), and both sides of the waveguide GeSn layer (0032);
the second stress film (010), the second stress film (010) is arranged on the detector GeSn layer (0033), the detector p + doped Ge layer (0042), the detector p + doped Si layer (0052), two sides of the detector protection layer (0062) and the detector protection layer (0062);
the electrode (011) is arranged on the Ge layer (002), the light source protection layer (0061) and the second stress film (010).
2. A semiconductor device according to claim 1, characterized in that the Si substrate (001) is formed of an n + -doped Si material with a thickness of 30nm-750 nm.
3. The semiconductor device of claim 1, wherein the light source GeSn layer (0031) and the detector GeSn layer (0033) are each 250nm thick, and the waveguide GeSn layer (0032) is 160nm-200nm thick.
4. The semiconductor device of claim 1, wherein the light source GeSn layer (0031), the waveguide GeSn layer (0032), and the detector GeSn layer (0033) are each formed of a GeSn material having a Sn composition of 3% -5%.
5. The semiconductor device of claim 1, wherein the light source p + doped Ge layer (0041) and the detector p + doped Ge layer (0042) are both 100nm thick.
6. The semiconductor device according to claim 1, characterized in that the light source p + doped Si layer (0051) and the detector p + doped Si layer (0052) are both 300nm thick.
7. The semiconductor device according to claim 1, wherein the light source protection layer (0061) and the detector protection layer (0062) each have a thickness of 900 nm.
8. The semiconductor device according to claim 1, wherein the first oxide layer (0071) and the second oxide layer (0072) are each SiO2The material is formed, and the width of the material is 20nm-50 nm.
9. The semiconductor device of claim 1, wherein the α -Si layer (008) is formed of α -Si material and has a thickness of 800nm-840 nm.
10. The semiconductor device according to claim 1, wherein the first stressor film (009) and the second stressor film (010) are each formed of SiN material and are each 10nm-20nm thick.
CN201811567572.2A 2018-12-20 2018-12-20 Semiconductor device with a plurality of transistors Withdrawn CN111354816A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116666499A (en) * 2023-07-24 2023-08-29 上海铭锟半导体有限公司 Germanium photoelectric detector and method for improving long-wave response thereof through stress memorization

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116666499A (en) * 2023-07-24 2023-08-29 上海铭锟半导体有限公司 Germanium photoelectric detector and method for improving long-wave response thereof through stress memorization
CN116666499B (en) * 2023-07-24 2023-10-20 上海铭锟半导体有限公司 Germanium photoelectric detector and method for improving long-wave response thereof through stress memorization

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