CN111354833A - Monolithic same-layer photoelectric integrated device and preparation method thereof - Google Patents
Monolithic same-layer photoelectric integrated device and preparation method thereof Download PDFInfo
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Abstract
The invention relates to a monolithic same-layer photoelectric integrated device and a preparation method thereof, wherein the preparation method comprises the following steps: sequentially growing an n-type doped Ge layer, an intrinsic GeSn layer, a p-type doped Ge layer, a p-type doped Si layer and a protective layer on an n-type doped Si substrate; etching the protective layer, the p-type doped Si layer, the p-type doped Ge layer and the intrinsic GeSn layer to form a light-emitting device region, a waveguide region, a detector region and an isolation groove; depositing an isolation layer in the isolation trench; depositing a cladding layer on the waveguide region; depositing compressive stress films on the isolation layer, the covering layer and the waveguide region; depositing tensile stress films on the n-type doped Si substrate, the detector area and two sides; and forming electrodes on the light-emitting device region, the n-type doped Si substrate and the tensile stress film. According to the invention, the Si-based modified Ge material is used to realize the preparation of the light-emitting device, the waveguide and the detector at the same layer, and the device has the advantages of novel structure, high integration level and low process cost.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a monolithic same-layer photoelectric integrated device and a preparation method thereof.
Background
Since the concept of integrated optics was proposed by Tamir and Miller in 1966, optoelectronic integration has generated a tremendous social impact from the theoretical development to the technological development. With the development of optical communication, optical information processing, optical computing, optical display, and other disciplines, there is a strong interest in optoelectronic integration with small size, light weight, reliable and stable operation, low power consumption, and high speed operation, and with the development of materials science and advanced manufacturing technology, it is possible to integrate optical, optical/electrical, and electronic components on a single structure or monolithic substrate. In 1972, Somekh s and Yarive a proposed the concept of integrating optical devices and electronic devices on the same semiconductor substrate, and semiconductor photoelectric integration promoted the development of human science and technology again due to its advantages of high integration level, large amount of information, high speed, and the like. The first experimental study of an OEIC (Optoelectronic Integrated Circuit) that integrates an AlGaAs/GaAs laser and a Gunn diode and GaAs MESFET Circuit on a GaAs substrate was reported in 1978 to 1979 by Yariv laboratories of the california institute of science and technology, usa.
However, in the existing manufacturing process, various photonic and electronic components are integrated on the same substrate, and materials meeting the performance requirements of the two components are selected. In order to make different materials complementary, the composite substrate material is optimally combined according to requirements, namely, a heteroepitaxy technology is utilized to epitaxially grow another substrate material film on one substrate material. However, the prepared optical and electronic devices are not compatible in structure, high in production cost and long in process period, and further development of the optical and electronic devices is restricted.
Therefore, it is very important to prepare a monolithic same-layer optoelectronic integrated device which makes the structure between the optical device and the electronic device compatible.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a monolithic same-layer photoelectric integrated device and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of a monolithic same-layer photoelectric integrated device, which comprises the following steps:
sequentially growing an n-type doped Ge layer, an intrinsic GeSn layer, a p-type doped Ge layer, a p-type doped Si layer and a protective layer on an n-type doped Si substrate;
etching the protective layer, the p-type doped Si layer, the p-type doped Ge layer and the intrinsic GeSn layer to form a light-emitting device region, a waveguide region, a detector region and an isolation groove;
depositing an isolation layer in the isolation trench;
depositing a cladding layer on the waveguide region;
depositing compressive stress films on the isolation layer and the two sides, on the covering layer and the two sides, and on the two sides of the waveguide region;
depositing tensile stress films on the n-type doped Si substrate, the detector area and two sides of the detector area;
forming a light emitting device electrode on the light emitting device region and the n-type Ge-doped layer;
and forming a detector electrode on the tensile stress film to finish the preparation of the monolithic same-layer photoelectric integrated device.
In one embodiment of the present invention, sequentially growing an n-type doped Ge layer, an intrinsic GeSn layer, a p-type doped Ge layer, a p-type doped Si layer, and a protection layer on the n-type doped Si substrate includes:
epitaxially growing the n-type Ge-doped layer on the n-type Si-doped substrate by using a CVD (chemical vapor deposition) process at the temperature of 330 ℃;
growing the intrinsic GeSn layer on the n-type Ge-doped layer by utilizing a reduced pressure CVD process at the temperature of 350 ℃;
growing the p-type Ge-doped layer on the intrinsic GeSn layer by using a CVD (chemical vapor deposition) process at the temperature of 160 ℃;
depositing the p-type doped Si layer on the p-type doped Ge layer by using a CVD (chemical vapor deposition) process under the temperature condition of 275-325 ℃;
depositing the protective layer on the p-type doped Si layer using an LPCVD process.
In one embodiment of the present invention, growing the intrinsic GeSn layer on the n-type Ge-doped layer comprises: and controlling the Sn component in the intrinsic GeSn layer to be 3% -5%.
In one embodiment of the present invention, etching the protective layer, the p-type doped Si layer, the p-type doped Ge layer, and the intrinsic GeSn layer comprises:
etching the protective layer and the p-type doped Si layer by introducing HF (hydrogen fluoride) by using a dry etching process;
by using a dry etching process, HF to HNO with the concentration ratio of 1:2.5:10 is adopted3:CH3And etching the p-type Ge-doped layer and the intrinsic GeSn layer by COOH.
In one embodiment of the present invention, depositing an isolation layer in the isolation trench comprises:
introduction of SiH4And O2And depositing the isolation layer in the isolation trench.
In one embodiment of the present invention, a compressive stress film is deposited on the isolation layer, the cladding layer and both sides of the waveguide region at a first temperature, a first pressure, a low frequency power and a first gas flow ratio, wherein the compressive stress film generates a compressive stress on the waveguide, and the compressive stress satisfies the following formula:
the first temperature is related to the compressive stress, Tc is-1.0 × T-463.6;
the relation between the first pressure and the compressive stress is that Tc is 1.03 × P-1363.5;
tc is-0.7 × R-813.4;
the first gas flow rate is in relation to the compressive stress, Tc 24 × X2-167×X-560；
Wherein Tc is the compressive stress in Pa; t is the first temperature in units of; p is the first pressure in mTorr; r is the low-frequency power and has the unit of W; x is the first gas flow ratio.
In one embodiment of the invention, the first temperature is 340 ℃ to 360 ℃, the first pressure is 500mTorr, the low frequency power is 150W, and the first gas flow ratio is 2.
In an embodiment of the present invention, under a second temperature, a second pressure, a radio frequency power, and a second gas flow ratio, a tensile stress film is deposited on the n-type doped Si substrate, the detector region, and both sides of the detector region, where the tensile stress film generates a tensile stress on the detector, and the tensile stress satisfies the following formula:
the second temperature is related to the tensile stress Ts, and Ts is 1.2 × T' -34.1;
the second pressure intensity is related to the tensile stress Ts, and Ts is 0.3 × P' -28.5;
the relation between the radio frequency power and the tensile stress Ts (-2.48 × 10)-6)×R′2+0.26×R′+134.1；
The second gas flow ratio is in relation to the tensile stress Ts, and Ts is-265.4 × X'2+574.6×X′+140.3；
Wherein Ts is the tensile stress with the unit of Pa; t' is the second temperature in units of; p' is the second pressure in mTorr; r' is the radio frequency power in W; x' is the second gas flow ratio.
In one embodiment of the invention, the second temperature is 240 ℃ to 280 ℃, the second pressure is 1500mTorr, the radio frequency power is 200W, and the second gas flow ratio is 0.75.
In an embodiment of the present invention, a monolithic and same-layer optoelectronic integrated device is prepared by the method for preparing a monolithic and same-layer optoelectronic integrated device described in the above embodiment.
Compared with the prior art, the invention has the beneficial effects that:
the monolithic same-layer photoelectric integrated device prepared by the preparation process realizes the same-layer preparation of the light-emitting device, the waveguide and the detector by using the Si-based modified Ge material, and has the advantages of novel structure, high integration level and low process cost.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention;
fig. 2a to 2f, fig. 2g, fig. 2i, fig. 2k, fig. 2p, fig. 2r, and fig. 2v are schematic process flow diagrams of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention;
fig. 2h is a schematic top view of a monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2g according to an embodiment of the present invention;
fig. 2j is a schematic top view of a monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2i according to an embodiment of the present invention;
fig. 2l is a schematic top view of a monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2k according to an embodiment of the present invention;
fig. 2n is a schematic top view of a monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2m according to an embodiment of the present invention;
fig. 2o is a schematic diagram of a right-view structure of a waveguide region wrapped by a compressive stress film according to an embodiment of the present invention;
fig. 2p is a schematic diagram of a right view principle of the intrinsic compressive stress of the compressive stress film on the waveguide according to the embodiment of the present invention;
FIG. 2q is a schematic top view of a waveguide with intrinsic compressive stress generated by a compressive stress film according to an embodiment of the present invention;
fig. 2s is a schematic top view of a monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2r according to an embodiment of the present invention;
fig. 2t is a schematic diagram of a right-view structure of a tensile stress film wrapping a detector region and a substrate according to an embodiment of the present invention;
fig. 2u is a schematic diagram of a right view principle of a tensile stress film generating a tensile stress on a detector according to an embodiment of the present invention;
fig. 2w is a schematic top view of a monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2v according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating transmittance simulation of isolation layers with different thicknesses at different wavelengths according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating transmittance simulations of a device at different wavelengths without a cladding layer and with a cladding layer according to an embodiment of the present invention;
FIG. 5-1 is a schematic top view of a linear tapered transition waveguide region according to an embodiment of the present invention;
fig. 5-2 is a schematic top view of a convex tapered transition waveguide region according to an embodiment of the present invention;
fig. 5-3 are schematic top-view structural diagrams of concave tapered transition waveguide regions according to embodiments of the present invention;
FIG. 6-1 is a schematic diagram illustrating a simulation of the effect of different tapered transition waveguide regions on transmittance at different wavelengths according to an embodiment of the present invention;
fig. 6-2 is a schematic simulation diagram of the effect of different tapered transition waveguide lengths on transmittance under different wavelength conditions according to an embodiment of the present invention;
fig. 7 is a schematic front view of a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention.
In the figure, a 001-n type doped Si substrate, a 002-n type doped Ge layer, a 003-intrinsic GeSn layer, a 0031-light emitting device intrinsic GeSn layer, a 0032-waveguide intrinsic GeSn layer, a 0033-detector intrinsic GeSn layer, a 004-p type doped Ge layer, a 0041-light emitting device p type doped Ge layer, a 0042-detector p type doped Ge layer, a 005-p type doped Si layer, a 0051-light emitting device p type doped Si layer, a 0052-detector p type doped Si layer, a 006-protective layer, a 0061-light emitting device protective layer, a 0062-detector protective layer, a 007-isolation layer, a 008-cladding layer, a 009-compressive stress film, a 010-tensile stress film, a 011-light emitting device electrode, and a 012-detector electrode.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention. As shown in fig. 1, a method for manufacturing a monolithic same-layer optoelectronic integrated device includes:
s1, sequentially growing an n-type Ge-doped layer 002, an intrinsic GeSn layer 003, a p-type Ge-doped layer p + Ge-doped layer 004, a p-type Si-doped layer 005 and a protective layer 006 on an n-type Si-doped substrate 001;
referring to fig. 2a to 2f, fig. 2a to 2f are schematic process flow diagrams of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention.
Wherein, step S1 includes:
s11, epitaxially growing an n-type doped Ge layer 002 on the n-type doped Si substrate 001 by CVD (Chemical Vapor Deposition) process at a temperature of 330 ℃;
referring to fig. 2a and 2b, the n-type doped Si substrate 001 is formed of an n + doped Si material and has a thickness of 30nm to 750 nm; the n-type Ge-doped layer 002 is formed of n + + Ge-doped material with a thickness of 50nm and a doping concentration of 1020cm-3。
The CVD process is a method of forming a thin film by performing a chemical reaction on a substrate using one or more gas-phase compounds or simple substances containing thin film elements.
S12, introducing H2And under the temperature condition of 350 ℃ and below, growing an intrinsic GeSn layer 003 with the thickness of 150nm-200nm on the n-type Ge-doped layer 002 by utilizing a reduced pressure CVD process, and controlling the Sn component in the GeSn material to be 3% -5%.
The intrinsic semiconductor is a pure semiconductor containing no impurities and no lattice defects.
In addition, since the solid solubility of Sn is low, Sn does not overflow due to the Sn component.
The solid solubility refers to the maximum content of solute in solid solution, i.e., the limit solubility of solute in a solvent.
Referring to fig. 2c, step S12 includes:
s121, growing a Ge virtual substrate on the n-type Ge-doped layer 002, wherein the thickness of the Ge virtual substrate is 50 nm;
s122, performing rapid thermal annealing on the Ge virtual substrate to form thermal mismatch, and introducing 0.2% of tensile stress;
among them, thermal annealing is a conventional technique in semiconductor processing, and is generally used to activate doping elements in semiconductor materials and restore amorphous structures caused by ion implantation into complete lattice structures.
S123, with SnCl4As Sn source, GeH4As a Ge source, epitaxially growing Ge on a Ge dummy substrate0.97Sn0.03A layer having a thickness of 150nm to 200 nm.
Wherein, due to Ge0.97Sn0.03Lattice-matched with both Ge-dummy substrates, Ge0.97Sn0.030.2% tensile stress is also present in the epitaxial layer.
S13, growing a p-type Ge-doped layer 004 on the intrinsic GeSn layer 003 by using a CVD process at the temperature of 160 ℃;
referring to FIG. 2d, the p-type Ge-doped layer 004 is made of p + Ge-doped material with a thickness of 100nm and a doping concentration of 3 × 1019cm-3。
S14, growing a p-type doped Si layer 005 on the p-type doped Ge layer 004 by utilizing a CVD process at the temperature of 275-325 ℃;
referring to fig. 2e, the p-type doped Si layer 005 is formed of p + doped Si material with a thickness of 300nm and a doping concentration of 1020cm-3。
S15, depositing a protective layer 006 on the p-type doped Si layer 005 by LPCVD (Low Pressure Chemical Vapor Deposition), as shown in fig. 2 f.
Wherein, step S15 includes:
depositing a first Ti layer on the p-type doped Si layer 005 by an LPCVD (low pressure chemical vapor deposition) process, wherein the thickness of the first Ti layer is 300 nm;
depositing an Al layer on the first Ti layer by using an LPCVD (low pressure chemical vapor deposition) process, wherein the thickness of the Al layer is 300 nm;
and depositing a second Ti layer on the Al layer by an LPCVD process, wherein the thickness of the second Ti layer is 300 nm.
The basic principle of the LPCVD process is to activate one or more gaseous substances with heat energy under a relatively low pressure to cause thermal decomposition or chemical reaction, and deposit the substances on the surface of a material to form a desired thin film.
S2, an etching protective layer 006, a p-type doped Si layer 005, a p-type doped Ge layer 004 and an intrinsic GeSn layer 003 form a light-emitting device region, a waveguide region and a detector region which are sequentially isolated;
referring to fig. 2g and fig. 2h specifically, fig. 2g is a schematic process flow diagram of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention, and fig. 2h is a schematic top view structure diagram of the monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2g according to the embodiment of the present invention.
Wherein, step S2 includes:
s21, introducing the HF etching protective layer 006 and the p-type doped Si layer 005 by using a dry etching process;
the dry etching refers to a technique of performing thin film etching using plasma.
S22, dry etching process is adopted, and HF: HNO with concentration ratio of 1:2.5:10 is adopted3:CH3And etching the p-type Ge-doped layer 004 and the intrinsic GeSn layer 003 by COOH to form a light-emitting device region, a waveguide region, a detector region and an isolation groove which are isolated in sequence.
Wherein the light emitting device region includes: a luminescent device intrinsic GeSn layer 0031, a luminescent device p-type doped Ge layer 0041, a luminescent device p-type doped Si layer 0051 and a luminescent device protective layer 0061; the waveguide region includes a waveguide intrinsic GeSn layer 0032; the detector region includes: a detector intrinsic GeSn layer 0033, a detector p-type doped Ge layer 0042, a detector p-type doped Si layer 0052 and a detector protection layer 0062.
In addition, isolation grooves are arranged between the waveguide region and the light-emitting device region and between the waveguide region and the detector region.
In addition, the light emitting device region, the n-type doped Si substrate 001, and the n-type doped Ge layer 002 collectively form a laser.
S3, introducing SiH4And O2Depositing an isolation layer 007 in the isolation trench;
wherein the isolation layer 007 is made of SiO2Forming a material with the thickness of 20nm-50nm, preferably 20 nm;
referring to fig. 2i and fig. 2j specifically, fig. 2i is a schematic process flow diagram of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention, and fig. 2j is a schematic top view structure diagram of the monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2i according to the embodiment of the present invention.
Wherein, SiO2The isolation layer 007 isolates the light-emitting device region from the waveguide region and isolates the waveguide region from the detector region, so that the electrical isolation effect is achieved, and the photoelectric devices at two ends are prevented from generating a parasitic effect.
Fig. 3 is a schematic diagram illustrating transmittance simulation of isolation layers with different thicknesses at different wavelengths according to an embodiment of the present invention, where as shown in fig. 3, the longer the wavelength is, the less the influence of the interface is; the effect of the substantially 20nm thick spacer layer 007 on light transmission is substantially the same as that without the spacer layer, with little substantially negligible effect on the overall light transmission; when the spacer layer 007 is gradually thickened, the transmittance is gradually decreased, and the transmittance is more decreased as the thickness is increased.
The above conclusion is because the scattering loss and reflection of the spacer layer become larger and larger with increasing thickness, resulting in an increase in coupling loss. At a wavelength of about 1.75 μm, the coupling efficiency between the waveguide and a device without and with the isolation layer 007 and with a thickness of 20nm of the isolation layer 007 is substantially 84% -85%, while the coupling efficiency with a thickness of 50nm of the isolation layer 007 is substantially 81% -82%. This indicates that the effect of the spacer layer 007 on the loss between the device and the waveguide is not negligible.
S4, depositing a covering layer 008 on the waveguide region;
specifically, referring to fig. 2k and fig. 2l, fig. 2k is a schematic process flow diagram of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention, and fig. 2l is a schematic top view structure diagram of the monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2k according to the embodiment of the present invention.
Further, a covering layer 008 is added on the waveguide region, wherein the covering layer 008 is formed by α -Si material and has a thickness of 800nm-840nm, fig. 4 is a simulation diagram of transmittance of the device under different wavelengths when no covering layer and a covering layer are provided according to the embodiment of the present invention, and as shown in fig. 4, the addition of the covering layer 008 can reduce coupling loss, which is substantially the same as the case of coupling the optical fiber with the device, and can reduce loss compared with the sidewall design.
In addition, the waveguide region comprises a conical transition waveguide region and a rectangular waveguide region, and two sides of the conical transition waveguide region can be in different shapes, such as a linear type, a convex type and a concave type. As shown in figure 5-1 of the drawings,
fig. 5-1 is a schematic top-view structure diagram of a linear tapered transition waveguide region provided in an embodiment of the present invention, as shown in fig. 5-2, fig. 5-2 is a schematic top-view structure diagram of a convex tapered transition waveguide region provided in an embodiment of the present invention, as shown in fig. 5-3, and fig. 5-3 is a schematic top-view structure diagram of a concave tapered transition waveguide region provided in an embodiment of the present invention. The longer the length of the tapered transition waveguide, the smaller the change size in the propagation direction, but the nonlinear increase, and the loss decreases less and less with the increase of the length, so the transmission loss of light is less affected.
Fig. 6-1 is a schematic diagram illustrating simulation of influence of different shapes of tapered transition waveguide regions on the projection degree under different wavelength conditions according to an embodiment of the present invention, where as shown in fig. 6-1, a concave transition waveguide increases transmission loss, and a convex transition waveguide is advantageous in fixed transition length transmission, and a longer transition wavelength is selected as much as possible under the permission of practical application.
Fig. 6-2 is a schematic diagram illustrating simulation of influence of different tapered transition waveguide lengths on transmittance under different wavelength conditions according to an embodiment of the present invention, as shown in fig. 6-2, a tapered transition waveguide length L ranges from 5 μm to 15 μm, and transmittance is the best when the tapered transition waveguide length L is 15 μm, but in a device design process, the tapered transition waveguide length L is not too long, and therefore the tapered transition waveguide length L is preferably 10 μm.
S5, depositing compressive stress films 009 on the isolating layer 007, the covering layer 008 and two sides of the waveguide region;
referring to fig. 2m and fig. 2n specifically, fig. 2m is a schematic process flow diagram of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention, and fig. 2n is a schematic top view structure diagram of the monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2m according to the embodiment of the present invention.
Wherein, step S5 includes:
introducing SiH under a first preset condition4And NH3A compressive stress film 009 with a thickness of 10-20nm is deposited on and over the spacer layer 007, on and over the cladding layer 008, and on and over the waveguide region by a PECVD (Plasma Enhanced chemical vapor Deposition) process.
Referring to fig. 2o, fig. 2o is a schematic diagram of a right-view structure of a waveguide region wrapped by a compressive stress film according to an embodiment of the present invention.
The first preset condition includes: a first temperature, a first pressure, a low frequency power, a first gas flow ratio.
The PECVD process is a process in which a gas containing atoms constituting a thin film is ionized by microwaves or radio frequencies to locally form a plasma, which has strong chemical activity and is easily reacted to deposit a desired thin film on a substrate. In order to allow the chemical reaction to proceed at a relatively low temperature, the activity of the plasma is utilized to promote the reaction.
The compressive stress film 009 generates compressive stress to the waveguide.
Referring specifically to fig. 2p and 2q, wherein,
fig. 2p and 2q are a schematic diagram of a right-view principle and a schematic diagram of a top-view principle of intrinsic compressive stress of the compressive stress film on the waveguide provided by the embodiment of the present invention, respectively, as shown in fig. 2p and 2q, the high-energy particle bombardment is introduced by using the low-frequency power source, so that atoms or ions of the compressive stress film 009 are combined or redistributed, that is, the compressive stress film 009 becomes compressive and is stretched or expanded, thereby generating intrinsic compressive stress on the waveguide.
The intrinsic stress is also called internal stress, and is generated in the film deposition growth environment (such as temperature, pressure, gas flow rate, etc.). If the film has a tendency to shrink along the film surface, the matrix generates tensile stress on the film, and conversely, the expansion tendency of the film along the film surface causes compressive stress. The intrinsic stress is closely related to the preparation method and the process of the thin film, and is different with the difference of the thin film and the base material.
Under the condition that other process conditions are not changed, the higher the first temperature is, the larger the formed waveguide compressive stress is; under the condition that other process conditions are not changed, the higher the first pressure is, the smaller the formed waveguide compressive stress is; under the condition that other process conditions are unchanged, the higher the low-frequency power is, the higher the formed waveguide compressive stress is. And the magnitude of the pressure stress has a certain linear relation with the first temperature, the first pressure, the low-frequency power and the first gas flow rate. The compressive stress satisfies the following formula:
the first temperature is related to the compressive stress, Tc is-1.0 × T-463.6;
the first pressure intensity is related to the pressure stress, Tc is 1.03 × P-1363.5;
tc is-0.7 × R-813.4;
the first gas flow rate is related to the compressive stress, Tc 24 × X2-167×X-560；
Wherein Tc is compressive stress in Pa; t is a first temperature in units of; p is a first pressure in mTorr; r is low-frequency power and has the unit of W; x is the first gas flow ratio.
Wherein the first temperature is 340-360 deg.C, the first pressure is 500mTorr, the low-frequency power is 150W, and the SiH4And NH3Has a first gas flow ratio of 2.
S6, depositing a tensile stress film 010 on the detector area and the substrate;
wherein, step S6 includes:
referring to fig. 2r and fig. 2s specifically, fig. 2r is a schematic process flow diagram of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention, and fig. 2s is a schematic top view structure diagram of the monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2r according to the embodiment of the present invention.
Wherein, step S6 includes:
introducing SiH under a second preset condition4And NH3And depositing a tensile stress film 010 with the thickness of 10nm-20nm on the detector area and the substrate by utilizing a PECVD process.
Referring to fig. 2t, fig. 2t is a schematic diagram of a right-view structure of the tensile stress film wrapping the detector region and the n-type doped Si substrate according to an embodiment of the present invention.
The second preset condition includes: a second temperature, a second pressure, a radio frequency power, a second gas flow ratio.
The tensile stress film 010 generates tensile stress to the detector.
Specifically, referring to fig. 2u, fig. 2u is a schematic diagram of a right-view principle that the tensile stress film generates tensile stress on the detector according to the embodiment of the present invention, as shown in fig. 2u, a radio frequency power source is used to introduce high-energy particle bombardment, so that atoms or ions of the tensile stress film 010 are combined or redistributed, that is, the tensile stress film 010 becomes tensile, thereby generating intrinsic tensile stress on the detector.
Under the condition that other process conditions are not changed, the higher the second temperature is, the larger the formed detector tensile stress is; under the condition that other process conditions are not changed, the higher the second pressure, the smaller the tensile stress of the formed detector is; under the condition that other process conditions are unchanged, the larger the radio frequency power is, the larger the tensile stress of the formed detector is. And the magnitude of the tensile stress has a certain linear relation with the second temperature, the second pressure, the radio frequency power and the second gas flow rate. The tensile stress satisfies the following formula:
the second temperature is related to the tensile stress Ts, wherein Ts is 1.2 × T' -34.1;
the second pressure is related to the tensile stress Ts, wherein Ts is 0.3 × P' -28.5;
radio frequency power and tensile stress Ts relation, Ts (-2.48 × 10)-6)×R′2+0.26×R′+134.1；
The second gas flow ratio is related to the tensile stress Ts, wherein Ts is-265.4 × X'2+574.6×X′+140.3；
Wherein Ts is tensile stress with the unit of Pa; t' is a second temperature in units of; p' is a second pressure in mTorr; r' is radio frequency power and has the unit of W; and X' is the second gas flow ratio.
Wherein the second temperature is 240-280 deg.C, the second pressure is 1500mTorr, the radio frequency power is 200W, and SiH4And NH3Is 0.75.
Because the compressive stress film 009 wraps the waveguide region, the stress directly acts on the waveguide, so that the waveguide is subjected to the compressive stress, and the forbidden bandwidth of the waveguide is increased; because the tensile stress film 010 wraps the detector area and the substrate, the stress directly acts on the detector, so that the detector generates tensile stress along the direction vertical to the optical transmission direction, and the forbidden bandwidth of the detector is reduced. Thereby satisfying the forbidden band relation: eg waveguide > Eg light emitting device > Eg detector, where Eg represents the forbidden band width. The integration of the light-emitting device, the waveguide and the detecting device is realized on the same layer by modulating the forbidden band relation of the light-emitting device, the waveguide and the detector, and the device has the advantages of novel structure, high integration level and low process cost.
And S7, forming a light-emitting device electrode on the light-emitting device area and the n-type Ge-doped layer, and forming a detector electrode on the tensile stress film.
Wherein, step S7 includes:
referring to fig. 2v and fig. 2w specifically, fig. 2v is a schematic process flow diagram of a method for manufacturing a monolithic same-layer optoelectronic integrated device according to an embodiment of the present invention, and fig. 2w is a schematic top view structure diagram of the monolithic same-layer optoelectronic integrated device manufactured by the process corresponding to fig. 2v according to the embodiment of the present invention.
S71, evaporating and depositing metal Al on the light-emitting device area, the n-type Ge-doped layer and the tensile stress film 010 by using an electron beam evaporation process, wherein the thickness is 10nm-20nm, and forming metal contact;
s72, selectively etching the metal Al in the designated area by using an etching process to form a luminescent device electrode 011 and a detector electrode 012 respectively.
The electron beam evaporation is a method of directly evaporating a material by using an electron beam under a vacuum condition, vaporizing the evaporated material and transporting the vaporized material to a substrate, and condensing the vaporized material on the substrate to form a thin film.
Fig. 7 is a schematic front view structure diagram of a monolithic homolayer optoelectronic integrated device according to an embodiment of the present invention, where the monolithic homolayer optoelectronic integrated device is fabricated by the above monolithic homolayer optoelectronic integrated device fabrication method, and as shown in the figure, the monolithic homolayer optoelectronic integrated device includes an n-type doped Si substrate 001, an n-type doped Ge layer 002, a light emitting device intrinsic GeSn layer 0031, a waveguide intrinsic GeSn layer 0032, a detector intrinsic GeSn layer 0033, a light emitting device p-type doped Ge layer 0041, a detector p-type doped Ge layer 0042, a light emitting device p-type doped Si layer 0051, a detector p-type doped Si layer 0052, a light emitting device protective layer 0061, a detector protective layer 0062, an isolation layer 007, a cladding layer 008, a compressive stress film 009, a tensile stress film 010, a light emitting device electrode 011, a detector electrode 012, an n-type doped Si substrate 001, an n-type doped Ge layer 002, a light emitting device intrinsic GeSn layer 0031, a cladding, the photoelectric integrated device comprises a waveguide intrinsic GeSn layer 0032, a detector intrinsic GeSn layer 0033, a light-emitting device p-type doped Ge layer 0041, a detector p-type doped Ge layer 0042, a light-emitting device p-type doped Si layer 0051, a detector p-type doped Si layer 0052, a light-emitting device protective layer 0061, a detector protective layer 0062, an isolation layer 007, a covering layer 008, a compressive stress film 009, a tensile stress film 010, a light-emitting device electrode 011 and a detector electrode 012 which are vertically distributed from bottom to top to form a multilayer structure, so that the photoelectric integrated device with the same layer on a single chip is formed.
The n-type doped Si substrate 001 is formed by an n + doped Si material, and the thickness is 30nm-750 nm; the n-type Ge-doped layer 002 is formed of an n + + Ge-doped material and has a thickness of 50 nm; the thickness of the luminescent device intrinsic GeSn layer 0031, the waveguide intrinsic GeSn layer 0032 and the detector intrinsic GeSn layer 0033 are 250 nm; the light-emitting device p-type doped Ge layer 0041 and the detector p-type doped Ge layer 0042 are both formed by p + doped Ge materials, and the thicknesses of the p + doped Ge layers are both 100 nm; the p-type doped Si layer 0051 of the light-emitting device and the p-type doped Si layer 0052 of the detector are both formed by p + doped Si materials, and the thicknesses of the p-type doped Si layers are 300 nm; the thicknesses of the light-emitting device protection layer 0061 and the detector protection layer 0062 are both 900 nm; the thickness of the isolation layer 007 is 20nm-50 nm; the thickness of the covering layer 008 is 50nm-90 nm; the thickness of the compressive stress film 009 and the thickness of the tensile stress film 010 are both 10nm-20 nm; the light-emitting device electrode 011 and the probe electrode 012 are each formed of metal Al.
The monolithic same-layer photoelectric integrated device prepared by the preparation process provided by the embodiment of the invention utilizes the Si-based modified Ge material to realize the same-layer preparation of the light-emitting device, the waveguide and the detector, thereby reducing the production cost of the device and shortening the process period.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A method for preparing a monolithic same-layer photoelectric integrated device is characterized by comprising the following steps:
sequentially growing an n-type doped Ge layer, an intrinsic GeSn layer, a p-type doped Ge layer, a p-type doped Si layer and a protective layer on an n-type doped Si substrate;
etching the protective layer, the p-type doped Si layer, the p-type doped Ge layer and the intrinsic GeSn layer to form a light-emitting device region, a waveguide region, a detector region and an isolation groove;
depositing an isolation layer in the isolation trench;
depositing a cladding layer on the waveguide region;
depositing compressive stress films on the isolation layer and the two sides, on the covering layer and the two sides, and on the two sides of the waveguide region;
depositing tensile stress films on the n-type doped Si substrate, the detector area and two sides of the detector area;
forming a light emitting device electrode on the light emitting device region and the n-type Ge-doped layer;
and forming a detector electrode on the tensile stress film to finish the preparation of the monolithic same-layer photoelectric integrated device.
2. The method for manufacturing a monolithic same-layer optoelectronic integrated device according to claim 1, wherein sequentially growing an n-type doped Ge layer, an intrinsic GeSn layer, a p-type doped Ge layer, a p-type doped Si layer, and a protection layer on the n-type doped Si substrate comprises:
epitaxially growing the n-type Ge-doped layer on the n-type Si-doped substrate by using a CVD (chemical vapor deposition) process at the temperature of 330 ℃;
growing the intrinsic GeSn layer on the n-type Ge-doped layer by utilizing a reduced pressure CVD process at the temperature of 350 ℃;
growing the p-type Ge-doped layer on the intrinsic GeSn layer by using a CVD (chemical vapor deposition) process at the temperature of 160 ℃;
depositing the p-type doped Si layer on the p-type doped Ge layer by using a CVD (chemical vapor deposition) process under the temperature condition of 275-325 ℃;
depositing the protective layer on the p-type doped Si layer using an LPCVD process.
3. The method of claim 2, wherein growing the intrinsic GeSn layer on the n-type Ge-doped layer comprises: and controlling the Sn component in the intrinsic GeSn layer to be 3% -5%.
4. The method of claim 1, wherein etching the protective layer, the p-doped Si layer, the p-doped Ge layer, and the intrinsic GeSn layer comprises:
etching the protective layer and the p-type doped Si layer by introducing HF (hydrogen fluoride) by using a dry etching process;
by using a dry etching process, HF to HNO with the concentration ratio of 1:2.5:10 is adopted3:CH3And etching the p-type Ge-doped layer and the intrinsic GeSn layer by COOH.
5. The method of claim 1, wherein depositing an isolation layer in the isolation trench comprises:
introduction of SiH4And O2And depositing the isolation layer in the isolation trench.
6. The method for manufacturing a monolithic same-layer optoelectronic integrated device according to claim 1, wherein a compressive stress film is deposited on the isolation layer, the cladding layer and both sides of the waveguide region at a first temperature, a first pressure, a low-frequency power and a first gas flow ratio, wherein the compressive stress film generates a compressive stress on the waveguide, and the compressive stress satisfies the following formula:
the first temperature is related to the compressive stress, Tc is-1.0 × T-463.6;
the relation between the first pressure and the compressive stress is that Tc is 1.03 × P-1363.5;
tc is-0.7 × R-813.4;
the first gas flow rate is in relation to the compressive stress, Tc 24 × X2-167×X-560；
Wherein Tc is the compressive stress in Pa; t is the first temperature in units of; p is the first pressure in mTorr; r is the low-frequency power and has the unit of W; x is the first gas flow ratio.
7. The method as claimed in claim 6, wherein the first temperature is 340 ℃ -360 ℃, the first pressure is 500mTorr, the low frequency power is 150W, and the first gas flow ratio is 2.
8. The method for manufacturing a monolithic same-layer optoelectronic integrated device according to claim 1, wherein under a second temperature, a second pressure, a radio frequency power and a second gas flow ratio, a tensile stress film is deposited on the n-type doped Si substrate, the detector region and both sides of the detector region, wherein the tensile stress film generates a tensile stress on the detector, and the tensile stress satisfies the following formula:
the second temperature is related to the tensile stress Ts, and Ts is 1.2 × T' -34.1;
the second pressure intensity is related to the tensile stress Ts, and Ts is 0.3 × P' -28.5;
the relation between the radio frequency power and the tensile stress Ts (-2.48 × 10)-6)×R′2+0.26×R′+134.1；
The second gas flow ratio is in relation to the tensile stress Ts, and Ts is-265.4 × X'2+574.6×X′+140.3；
Wherein Ts is the tensile stress with the unit of Pa; t' is the second temperature in units of; p' is the second pressure in mTorr; r' is the radio frequency power in W; x' is the second gas flow ratio.
9. The method of claim 8, wherein the second temperature is 240 ℃ to 280 ℃, the second pressure is 1500mTorr, the RF power is 200W, and the second gas flow ratio is 0.75.
10. A monolithic homolayer optoelectronic integrated device, wherein the monolithic homolayer optoelectronic integrated device is prepared by the method for preparing a monolithic homolayer optoelectronic integrated device according to any one of claims 1 to 9.
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