CN111354778A - 半导体装置及其形成方法 - Google Patents

半导体装置及其形成方法 Download PDF

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CN111354778A
CN111354778A CN201910788574.2A CN201910788574A CN111354778A CN 111354778 A CN111354778 A CN 111354778A CN 201910788574 A CN201910788574 A CN 201910788574A CN 111354778 A CN111354778 A CN 111354778A
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type well
semiconductor substrate
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CN111354778B (zh
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席德·内亚兹·依曼
陈柏安
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Nuvoton Technology Corp
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Abstract

一种半导体装置及其形成方法，该形成方法包括提供半导体基板、于半导体基板中形成第一N型注入区与第二N型注入区。第一N型注入区与第二N型注入区被半导体基板的一部分隔开。上述方法亦包括于半导体基板中形成第一P型注入区、对半导体基板进行热处理工艺以于半导体基板中形成P型阱与N型阱。N型阱具有第一部分、第二部分以及第三部分，第三部分位于第一部分与第二部分之间，第三部分的掺杂浓度低于第一部分的掺杂浓度与第二部分的掺杂浓度。

Description

半导体装置及其形成方法
技术领域
本发明实施例关于一种半导体装置，且特别有关于一种横向扩散金属氧化物半导体(lateral diffused metal oxide semiconductor，LDMOS)场效应晶体管及其形成方法。
背景技术
半导体装置已广泛地使用于各种电子产品中，举例而言，诸如个人电脑、手机以及数码相机等。半导体装置的制造通常是藉由在半导体基板上形成绝缘层或介电层、导电层以及半导体层，接着使用光刻工艺图案化所形成的各种材料层，藉以在此半导体基板之上形成电路零件及组件。
现有的半导体装置及其形成方法大抵上可满足一般需求，然而随着装置的微型化，其并非在各方面皆令人满意。
发明内容
本发明实施例包括一种半导体装置的形成方法。上述方法包括提供半导体基板、于上述半导体基板中形成第一N型注入区与第二N型注入区。上述第一N型注入区与上述第二N型注入区被上述半导体基板的一部分隔开。上述方法亦包括于上述半导体基板中形成第一P型注入区。上述第一N型注入区位于上述第二N型注入区与上述第一P型注入区之间。上述方法亦包括对上述半导体基板进行热处理工艺以于上述半导体基板中形成P型阱与N型阱。上述N型阱具有第一部分、第二部分以及第三部分，上述第一部分位于上述第三部分与上述P型阱之间，上述第三部分位于上述第一部分与上述第二部分之间，上述第三部分的掺杂浓度低于上述第一部分的掺杂浓度与上述第二部分的掺杂浓度。上述方法亦包括形成栅极介电层于上述半导体基板上，以及形成栅极电极于上述栅极介电层上。上述栅极介电层覆盖上述P型阱与上述N型阱。
本发明实施例亦包括一种半导体装置。上述半导体装置包括半导体基板、位于上述半导体基板中的P型阱与N型阱。上述N型阱相邻于上述P型阱。上述N型阱具有第一部分、第二部分以及第三部分。上述第一部分位于上述第三部分与上述P型阱之间。上述第三部分位于上述第一部分与上述第二部分之间。上述第三部分的掺杂浓度低于上述第一部分的掺杂浓度与上述第二部分的掺杂浓度。上述半导体装置亦包括位于上述P型阱中的N型源极区、位于上述N型阱中的N型漏极区、位于上述半导体基板上的栅极介电层以及位于上述栅极介电层上的栅极电极。上述栅极介电层部分覆盖上述P型阱与上述N型阱。上述N型阱的第三部分与上述N型阱的第一部分之间具有第一界面，且上述第一界面与上述栅极电极的侧壁对齐。
附图说明
以下将配合所附图式详述本发明实施例。应注意的是，各种特征部件并未按照比例绘制且仅用以说明例示。事实上，元件的尺寸可能经放大或缩小，以清楚地表现出本发明实施例的技术特征。
图1A、图1B、图1C、图1D、图1E、图1F、图1G、图1H、图1I、图1J以及图1K为一系列的工艺剖面图，其绘示出本发明一些实施例的半导体装置的形成方法。
图1C’绘示出本发明一些实施例的N型阱的掺杂浓度曲线图。
图2绘示出本发明一些实施例的半导体装置的剖面图。
图3绘示出本发明一些实施例的半导体装置的剖面图。
图4绘示出本发明一些实施例的半导体装置的剖面图。
图5绘示出本发明一些实施例的半导体装置的剖面图。
附图标号：
10、20、30、40、50～半导体装置；
100～半导体基板；
100a～半导体基板的一部分；
102～第一掩膜；
102a～第一开口；
102b～第二开口；
104～第一N型注入区；
106～第二N型注入区；
108～第二掩膜；
108a～第三开口；
110～第一P型注入区；
112～P型阱；
114～N型阱；
114a～N型阱的第一部分；
114b～N型阱的第二部分；
114c～N型阱的第三部分；
116～N型掺杂区；
118～N型掺杂区；
120a、120b～氧化物；
122～栅极介电层；
124～栅极电极；
124S～栅极电极的侧壁
126～P型掺杂区；
128～栅极侧壁间隔物；
130～N型漏极区；
132～N型源极区；
134～P型掺杂区；
I1～第一界面；
I2～第二界面；
A1～热处理；
D1、D2、D3～深度；
P1、P2、P3～位置；
W1、W2、W3～宽度；
S1～间距。
具体实施方式
以下的揭露内容提供许多不同的实施例或范例以实施本案的不同特征。以下的揭露内容叙述各个构件及其排列方式的特定范例，以简化说明。当然，这些特定的范例并非用以限定。例如，若是本发明实施例叙述了一第一特征部件形成于一第二特征部件之上或上方，即表示其可能包含上述第一特征部件与上述第二特征部件是直接接触的实施例，亦可能包含了有附加特征部件形成于上述第一特征部件与上述第二特征部件之间，而使上述第一特征部件与第二特征部件可能未直接接触的实施例。
应理解的是，额外的操作步骤可实施于所述方法之前、之间或之后，且在所述方法的其他实施例中，部分的操作步骤可被取代或省略。
此外，其中可能用到与空间相关用词，例如「在…下方」、「下方」、「较低的」、「上方」、「较高的」及类似的用词，这些空间相关用词是为了便于描述图示中一个(些)元件或特征部件与另一个(些)元件或特征部件之间的关系，这些空间相关用词包括使用中或操作中的装置的不同方位，以及图式中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，则其中所使用的空间相关形容词也将依转向后的方位来解释。
除非另外定义，在此使用的全部用语(包括技术及科学用语)具有与本发明的本领域技术人员所通常理解的相同涵义。能理解的是，这些用语，例如在通常使用的字典中定义的用语，应被解读成具有与相关技术及本发明的背景或上下文一致的意思，而不应以一理想化或过度正式的方式解读，除非在本发明实施例有特别定义。
以下所揭露的不同实施例可能重复使用相同的参考符号及/或标记。这些重复是为了简化与清晰的目的，并非用以限定所讨论的不同实施例及/或结构之间有特定的关系。
本发明实施例的半导体装置的N型阱具有第一部分、第二部分以及位于上述第一部分与上述第二部分之间的第三部分，上述N型阱之第三部分的掺杂浓度低于上述N型阱之第一部分的掺杂浓度与上述N型阱之第二部分的掺杂浓度，因此可提升半导体装置的击穿电压。此外，根据本发明实施例，使用单一注入掩膜进行离子注入工艺于半导体基板中形成被上述半导体基板的一部分隔开的第一N型注入区与第二N型注入区，因此可在不增加注入掩膜的情况下形成上述N型阱的第一部分、第二部分与第三部分，藉此提升半导体装置的击穿电压而同时不增加半导体装置的制造成本。
首先，请参照图1A，根据本发明一些实施例，提供半导体基板100。半导体基板100可为硅基板，但本发明实施例并非以此为限。在一些实施例中，半导体基板100包括外延半导体层。在一些实施例中，半导体基板100可包括单晶基板、多层基板(multi-layersubstrate)、梯度基板(gradient substrate)、其他适当的基板或上述的组合。在一些实施例中，半导体基板100为P型半导体基板。举例而言，P型半导体基板100可包括P型掺质(例如:硼、铝、镓、铟、铊、其他适当的P型掺质或上述的组合)。根据一些实施例，于半导体基板100上形成第一掩膜102。在一些实施例中，第一掩膜102具有第一开口102a与第二开口102b，且半导体基板100的顶表面的一部分经由第一开口102a与第二开口102b露出。
在一些实施例中，如图1A所示，第一开口102a与第二开口102b之间具有间距S1，间距S1位于半导体基板100的部分100a之上。当间距S1太大时，可能会导致后文所述的N型注入区104和106两区经过热处理工艺后(例如:后文所述的热处理工艺A1)无法连接在一起而降低半导体装置的效能。在一些实施例中，间距S1小于12微米(例如:间距S1为2至10微米)。
如图1A所示，第一开口102a可具有第一宽度W1，第二开口102b可具有第二宽度W2。第一宽度W1可等于、大于或小于宽度W2。当第一宽度W1太大且第二宽度W2太小时，可能会使后续所形成的N型阱(例如:图1K中的N型阱114)的掺杂浓度较低的部分太靠近N型漏极区(例如:图1K中的N型漏极区130)，这可能会导致电场分布不均匀而降低半导体装置的效能。在一些实施例中，第一宽度W1与第二宽度W2之间的比值(亦即，W1/W2)为0.2至1。
在一些实施例中，可使用如旋转涂布(spin-on coating)的方式形成光阻层于半导体基板100上，接着进行软烘烤(soft baking)、曝光(exposure)、曝光后烘烤(postexposure baking)以及显影(developing)等步骤图案化上述光阻层以形成具有第一开口102a与第二开口102b的第一掩膜102。在一些实施例中，第一掩膜102可由如氧化硅或氮化硅等硬掩膜材料所形成，且形成第一掩膜102的工艺可包括沉积工艺、光刻工艺、蚀刻工艺、其他适当的工艺或上述的组合。
接着，如图1A所示，根据一些实施例，于半导体基板100中形成第一N型注入区104与第二N型注入区106。于后续的步骤中，第一N型注入区104与第二N型注入区106可被用来在半导体基板100中形成N型阱(例如:图1D中的N型阱114)，于后文将对此进行详细说明。
在一些实施例中，第一N型注入区104与第二N型注入区106包括N型掺质(例如:氮、磷、砷、锑、铋、其他适当的N型掺质或上述的组合)。举例而言，可使用离子注入工艺将前述的N型掺质注入至半导体基板100中而于半导体基板100中形成第一N型注入区104与第二N型注入区106。在一些实施例中，第一掩膜102于上述离子注入工艺中充当注入掩膜，且上述N型掺质可经由第一掩膜102的第一开口102a与第二开口102b进入半导体基板100中。
在一些实施例中，如图1A所示，半导体基板100的部分100a位于第一N型注入区104与第二N型注入区106之间。在一些实施例中，第一N型注入区104与第二N型注入区106被半导体基板100的部分100a分隔开。
接着，请参照图1B，根据一些实施例，移除第一掩膜102。在一些实施例中，第一掩膜102是由光阻所形成，因此可使用如等离子体灰化的方式移除第一掩膜102。在一些实施例中，第一掩膜102是由如氧化硅或氮化硅等硬掩膜材料所形成，因此可使用蚀刻工艺移除第一掩膜102。
接着，请参照图1B，根据一些实施例，于半导体基板100上形成第二掩膜108，第二掩膜108覆盖第一N型注入区104与第二N型注入区106。在一些实施例中，第二掩膜108具有第三开口108a，且半导体基板100的顶表面的一部分经由第三开口108a露出。第二掩膜108的材料与形成方法可相同或类似于前述的第一掩膜102，为了简明起见，于此将不再详细说明。
接着，如图1B所示，根据一些实施例，于半导体基板100中形成第一P型注入区110。于后续的步骤中，第一P型注入区110可被用来在半导体基板100中形成P型阱(例如:图1D中的P型阱112)，于后文将对此进行详细说明。
在一些实施例中，如图1B所示，第一N型注入区104位于第二N型注入区106与第一P型注入区110之间。在一些实施例中，如图1B所示，第一P型注入区110的深度可大抵上等于第一N型注入区104的深度与第二N型注入区106的深度。
在一些实施例中，第一P型注入区110包括P型掺质(例如:硼、铝、镓、铟、铊、其他适当的P型掺质或上述的组合)。举例而言，可使用离子注入工艺将前述的P型掺质注入至半导体基板100中而于半导体基板100中形成第一P型注入区110。在一些实施例中，第二掩膜108于上述离子注入工艺中充当注入掩膜，且上述P型掺质可经由第二掩膜108的第三开口108a进入半导体基板100中。
接着，如图1C所示，根据一些实施例，移除第二掩膜108。在一些实施例中，第二掩膜108是由光阻所形成，因此可使用如等离子体灰化的方式移除第二掩膜108。在一些实施例中，第二掩膜108是由如氧化硅或氮化硅等硬掩膜材料所形成，因此可使用蚀刻工艺移除第二掩膜108。
接着，如图1C所示，根据一些实施例，对半导体基板100进行热处理工艺A1，以于半导体基板100中形成P型阱112以及与P型阱112相邻的N型阱114。在一些实施例中，热处理工艺A1可活化第一P型注入区110中的P型掺质以及第一N型注入区104与第二N型注入区106中的N型掺质。
举例而言，热处理工艺A1可包括炉管退火工艺(furnace annealing process)、其他适当的热处理工艺或上述的组合。在一些实施例中，热处理工艺A1的热处理温度为900℃至1250℃，且所对应的热处理时间为120分钟至600分钟。
在一些实施例中，P型阱112的掺杂浓度大于P型半导体基板100的掺杂浓度。举例而言，P型阱112的掺杂浓度可为1E16至1E18cm-3。
在一些实施例中，如图1C所示，N型阱114具有第一部分114a、第二部分114b以及第三部分114c。在一些实施例中，N型阱114的第一部分114a位于P型阱112与N型阱114的第三部分114c之间，N型阱114的第三部分114c位于N型阱114的第一部分114a与第二部分114b之间。
在一些实施例中，N型阱114的第一部分114a对应于第一N型注入区104，N型阱114的第二部分114b对应于第二N型注入区106，N型阱114的第三部分114c对应于半导体基板100的部分100a。如图1C所示，N型阱114的第一部分114a与第三部分114c之间可具有第一界面I1，N型阱114的第二部分114b与第三部分114c之间可具有第二界面I2。
在一些实施例中，N型阱114的第三部分114c的掺杂浓度(例如:平均掺杂浓度)低于第一部分114a的掺杂浓度与第二部分114b的掺杂浓度。在一些实施例中，如图1C所示，经由热处理工艺A1，第一N型注入区104与第二N型注入区106中一部分的N型掺质扩散进入半导体基板100的部分100a中，使得所形成的N型阱114具有高掺杂浓度部分(例如:第一部分114a与第二部分114b)以及位于此些高掺杂浓度部分之间的低掺杂浓度部分(例如:第三部分114c)。
在一些实施例中，由于N型阱114具有低掺杂浓度部分(例如:第三部分114c)以及位于此低掺杂浓度部分两侧的高掺杂浓度部分(例如:第一部分114a与第二部分114b)，使得所形成的半导体装置(例如:后文所述的半导体装置10)具有较高的击穿电压。举例而言，N型阱114的第三部分114c的掺杂浓度可为1E16至1E18cm-3，N型阱114之第一部分114a的掺杂浓度可为2E16至5E18cm-3，N型阱114的第二部分114b的掺杂浓度可为2E16至5E18cm-3。
承前述，在一些实施例中，用来形成被半导体基板100的部分100a分隔的第一N型注入区104与第二N型注入区106的离子注入工艺仅使用单一注入掩膜(亦即，第一掩膜102)。换句话说，在此些实施例中，不需使用额外的注入掩膜即可使所形成的N型阱114具有低掺杂浓度部分(例如:第三部分114c)以及位于此低掺杂浓度部分两侧的高掺杂浓度部分(例如:第一部分114a与第二部分114b)，因此可降低半导体装置的生产成本。
在一些实施例中，经由热处理工艺A1，第一N型注入区104与第二N型注入区106中一部分的N型掺质扩散进入半导体基板100的部分100a中而形成N型阱114的第三部分114c，因此N型阱114的第三部分114c的掺杂浓度从第一界面I1与第二界面I2朝向N型阱114的第三部分114c的中心区逐渐下降。举例而言，在一些实施例中，如图1C与图1C’所示，N型阱114的第三部分114c的掺杂浓度从位置P1与位置P2朝向位置P3逐渐下降至一最小值。在一些实施例中，位置P1位于第一界面I1上，位置P2位于第二界面I2上，位置P1与位置P3之间的距离为Z1，位置P2与位置P3之间的距离为Z2，距离Z1小于或大抵上等于距离Z2(例如:距离Z1与距离Z2之间的比值(亦即，Z1/Z2)为0.3至1)。
如图1C所示，N型阱114的第一部份114a可具有深度D1，N型阱114的第二部份114b可具有深度D2，N型阱114的第三部份114c可具有深度D3。在一些实施例中，深度D1与深度D2大于深度D3。在一些实施例中，如图1C所示，N型阱114的第三部份114c的深度从第一界面I1与第二界面I2朝向N型阱114的第三部分114c的中心区逐渐缩小。在一些实施例中，N型阱114的第三部份114c具有内凹的底部轮廓。
接着，如图1D所示，根据一些实施例，于N型阱114中形成N型掺杂区116。在一些实施例中，N型掺杂区116位于N型阱114的第二部分114b中。N型掺杂区116的掺杂浓度可大于N型阱114的第二部分114b的掺杂浓度。举例而言，N型掺杂区116的掺杂浓度可为5E17至1E19cm-3。举例而言，形成N型掺杂区116的步骤可包括离子注入工艺、热处理工艺、其他适当的工艺或上述的组合。
接着，如图1E所示，根据一些实施例，于N型阱114中形成N型掺杂区118。N型掺杂区118的掺杂浓度可大于N型阱114的第二部分114b的掺杂浓度并小于N型掺杂区116的掺杂浓度。举例而言，N型掺杂区118的掺杂浓度可为1E17至8E18cm-3。举例而言，形成N型掺杂区118的步骤可包括离子注入工艺、热处理工艺、其他适当的工艺或上述的组合。
接着，如图1F所示，根据一些实施例，于半导体基板100的顶表面上形成氧化物120a与氧化物120b。在一些实施例中，氧化物120a与氧化物120b可为场氧化物(fieldoxide)。在一些实施例中，如图1F所示，氧化物120a覆盖N型阱114，氧化物120b覆盖P型阱112。在一些实施例中，如图1F所示，氧化物120a完全覆盖N型阱114的第三部分114c。在一些实施例中，如图1F所示，氧化物120a仅部分覆盖N型阱114的第一部分114a与第二部分114b。举例而言，氧化物120a与氧化物120b可为氧化硅，且可使用硅局部氧化法(localoxidation of silicon，LOCOS)形成氧化物120a与氧化物120b。
接着，如图1G所示，根据一些实施例，于半导体基板100的顶表面上形成栅极介电层122，并于栅极介电层122上形成栅极电极124。栅极介电层122与栅极电极124可部分覆盖N型阱114与P型阱112。
如图1G所示，栅极电极124可具有侧壁124S。在一些实施例中，如图1G所示，栅极电极124的侧壁124S大抵上与第一界面I1相互对齐且相邻于掺杂浓度较低的N型阱114的第三部分114c，这可降低在栅极电极124的侧壁124S附近的电场，进而提高半导体装置的击穿电压。在一些实施例中，栅极电极124的侧壁124S与第一界面I1共平面。
举例而言，栅极介电层122可由氧化硅、氮化硅、氮氧化硅、高介电常数(high-k)介电材料、其他适当的介电材料或上述的组合所形成。在一些实施例中，栅极介电层122的形成步骤可包括沉积工艺、光刻工艺、蚀刻工艺、其他适当的工艺或上述的组合。
举例而言，栅极电极124可由多晶硅、金属(例如:W、Ti、Al、Cu、Mo、Ni、Pt、其他适当的金属材料或上述的组合)、金属合金、金属氮化物、金属硅化物、金属氧化物、其他适当的导电材料或上述的组合所形成。在一些实施例中，栅极电极124的形成步骤可包括沉积工艺、光刻工艺、蚀刻工艺、其他适当的工艺或上述的组合。
接着，如图1H所示，根据一些实施例，于P型阱112中形成P型掺杂区126。P型掺杂区126的掺杂浓度可大于P型阱112的掺杂浓度。举例而言，P型掺杂区126的掺杂浓度可为1E17至5E18cm-3。举例而言，形成P型掺杂区126的步骤可包括离子注入工艺、热处理工艺、其他适当的工艺或上述的组合。
接着，如图1I所示，根据一些实施例，于栅极介电层122与栅极电极124的侧壁上形成栅极侧壁间隔物128。举例而言，栅极侧壁间隔物128可由绝缘材料(例如:SiO2、SiN、SiON、其他适当的绝缘材料或上述的组合)形成。举例而言，可使用化学气相沉积工艺或其他合适的工艺于半导体基板100的顶表面上形成绝缘材料的毯覆层(blanket layer)，接着对上述绝缘材料的毯覆层进行非等向性的(anisotropic)蚀刻而于栅极介电层122与栅极电极124的侧壁上形成栅极侧壁间隔物128。
接着，如图1J所示，根据一些实施例，于N型阱114中形成N型漏极区130，并于P型阱112中形成N型源极区132。在一些实施例中，如图1J所示，N型源极区132形成于P型掺杂区126中，N型漏极区130形成于N型掺杂区116中。在一些实施例中，N型源极区132的一部分位于栅极电极124与栅极介电层122的下方。
举例而言，N型漏极区130的掺杂浓度与N型源极区132的掺杂浓度各自可为5E19至1E21cm-3。举例而言，形成N型漏极区130与N型源极区132的步骤可包括离子注入工艺、热处理工艺、其他适当的工艺或上述的组合。
在一些实施例中，N型漏极区130的掺杂浓度大于N型掺杂区116的掺杂浓度与N型掺杂区118的掺杂浓度。在一些实施例中，N型掺杂区118围绕N型漏极区130的侧壁与底表面。
接着，如图1K所示，根据一些实施例，于P型阱112中形成P型掺杂区134以形成半导体装置10。在一些实施例中，P型掺杂区134位于P型掺杂区126中，且P型掺杂区134的掺杂浓度大于P型掺杂区126的掺杂浓度。举例而言，P型掺杂区134的掺杂浓度可为5E19至1E21cm-3。举例而言，形成P型掺杂区134的步骤可包括离子注入工艺、热处理工艺、其他适当之工艺或上述之组合。在一些实施例中，P型掺杂区134直接接触N型源极区132。
如图1K所示，本发明实施例的半导体装置10的N型阱114具有低掺杂浓度部分(例如:第三部分114c)以及位于此低掺杂浓度部分两侧的高掺杂浓度部分(例如:第一部分114a与第二部分114b)而可具有较高的击穿电压。在一些实施例中，半导体装置10的击穿电压可为80至200伏特。
如图1K所示，半导体装置10的N型阱114的第三部分114c可具有宽度W3。当宽度W3太大时，可能会使N型阱114c浓度太低，增加导通电阻而降低半导体装置10的效能。在一些实施例中，宽度W3小于10微米(例如:宽度W3为1至8微米)。
综合上述，根据一些实施例，半导体装置10的N型阱114具有第一部分114a、第二部分114c以及位于第一部分114a与第二部分114b之间的第三部分114c，N型阱114的第三部分114c的掺杂浓度低于N型阱的第一部分114a的掺杂浓度与N型阱的第二部分114b的掺杂浓度，因此可使半导体装置10具有较高的击穿电压。此外，根据一些实施例，使用单一注入掩膜(亦即，第一掩膜102)进行离子注入工艺于半导体基板100中形成被半导体基板的一部分100a隔开的第一N型注入区104与第二N型注入区106，因此可在不增加注入掩膜的情况下形成N型阱114的第一部分114a、第二部分114b与第三部分114c而提升半导体装置10的性能且不增加制造成本。
图2绘示出本发明一些实施例的半导体装置20的剖面图。半导体装置20与半导体装置10的其中一个差异在于半导体装置20的第一界面I1与栅极电极124的侧壁124S横向分离(laterally spaced apart)。在一些实施例中，如图2所示，栅极电极124部分覆盖N型阱114的第三部分114c。
图3绘示出本发明一些实施例的半导体装置30的剖面图。半导体装置30与半导体装置10的其中一个差异在于半导体装置30的第二界面I2与栅极电极124的侧壁124S相互对齐。在一些实施例中，第二界面I2与栅极电极124的侧壁124S共平面。在一些实施例中，如图3所示，栅极电极124完全覆盖N型阱114的第三部分114c。
图4绘示出本发明一些实施例的半导体装置40的剖面图。半导体装置40与半导体装置10的其中一个差异在于半导体装置40的第一界面I1与栅极电极124的侧壁124S横向分离。在一些实施例中，如图4所示，第二界面I2与栅极电极124的侧壁124S横向分离，且栅极电极124完全覆盖N型阱114的第三部分114c。
图5绘示出本发明一些实施例的半导体装置50的剖面图。半导体装置50与半导体装置10的其中一个差异在于半导体装置50的第一界面I1与栅极电极124的侧壁124S横向分离。在一些实施例中，如图5所示，第二界面I2与栅极电极124的侧壁124S横向分离，且栅极电极124未覆盖N型阱114的第三部分114c。在一些实施例中，如图5所示，第一界面I1可与栅极侧壁间隔物128的侧壁相互对齐。
综合上述，根据本发明实施例，半导体装置的N型阱具有低掺杂浓度部分以及位于此低掺杂浓度部分两侧的高掺杂浓度部分，而可提高击穿电压。此外，根据本发明实施例，使用单一注入掩膜进行离子注入工艺于半导体基板中形成被上述半导体基板的一部分隔开的第一N型注入区与第二N型注入区，因此可在不增加注入掩膜及制造成本的情况下形成上述N型阱的第一部分、第二部分与第三部分。
前述内文概述了许多实施例的特征部件，使本领域技术人员可以从各个方面更佳地了解本发明实施例。本领域技术人员应可理解，且可轻易地以本发明实施例为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例相同的优点。本领域技术人员也应了解这些相等的结构并未背离本发明实施例的发明精神与范围。在不背离本发明实施例的发明精神与范围的前提下，可对本发明实施例进行各种改变、置换或修改，因此本发明的保护范围当视权利要求所界定者为准。另外，虽然本发明已以数个较佳实施例揭露如上，然其并非用以限定本发明，且并非所有优点都已于此详加说明。

Claims (16)

1.一种半导体装置的形成方法，其特征在于，包括:
提供一半导体基板；
于所述半导体基板中形成一第一N型注入区与一第二N型注入区，其中所述第一N型注入区与所述第二N型注入区被所述半导体基板的一部分隔开；
于所述半导体基板中形成一第一P型注入区，其中所述第一N型注入区位于所述第二N型注入区与所述第一P型注入区之间；
对所述半导体基板进行一热处理工艺以于所述半导体基板中形成一P型阱与一N型阱，其中所述N型阱具有一第一部分、一第二部分以及一第三部分，其中所述第一部分位于所述第三部分与所述P型阱之间，所述第三部分位于所述第一部分与所述第二部分之间，且所述第三部分的掺杂浓度低于所述第一部分的掺杂浓度与所述第二部分的掺杂浓度；
形成一栅极介电层于所述半导体基板上，其中所述栅极介电层覆盖所述P型阱与所述N型阱；以及
形成一栅极电极于所述栅极介电层上。
2.根据权利要求1所述的半导体装置的形成方法，其特征在于，于所述半导体基板中形成所述第一N型注入区与所述第二N型注入区的步骤包括：
形成一第一注入掩膜于所述半导体基板上，其中所述第一注入掩膜具有一第一开口与一第二开口，所述第一开口与所述第二开口之间具有一间距；以及
经由所述第一开口与第二开口将N型掺质注入至所述半导体基板中。
3.根据权利要求2所述的半导体装置的形成方法，其特征在于，于所述半导体基板中形成所述第一P型注入区的步骤包括:
形成一第二注入掩膜于所述半导体基板上，其中所述第二注入掩膜覆盖所述第一N型注入区与所述第二N型注入区，且所述第二注入掩膜具有一第三开口；以及
经由所述第三开口将P型掺质注入至所述半导体基板中。
4.根据权利要求2所述的半导体装置的形成方法，其特征在于，所述间距为2至10微米。
5.根据权利要求1所述的半导体装置的形成方法，其特征在于，所述N型阱的第一部分与所述N型阱的第三部分之间具有一第一界面，所述N型阱的第二部分与所述N型阱的第三部分之间具有一第二界面，其中所述N型阱的第三部分的掺杂浓度从所述第一界面与所述第二界面朝向所述N型阱的第三部分的中心区逐渐降低。
6.根据权利要求5所述的半导体装置的形成方法，其特征在于，所述N型阱的第三部分的深度从所述第一界面与所述第二界面朝向所述N型阱的第三部分的中心区逐渐缩小。
7.根据权利要求1所述的半导体装置的形成方法，其特征在于，所述N型阱的第三部分的深度小于所述N型阱的第一部分的深度与所述N型阱的第二部分的深度。
8.根据权利要求1所述的半导体装置的形成方法，其特征在于，更包括:
于所述P型阱中形成一N型源极区；以及
于所述N型阱的第二部分中形成一N型漏极区。
9.根据权利要求8所述的半导体装置的形成方法，其特征在于，更包括:
于所述半导体基板上形成一场氧化物，其中所述场氧化物覆盖所述N型阱的第三部分。
10.根据权利要求8所述的半导体装置的形成方法，其特征在于，更包括:
于所述P型阱中形成一P型掺杂区，其中所述P型掺杂区直接接触所述N型源极区。
11.一种半导体装置，其特征在于，包括:
一半导体基板；
一P型阱，位于所述半导体基板中；
一N型阱，位于所述半导体基板中且相邻于所述P型阱，其中所述N型阱具有一第一部分、一第二部分以及一第三部分，其中所述第一部分位于所述第三部分与所述P型阱之间，所述第三部分位于所述第一部分与所述第二部分之间，且所述第三部分的掺杂浓度低于所述第一部分的掺杂浓度与所述第二部分的掺杂浓度；
一N型源极区，位于所述P型阱中；
一N型漏极区，位于所述N型阱中；
一栅极介电层，位于所述半导体基板上，其中所述栅极介电层部分覆盖所述P型阱与所述N型阱；以及
一栅极电极，位于所述栅极介电层上，其中所述N型阱的第三部分与所述N型阱的第一部分之间具有一第一界面，且所述第一界面与所述栅极电极的一侧壁对齐。
12.根据权利要求11所述的半导体装置，其特征在于，所述N型阱的第三部分与所述N型阱的第二部分之间具有一第二界面，且所述N型阱的第三部分的掺杂浓度从所述第一界面与所述第二界面朝向所述N型阱的第三部分的中心区逐渐降低。
13.根据权利要求12所述的半导体装置，其特征在于，所述N型阱的第三部分的深度从所述第一界面与所述第二界面朝向所述N型阱的第三部分的中心区逐渐缩小。
14.根据权利要求11所述的半导体装置，其特征在于，所述N型阱的第三部分的深度小于所述N型阱的第一部分的深度与所述N型阱的第二部分的深度。
15.根据权利要求11所述的半导体装置，其特征在于，更包括:
一P型掺杂区位于所述P型阱中，其中所述P型掺杂区直接接触所述N型源极区。
16.根据权利要求11所述的半导体装置，其特征在于，更包括:
一场氧化物，位于所述半导体基板上，其中所述场氧化物覆盖所述N型阱的第一部分、所述N型阱的第二部分以及所述N型阱的第三部分。
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