CN111354645B - Embedded chip and preparation method thereof - Google Patents

Embedded chip and preparation method thereof Download PDF

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Publication number
CN111354645B
CN111354645B CN201811571261.3A CN201811571261A CN111354645B CN 111354645 B CN111354645 B CN 111354645B CN 201811571261 A CN201811571261 A CN 201811571261A CN 111354645 B CN111354645 B CN 111354645B
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chip
circuit board
chip body
pin
conductive
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CN111354645A (en
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黄立湘
缪桦
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Shennan Circuit Co Ltd
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Shennan Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides an embedded chip and a preparation method thereof, wherein the preparation method of the embedded chip forms a conductive closed-loop structure surrounding a chip body in a circuit board when the circuit board is subjected to patterning treatment and metal plating, so that pin bonding pads of the chip body are mutually conducted through the conductive closed-loop structure, and further, when the chip pins are formed subsequently, the static current generated by cutting the chip can be dispersed through the conductive closed-loop structure, and the static protection of the chip is realized.

Description

Embedded chip and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to an embedded chip and a preparation method thereof.
Background
With the development of the information society, the amount of information processing of various electronic devices is increasing day by day, and the demand for high-frequency and high-speed signal transmission is increasing day by day. The semiconductor chip is embedded into the circuit board for packaging, so that the connection distance between the semiconductor chip and the packaging substrate can be effectively shortened, and powerful guarantee is provided for high-frequency and high-speed signal transmission. The bare chip embedded circuit board can meet the development requirements of high integration level of a packaging body and miniaturization of electronic products.
In the prior art, a bare chip embedded circuit board is generally prepared by adhering a bare chip to a circuit board, and embedding the bare chip in the circuit board gradually. In addition, the embedded bare chips are usually embedded by a plurality of bare chips on a whole substrate, and after the bare chips are embedded, each chip is cut to obtain one or more required embedded chips. In addition, the leads of the chips are separated from each other, and may be damaged by static electricity during the storage process.
Disclosure of Invention
The invention provides an embedded chip and a preparation method thereof, which are used for realizing electrostatic protection on the chip in the process of preparing the embedded chip.
In order to solve the technical problems, the invention adopts a technical scheme that: provided is a method for preparing an embedded chip, the method comprising:
providing a chip body contained inside a circuit board, wherein the chip body is provided with a pin bonding pad;
patterning the circuit board to form blind holes corresponding to the pin bonding pads of the chip body, and forming a closed-loop groove surrounding the chip body on the circuit board;
performing metal electroplating on the patterned circuit board to lead out the pin pad from electroplated metal through the blind hole and form a conductive closed-loop structure at the closed-loop groove, wherein the pin pad is conducted with the conductive closed-loop structure through the electroplated metal;
and disconnecting the pin bonding pad from the conductive closed-loop structure, and removing the conductive closed-loop structure to form the chip pin of the chip body.
In one embodiment, the number of the chip bodies is at least one, and the conductive closed loop structure surrounds the at least one chip;
and the pin bonding pad of each chip in the at least one chip is conducted with the conductive closed loop structure through the electroplated metal.
In one embodiment, the step of patterning the circuit board further includes:
forming a through hole on the circuit board, wherein the through hole penetrates through the circuit board and is positioned in the range of the conductive closed-loop structure;
the number of the through holes corresponds to that of the chip bodies, and each through hole is located between the corresponding chip body and the conductive closed-loop structure.
In one embodiment, the circuit board comprises a first metal layer and a second metal layer, and a filling layer located between the first metal layer and the second metal layer;
the step of providing a chip body contained within a circuit board includes:
providing a chip body contained within the fill layer of a circuit board.
In one embodiment, the step of providing a chip body contained within a circuit board includes:
forming the first metal layer on a circuit board carrier;
pasting a patch on the first metal layer, and fixing the chip body on the patch;
forming a filling layer wrapping the chip body around the chip body;
and forming the second metal layer on the filling layer, and removing the circuit board carrier.
In one embodiment, the step of providing a chip body contained within a circuit board includes:
forming a groove corresponding to the chip body on the circuit board substrate, and fixing the circuit board substrate on the bonding layer;
fixing the chip body in the groove by using the bonding layer;
filling materials in the groove to form a filling layer wrapping the chip body;
and removing the bonding layer, and forming the first metal layer and the second metal layer on the first surface and the second surface of the filling layer respectively.
In one embodiment, the method of making further comprises:
and providing a conductive plug-in corresponding to the chip pins, wherein the conductive plug-in is detachably plugged with the plurality of chip pins.
On the other hand, the invention adopts a technical scheme that: providing an embedded chip, the embedded chip comprising:
a circuit board on which a blind hole and a plating metal are provided;
the chip body is positioned in the circuit board and provided with a pin bonding pad, and the pin bonding pad is led out from the electroplated metal through a blind hole in the circuit board to form a chip pin;
the chip pin is formed by removing a conductive closed loop structure which is arranged on the circuit board and surrounds the chip body.
In one embodiment, the number of the chips is at least one, and the conductive closed loop structure surrounds the at least one chip;
and the pin bonding pad of each chip in the at least one chip is conducted with the conductive closed loop structure through the electroplated metal.
In one embodiment, a conductive insert is also included; the conductive plug-in is detachably connected with the chip pins in an inserting mode.
The invention has the beneficial effects that: different from the situation of the prior art, the preparation method of the embedded chip provided by the invention comprises the steps of providing a chip body which is contained in a circuit board and is provided with a pin bonding pad, carrying out patterning treatment on the circuit board, forming a blind hole corresponding to the pin bonding pad of the chip body, and forming a closed-loop groove which surrounds the chip body on the circuit board; performing metal electroplating on the patterned circuit board to lead out the pin pad from electroplated metal through the blind hole and form a conductive closed-loop structure at the closed-loop groove, wherein the pin pad is conducted with the conductive closed-loop structure through the electroplated metal; and disconnecting the pin bonding pad from the conductive closed-loop structure, and removing the conductive closed-loop structure to form the chip pin of the chip body. By the preparation method, before the chip pins of the chip body are formed, the pin bonding pads of the chip body are mutually conducted by the conductive closed-loop structure, so that when the chip pins are formed subsequently, the electrostatic current generated by cutting the chip can be dispersed by the conductive closed-loop structure, and the electrostatic protection of the chip is realized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating an embedded chip according to the present invention;
fig. 2a is a schematic structural diagram of the embedded chip corresponding to step S101 in fig. 1;
fig. 2b is a schematic top view of the embedded chip shown in fig. 2 a;
fig. 3a is a schematic structural diagram of the embedded chip corresponding to step S102 in fig. 1;
FIG. 3b is a schematic top view of the embedded chip shown in FIG. 3 a;
fig. 4a is a schematic structural diagram of the embedded chip corresponding to step S103 in fig. 1;
fig. 4b is a schematic top view of the embedded chip shown in fig. 4 a;
fig. 5a is a schematic structural diagram of the embedded chip corresponding to step S104 in fig. 1;
fig. 5b is a schematic top view of the embedded chip shown in fig. 5 a;
fig. 6a is a schematic structural diagram of an embedded chip obtained by the preparation method shown in fig. 1;
fig. 6b is a schematic top view of the embedded chip shown in fig. 6 a;
FIG. 7 is a schematic flow chart of a second embodiment of a method for fabricating an embedded chip according to the present invention
Fig. 8a is a schematic structural diagram of the embedded chip corresponding to step S105 in fig. 7; (ii) a
Fig. 8b is a schematic top view of the embedded chip shown in fig. 8 a;
fig. 9a is a schematic structural view of an embedded chip obtained by the preparation method shown in fig. 7;
fig. 9b is a schematic top view of the embedded chip shown in fig. 9 a;
FIG. 10 is a schematic flow chart diagram illustrating an embodiment of step S101 in FIG. 1;
fig. 11a to 11c are schematic diagrams of the circuit board structures obtained in steps S1011 to S1014 of fig. 10;
FIG. 12 is a schematic flow chart of another embodiment of step S101 in FIG. 1;
fig. 13a to 13c are schematic diagrams of the circuit board structures obtained in steps S1015 to S1018 in fig. 12;
fig. 14 is a flow chart of a method for manufacturing an embedded chip according to a third embodiment of the present invention;
fig. 15a is a schematic structural diagram of the embedded chip after the patterning process in step S202 in fig. 14;
fig. 15b is a schematic top view of the embedded chip shown in fig. 15 a;
fig. 16a is a schematic structural diagram of the embedded chip after the metal plating is performed in step S202 in fig. 14;
fig. 16b is a schematic top view of the embedded chip shown in fig. 16 a;
fig. 17 is a schematic structural view of an embedded chip obtained by the preparation method shown in fig. 14;
fig. 18 is a flow chart of a fourth embodiment of a method for fabricating an embedded chip according to the present invention;
FIG. 19a is a schematic diagram of a portion of a conductive closed loop structure;
FIG. 19b is a schematic diagram of an embodiment of a conductive insert;
fig. 19c is a schematic structural diagram of an embodiment of a conductive interposer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive work based on the embodiments of the present invention, are within the scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing an embedded chip according to a first embodiment of the present invention. As shown in fig. 1, the preparation method of this embodiment at least includes the following steps:
in step S101, a chip body included in a circuit board is provided.
As shown in fig. 2a, the chip body 200 provided in this embodiment is prepared inside the circuit board 100, the chip body 200 inside the circuit board 100 is shown by using a dotted line in fig. 2a, the chip body 200 at least has pin pads 201, 202, 203, the number of the pin pads is not particularly limited in the present invention, in this embodiment, a plurality of pin pads are taken as an example, fig. 2b is a cross-sectional view along the dotted line a in fig. 2a, and as shown in fig. 2b, the pin pads of the chip body 200 in this embodiment at least include a first pin pad 201, a second pin pad 202, a third pin pad 203, a fourth pin pad 204, and a fifth pin pad 205, which are respectively disposed on the upper and lower two sides of the chip body 200. It is understood that fig. 2a is a cross-sectional view along the dotted line a, and thus only the first lead pad 201, the second lead pad 202, and the third lead pad 203 are shown.
Further, in the present embodiment, the circuit board 100 may include at least a first metal layer 101, a second metal layer 102, and a filling layer 103 located between the first metal layer 101 and the second metal layer 102; the chip body 200 is contained within the filler layer 103 of the circuit board 100. Further, the circuit board 100 of the present embodiment may further include a patch 104, and the chip body 200 is fixed on the first metal layer 101 through the third pin pad 203 by using the conductive patch 104, in other embodiments, the patch 104 may also be non-conductive, or the circuit board 100 does not have the patch 104, and the chip body 200 is disposed in the circuit board 100 by using other manners, which is not limited in this embodiment.
Further, the number of the chip bodies 200 provided in the present embodiment is not limited, and may be one chip body 200, or may be a plurality of chip bodies 200 included in the same circuit board 100, and in the present embodiment, 2 chip bodies 200 included in the circuit board 100 are taken as an example, as shown in fig. 2 b. In this embodiment, two chip bodies 200 are the same as each other as an example.
In step S102, the circuit board is patterned to form blind holes corresponding to the pin pads of the chip body, and a closed-loop groove surrounding the chip body is formed on the circuit board.
As further shown in fig. 3a and 3b, the circuit board 100 is patterned to form blind holes 105 corresponding to the first and second pin pads 201 and 202 on the circuit board 100, and in this embodiment, the third pin pad 203 is conducted to the first metal layer 101 through the conductive patch 104, so that the blind hole 105 corresponding to the third pin pad 203 does not need to be formed, and in other embodiments, if the patch 104 is not conductive or the chip body 200 is placed in the circuit board 100 in other manners, so that the third pin pad 203 cannot be directly conducted to the first metal layer 101, the blind hole 105 corresponding to the third pin pad 203 needs to be formed at the same time during the patterning process. It can be understood that the blind holes 105 corresponding to the fourth pin pad 204 and the fifth pin pad 205 are also formed at this time, and the structures of the fourth pin pad 204 and the fifth pin pad 205 are respectively the same as those of the first pin pad 201 and the second pin pad 202, which are not repeated herein and are not marked in fig. 3b (for simplicity of the drawing, the fourth pin pad 204 and the fifth pin pad 205 are not marked in the drawing, and refer to fig. 2b specifically).
Further, the present embodiment forms the closed-loop groove 106 surrounding the chip bodies 200 on the circuit board 100 through the patterning process, the top view of the circuit board 100 at this time is shown in fig. 3b, and when the circuit board 100 includes a plurality of chip bodies 200, the closed-loop groove 106 surrounds the plurality of chip bodies 200.
Further, the closed-loop groove 106 may be a closed-loop groove 106 disposed on the second metal layer 102 of the circuit board 100, or may be a closed-loop groove 106 penetrating through the second metal layer 102 and the filling layer 103 (at this time, the bottom of the closed-loop groove 106 is the first metal layer 101), and in addition, the closed-loop groove 106 may also be a closed-loop groove 106 disposed on the first metal layer 101 of the circuit board 100, or may be a closed-loop groove 106 penetrating through the first metal layer 101 and the filling layer 103 (at this time, the bottom of the closed-loop groove 106 is the second metal layer 102); the embodiment is not limited in particular, and as shown in fig. 3a, the embodiment takes the closed-loop groove 106 penetrating through the second metal layer 102 and the filling layer 103 as an example.
In step S103, metal plating is performed on the patterned circuit board to lead out the pin pad from the plated metal through the blind via and form a conductive closed-loop structure at the closed-loop groove.
As shown in fig. 4a and 4b, the circuit board 100 formed in step S102 is subjected to metal plating, and a metal plating layer 107 is formed on the circuit board 100. At this time, the first pin pad 201, the second pin pad 202, the fourth pin pad 204 and the fifth pin pad 205 of the chip body 200 are respectively led out of the plated metal through the corresponding blind holes 105, the closed-loop groove 106 is also filled with the plated metal to form a conductive closed-loop structure 300, and the third pin pad 203 is conducted with the metal plating layer 107 through the first metal layer 101 and the conductive closed-loop structure 300; further, the first pin pad 201, the second pin pad 202, the third pin pad 203, the fourth pin pad 204 and the fifth pin pad 205 are conducted with each other through the plated metal, the conductive closed-loop structure 300 and the first metal layer 101, metal wires formed by the plated metal are respectively arranged between the first pin pad 201, the second pin pad 202, the fourth pin pad 204 and the fifth pin pad 205 and the conductive closed-loop structure 300, and the third pin pad 203 and the conductive closed-loop structure 300 can form the metal wires through the first metal layer 101.
In this embodiment, the bottom of the closed-loop groove 106 is the first metal layer 101, after the metal is electroplated, the conductive closed-loop structure 300 can conduct the first metal layer 101 and the second metal layer 102, and further, since the conductive closed-loop structure 300 surrounds the plurality of chip bodies 200, and the first pin pad 201, the second pin pad 202, the third pin pad 203, the fourth pin pad 204, and the fifth pin pad 205 of the chip bodies 200 are all connected to the conductive closed-loop structure 300, for one chip body 200, the first pin pad 201, the second pin pad 202, the third pin pad 203, the fourth pin pad 204, and the fifth pin pad 205 can be conducted with each other through the conductive closed-loop structure 300; for the plurality of chip bodies 200, the first pin pad 201, the second pin pad 202, the third pin pad 203, the fourth pin pad 204 and the fifth pin pad 205 of each chip body 200 are all in conduction with the conductive closed-loop structure 300, so that each pin pad of the plurality of chip bodies 200 can also be in conduction with each other through the conductive closed-loop structure 300.
In this embodiment, the metal plating may be a copper circuit, and the plating metal is copper plating.
In step S104, the pin pad is disconnected from the conductive closed-loop structure, and the conductive closed-loop structure is removed to form a chip pin of the chip body.
The plurality of pin pads of the chip body 200 are electrically connected to each other through the conductive closed-loop structure 300, and the conductive closed-loop structure 300 needs to be removed to obtain mutually independent chip structures. Further, as shown in fig. 5a and 5b, a cut is made at the metal wire between the pin pad and the conductive closed-loop structure 300 (at arrow b in fig. 5a, i.e., at the dashed-line frame in fig. 5 b), thereby disconnecting the pin pad from the conductive closed-loop structure 300. Further, the embedded chip shown in fig. 6a and 6b is obtained, wherein the chip pins 108 are formed by separating the metal wires led out from the pin pads from the conductive closed-loop structure 300, and the chip pins 108 are not conducted with each other. When the prepared embedded chip is used, the non-conductive chip pins 108 are connected to the corresponding electronic devices.
Further, referring to fig. 7, as shown in fig. 7, in a second embodiment of the method for manufacturing an embedded chip of the present invention, step S102 in fig. 1 can be replaced by the following steps:
in step S105, patterning the circuit board to form blind holes corresponding to the pin pads of the chip body, and forming a closed-loop groove around the chip body on the circuit board; and simultaneously, a through hole is formed in the circuit board, penetrates through the circuit board and is positioned in the range of the conductive closed-loop structure.
In the present embodiment, when the circuit board 100 is subjected to the patterning process, in addition to the formation of the blind via 105 and the closed-loop groove 106 as in step S102, a through hole 109 is formed on the circuit board 100, as shown in fig. 8a and 8 b. The through hole 109 penetrates through the second metal layer 102 and the filling layer 103 of the circuit board 100, and is filled with a plating metal during metal plating in a subsequent step.
Further, the number of the through holes 109 corresponds to the number of the chip body 200, and in other embodiments, the number of the through holes 109 may also correspond to the number of the pin pads of the chip body 200. As shown in fig. 8a and 8b, the through hole 109 is located within the conductive closed-loop structure 300, and further, the through hole 109 is located between the chip body 200 and the conductive closed-loop structure 300. In this embodiment, the through holes 109 correspond to the first pin pad 201, the second pin pad 202, the fourth pin pad 204, and the fifth pin pad 205 on the side of the chip body 200 close to the second metal layer 102, and each through hole 109 is located on the corresponding pin pad to metal wire of the closed loop structure, so that the obtained embedded chip is as shown in fig. 9a and 9 b.
In the embodiment, when the blind holes 105 of the pin pads of the chip body 200 are prepared, the closed-loop groove 106 is prepared on the circuit board 100 around the chip body 200, so that a conductive closed-loop structure 300 can be prepared at the closed-loop groove 106 through metal plating in the subsequent steps, and the conductive closed-loop structure 300 conducts the pin pads of each chip body 200; further, when each chip body 200 is cut to obtain a final embedded chip, the influence of the electrostatic current generated by cutting or other rubbing on the chip body 200 can be reduced, thereby achieving the purpose of protecting the chip body 200 and improving the yield of the final embedded chip.
In this embodiment, the step S101 may provide the chip body 200 included in the circuit board 100 in various ways.
Further, referring to fig. 10, in an embodiment, the step S101 in this embodiment may include the following steps:
in step S1011, a first metal layer is formed on the circuit board carrier.
In this embodiment, the first metal layer may be a copper foil layer, and a corresponding circuit pattern may be fabricated on the copper foil layer by steps of film pasting, exposure, development, etching, film removal, and the like.
In step S1012, a patch is attached to the first metal layer, and the chip body is fixed to the patch.
As shown in fig. 11a, in this embodiment, a first metal layer 101 is first prepared on a circuit board carrier 400, and then a patch 104 is pasted on the first metal layer 101, and a chip body 200 is fixed on the patch 104. The chip body 200 at least has a first lead pad 201, a second lead pad 202, and a third lead pad 203, and the chip body 200 is fixed by fixing the third lead pad 203 on the patch 104 in this embodiment.
In this embodiment, the first metal layer 101 may be prepared by electroplating, coating, or the like. Further, the patch 104 may be a discrete plurality of patches 104, and the number of patches 104 corresponds to the number of chip bodies 200. In addition, the size of the patch 104 may correspond to the size of the chip body 200, so that the chip can be relatively stably attached to the patch 104. Further, when the chip body 200 is attached, a high-temperature high-pressure attaching process is further adopted, so that sufficient temperature and pressure are provided when the chip body 200 is attached, the chip body 200 is more firmly attached to the patch 104, and the patch 104 is more firmly attached to the first metal layer 101.
In step S1013, a filling layer wrapping the chip body is formed around the chip body.
After step S1012, if there are gaps between the plurality of attached chip bodies 200, a material is filled in the gaps to form the filling layer 103, and as shown in fig. 11b, the filling layer 103 wraps the chip bodies 200.
The filling layer 103 may be a semiconductor packaging material, usually a liquid, which has the functions of heat dissipation and insulation, and becomes solid at a temperature of 120 ° to 300 °.
In step S1014, a second metal layer is formed on the filling layer, and the circuit board carrier is removed.
As further shown in fig. 11c, a second metal layer 102 is further prepared above the filling layer 103 and the circuit board carrier 400 is removed. Thus, the chip body 200 included in the circuit board 100 is completed.
It can be understood that, with the chip body 200 included in the circuit board 100 provided in the present embodiment, the third pin pad 203 is connected to the first metal layer 101 through the patch 104, where the patch 104 may be a conductive patch 104 or a non-conductive patch 104. If the patch 104 is a conductive patch 104, the third pin pad 203 can be directly connected to the first metal layer 101 through the conductive patch 104, so that the formation of the blind via 105 corresponding to the third pin pad 203 is not required during the patterning process in step S102, and after the metal plating process in step S103, the third pin pad 203 can be connected to the conductive closed-loop structure 300 through the conductive patch 104 and the first metal layer 101. If the patch 104 is a non-conductive patch 104, in the step S102, when the patterning process is performed, blind holes 105 corresponding to the third pin pads 203 need to be formed on the first metal layer 101 and the patch 104, and after the metal plating is performed in the step S103, the third pin pads 203 are led out to the first metal layer 101 through the blind holes 105, and are further conducted with the conductive closed-loop structure 300.
In this embodiment, the second metal layer may also be a copper foil layer, and a corresponding circuit pattern may be fabricated on the copper foil layer by steps of film pasting, exposure, development, etching, film removal, and the like.
Further, the present invention also proposes another embodiment of providing a chip body 200 contained within the circuit board 100; referring to fig. 12, in the present embodiment, the step S101 may further include the following steps:
in step S1015, a groove corresponding to the chip body is formed on the circuit board substrate, and the circuit board substrate is fixed on the bonding layer.
As shown in fig. 13a, a plurality of grooves corresponding to the chip bodies 200 may be formed on the circuit board substrate 500 by etching or the like, and it is understood that when the number of the chip bodies 200 is plural, a plurality of grooves corresponding to the chip bodies 200 may be formed on the circuit board substrate 500. Further, the circuit board substrate 500 provided with the groove is attached to the adhesive layer 600.
In step S1016, the chip body is fixed in the groove using an adhesive layer.
Further, as shown in fig. 13b, the chip body 200 is placed in the groove of the circuit board base 500, and the chip body 200 is stuck on the adhesive layer 600.
In step S1017, a material is filled in the groove to form a filling layer wrapping the chip body.
And (4) filling the structure obtained in the step (S1016) with a material to form a filling layer 103, wherein the filling layer 103 wraps the chip body 200, and further, the filling layer 103 can also cover the circuit board substrate 500.
In step S1018, the adhesive layer is removed, and a first metal layer and a second metal layer are formed on the first surface and the second surface of the filling layer, respectively.
As shown in fig. 13c, the adhesive layer 600 is removed, and the first metal layer 101 and the second metal layer 102 are prepared on both surfaces of the filling layer 103, respectively. In this embodiment, the second metal layer 102 may be disposed after removing the adhesive layer 600, that is, the second metal layer 102 is formed on the filling layer 103, then the adhesive layer 600 is removed, and the first metal layer 101 is formed on the surface of the filling layer 103 where the adhesive layer 600 is removed.
The manner of removing the adhesive layer 600 in this embodiment is not particularly limited, and the manner of preparing the first metal layer 101 and the second metal layer 102 is also not particularly limited.
The above two embodiments of providing the chip body 200 included in the circuit board 100 are only examples of the present invention, and in other embodiments, the chip body 200 included in the circuit board 100 may also be provided in other manners.
Further, referring to fig. 14, fig. 14 is a flowchart illustrating a method for fabricating an embedded chip according to a third embodiment of the present invention. As shown in fig. 14, the preparation method of this embodiment may include the following steps:
in step S201, a chip body included inside the circuit board is provided.
The chip body 200 provided in the present embodiment may be as shown in fig. 2a and 2b, the chip body 200 is prepared inside the circuit board 100, and the chip body 200 has a plurality of pin pads thereon. The number of the pin pads is not particularly limited in the present invention, and in this embodiment, a plurality of pin pads are taken as an example, and the structure of the chip body 200 and the circuit board 100 can refer to fig. 2a and fig. 2b, which are not described herein again.
Further, in the present embodiment, as shown in fig. 2a and 2b, the circuit board 100 may include a first metal layer 101, a second metal layer 102, and a filling layer 103 located between the first metal layer 101 and the second metal layer 102; the chip body 200 is contained within the filler layer 103 of the circuit board 100.
Further, in the present embodiment, the embodiment of providing the chip body 200 included in the circuit board 100 may be the same as the embodiment shown in fig. 10 to 11c, and may also be the same as the embodiment shown in fig. 12 to 13c, and is not repeated herein.
In step S202, the circuit board is sequentially subjected to patterning and metal plating to form a plurality of chip pins.
As shown in fig. 15a and 15b, through patterning, blind holes 105 corresponding to the first, second, fourth, and fifth lead pads 201, 202, 204, and 205 of the chip body 200, respectively, are formed on the circuit board 100; further, metal plating is performed on the circuit board 100, and as shown in fig. 16a and 16b, the plated metal fills the blind via 105, and the first pin pad 201, the second pin pad 202, the fourth pin pad 204, and the fifth pin pad 205 are respectively led out of the surface of the circuit board 100, so as to form the chip pin 108.
Further, in other embodiments, when the circuit board 100 is patterned, a through hole 109 is also formed on the circuit board 100, as shown in fig. 15a and 15 b. The through hole 109 penetrates through the second metal layer 102 and the filling layer 103 of the circuit board 100, and is filled with a plating metal during metal plating in a subsequent step.
Further, the number of the through holes 109 corresponds to the number of the chip body 200, in other embodiments, the number of the through holes 109 may also correspond to the number of the pin pads of the chip body 200, and in this embodiment, the through holes 109 respectively correspond to the first pin pad 201, the second pin pad 202, the fourth pin pad 204, and the fifth pin pad 205.
In step S203, conductive plugs corresponding to the plurality of chip pins are provided, and the conductive plugs are detachably plugged with the plurality of chip pins.
As shown in fig. 17, in the present embodiment, after the chip pins of the chip body 200 are formed in step S202, the conductive plugs 310 corresponding to the chip pins are provided, and the conductive plugs 310 can be detachably plugged with the chip pins. When the chip structure obtained in step S202 is not needed to be used, the conductive plug 310 is plugged onto the chip pins to conduct the chip pins with each other, thereby preventing electrostatic damage to the chip body 200 caused by static electricity generated by storage and the like during placement; when the chip structure obtained in step S202 needs to be used, the conductive plug 310 is detached from the chip pins and the chip pins are connected to the corresponding electronic devices.
This embodiment can dismantle electrically conductive plug-in components 310 of grafting through providing with chip pin 108, when the chip does not use, switches on a plurality of chip pins 108 each other through electrically conductive plug-in components 310, and then improves the antistatic properties of chip, when needs use, with electrically conductive plug-in components 310 dismantle can.
Further, the method for manufacturing an embedded chip of the present embodiment may be combined with the first embodiment of the manufacturing method shown in fig. 1 to 6b to form a new embodiment, that is, in another embodiment, when the circuit board 100 is sequentially subjected to the patterning process and the metal plating in step S202 to form the plurality of chip pins 108, the method may be combined with steps 102 to S104 shown in fig. 1 to form a new embodiment, and a flow diagram of the embodiment may be as shown in fig. 18:
in step S301, a chip body included in a circuit board is provided.
In step S302, the circuit board is patterned to form blind holes corresponding to the pin pads of the chip body, and a closed-loop groove surrounding the chip body is formed on the circuit board.
In step S303, metal plating is performed on the patterned circuit board to lead out the pin pad from the plated metal through the blind via, and a conductive closed-loop structure is formed at the closed-loop groove.
In step S304, the pin pad is disconnected from the conductive closed-loop structure, and the conductive closed-loop structure is removed to form a chip pin of the chip body.
Steps S301 to S304 in the present embodiment may be the same as steps S101 to S104 shown in fig. 1, and corresponding schematic structural diagrams may refer to fig. 2a to fig. 6b, which are not repeated herein.
In step S305, conductive plugs corresponding to the plurality of chip pins are provided, and the conductive plugs are detachably plugged with the plurality of chip pins.
Step S305 in this embodiment may be the same as step S203 shown in fig. 14, and is not described herein again.
In this embodiment, the usable one or more embedded chips can be obtained through steps S301 to S304, and further, the step S305 can provide respective conductive plugs for the one or more embedded chips obtained in step S304, so as to improve the antistatic capability of the one or more embedded chips.
Further, in the present embodiment, the conductive plugs 310 provided in step S305 can be obtained by preparing the conductive closed-loop structure 300 removed in step S304 to form conductive grooves corresponding to the respective chip pins. Each groove corresponds to each chip pin, so as to obtain the conductive plug 310 which can be detachably plugged with the chip pins.
Further, step S305 may take the following form:
the bumps 301 corresponding to the chip pins remained on the conductive closed-loop structure 300 are removed, and metal plating is performed between the bumps 301 to fill a new bump structure 311, so as to form a mutually-conductive groove 312 on the conductive closed-loop structure 300.
Specifically, after the conductive closed-loop structure 300 is removed, the bumps 301 corresponding to the chip pins are remained on the conductive closed-loop structure 300, and the removed conductive closed-loop structure 300 may be in a structure similar to a "mountain" shape, as shown in fig. 19 a. In this embodiment, metal filling is performed between the protrusions 310 to form protrusion structures 311, and the protrusions 310 are etched away, so as to obtain the conductive plugs 310 shown in fig. 19 b. It is understood that the recesses 312 of the conductive plug 310 may correspond to the chip pins, and the protrusions 311 may correspond to the gaps between the chip pins, so that the conductive plug 310 may be detachably plugged to the chip pins.
Further, step S305 also adopts the following manner:
the bumps 301 corresponding to the chip pins remained on the conductive closed-loop structure 300 are removed, and etching is performed at the positions corresponding to the bumps, so as to form mutually-conductive grooves 321 on the conductive closed-loop structure 300.
Specifically, after the conductive closed-loop structure 300 is removed, the bumps 301 corresponding to the chip pins remain on the conductive closed-loop structure 300, and the removed conductive closed-loop structure 300 may be in a structure similar to a "mountain" shape, as shown in fig. 19 a. In this embodiment, each protrusion 301 in fig. 19a is etched away, and a corresponding groove 321 is further etched at the position of the protrusion 301, thereby obtaining the conductive plug 320 shown in fig. 19 c. It is understood that the grooves 321 in the conductive plug 320 correspond to the chip pins, so that the conductive plug 320 can be detachably connected to the chip pins.
Furthermore, the invention also provides an embedded chip, which comprises a circuit board, wherein the circuit board is provided with a blind hole and electroplated metal; the chip body is positioned in the circuit board and provided with a pin bonding pad, and the pin bonding pad is led out from the electroplated metal through a blind hole in the circuit board to form a chip pin; the chip pin is formed by removing a conductive closed loop structure which is arranged on the circuit board and surrounds the chip body.
Specifically, the embedded chip of the present embodiment can be prepared by the preparation method shown in fig. 1, and the structure thereof can be shown in fig. 6a and fig. 6b, which is not described herein again.
Furthermore, the invention also provides another embedded chip, which comprises a circuit board, wherein the circuit board is provided with electroplated metal; the chip body is positioned in the circuit board and provided with a plurality of pin bonding pads, and the plurality of pin bonding pads are led out by the electroplated metal to form a plurality of chip pins; and the conductive plug-in is detachably plugged with the chip pins.
Specifically, the embedded chip of the present embodiment can be prepared by the preparation method shown in fig. 14, and the structure of the embedded chip of the present embodiment can be shown in fig. 17, which is not described herein again. Further, the embedded chip of the present embodiment can also be prepared by the preparation method shown in fig. 18, and the structure thereof can still be as shown in fig. 17, which is not described herein again.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (8)

1. A method for preparing an embedded chip, comprising:
providing a chip body contained inside a circuit board, wherein the chip body is provided with a pin bonding pad;
patterning the circuit board to form blind holes corresponding to the pin bonding pads of the chip body, and forming a closed-loop groove surrounding the chip body on the circuit board;
performing metal electroplating on the patterned circuit board to lead out the pin pad from electroplated metal through the blind hole and form a conductive closed-loop structure at the closed-loop groove, wherein the pin pad is conducted with the conductive closed-loop structure through the electroplated metal;
and disconnecting the pin bonding pad from the conductive closed-loop structure, and removing the conductive closed-loop structure to form the chip pin of the chip body.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the number of the chip bodies is at least one, and the conductive closed-loop structure surrounds the at least one chip;
and the pin bonding pad of each chip in the at least one chip is conducted with the conductive closed loop structure through the electroplated metal.
3. The method for manufacturing according to claim 1, wherein the step of performing patterning processing on the circuit board further includes:
forming a through hole on the circuit board, wherein the through hole penetrates through the circuit board and is positioned in the range of the conductive closed-loop structure;
the number of the through holes corresponds to that of the chip bodies, and each through hole is located between the corresponding chip body and the conductive closed-loop structure.
4. The manufacturing method according to claim 1, wherein the circuit board includes a first metal layer and a second metal layer, and a filling layer located between the first metal layer and the second metal layer;
the step of providing a chip body contained within a circuit board includes:
providing a chip body contained within the fill layer of a circuit board.
5. The method of claim 4, wherein the step of providing a chip body contained within a circuit board comprises:
forming the first metal layer on a circuit board carrier;
pasting a patch on the first metal layer, and fixing the chip body on the patch;
forming a filling layer wrapping the chip body around the chip body;
and forming the second metal layer on the filling layer, and removing the circuit board carrier.
6. The method of claim 4, wherein the step of providing a chip body contained within a circuit board comprises:
forming a groove corresponding to the chip body on the circuit board substrate, and fixing the circuit board substrate on the bonding layer;
fixing the chip body in the groove by using the bonding layer;
filling materials in the groove to form a filling layer wrapping the chip body;
and removing the bonding layer, and forming the first metal layer and the second metal layer on the first surface and the second surface of the filling layer respectively.
7. The method of claim 1, further comprising:
and providing a conductive plug-in corresponding to the chip pin, wherein the conductive plug-in is detachably plugged with the chip pin.
8. An embedded chip, comprising:
a circuit board on which a blind hole and a plating metal are provided;
the chip body is positioned in the circuit board and provided with a pin bonding pad, and the pin bonding pad is led out from the electroplated metal through a blind hole in the circuit board to form a chip pin;
the conductive plug-in is detachably plugged with the chip pins;
the chip pin is formed by removing a conductive closed loop structure which is arranged on the circuit board and surrounds the chip body.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307684A (en) * 1998-04-24 1999-11-05 Matsushita Electric Ind Co Ltd Semiconductor package
CN102097415A (en) * 2009-12-10 2011-06-15 日月光半导体制造股份有限公司 Semiconductor packaging piece and manufacture method thereof
WO2013095522A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Electrostatic discharge compatible dicing tape with laser scribe capability
CN104485320A (en) * 2014-12-30 2015-04-01 华天科技（西安）有限公司 Embedded sensing chip encapsulation structure with vertical through hole and manufacturing method thereof
CN106163106A (en) * 2015-04-07 2016-11-23 深南电路股份有限公司 A kind of circuit board with power integrated module and processing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101362015B1 (en) * 2008-12-24 2014-02-11 엘지디스플레이 주식회사 Flat Panel Display Comprising Static Electricity Protection Circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307684A (en) * 1998-04-24 1999-11-05 Matsushita Electric Ind Co Ltd Semiconductor package
CN102097415A (en) * 2009-12-10 2011-06-15 日月光半导体制造股份有限公司 Semiconductor packaging piece and manufacture method thereof
WO2013095522A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Electrostatic discharge compatible dicing tape with laser scribe capability
CN104485320A (en) * 2014-12-30 2015-04-01 华天科技（西安）有限公司 Embedded sensing chip encapsulation structure with vertical through hole and manufacturing method thereof
CN106163106A (en) * 2015-04-07 2016-11-23 深南电路股份有限公司 A kind of circuit board with power integrated module and processing method thereof

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