CN111354639A - IGBT device and preparation method thereof - Google Patents

IGBT device and preparation method thereof Download PDF

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Publication number
CN111354639A
CN111354639A CN202010342098.4A CN202010342098A CN111354639A CN 111354639 A CN111354639 A CN 111354639A CN 202010342098 A CN202010342098 A CN 202010342098A CN 111354639 A CN111354639 A CN 111354639A
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China
Prior art keywords
substrate
cut
buffer layer
metal layer
interlayer dielectric
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CN202010342098.4A
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Chinese (zh)
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潘嘉
杨继业
黄璇
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202010342098.4A priority Critical patent/CN111354639A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

The application discloses a preparation method of an IGBT device and the IGBT device, and the method comprises the following steps: providing a substrate, wherein a deep groove type grid is formed in the substrate, an interlayer dielectric is formed on the upper surface of the substrate, a top metal layer is formed on the interlayer dielectric, and the top end of the deep groove type grid is connected with the interlayer dielectric; sequentially implanting boron ions and hydrogen elements into the lower surface of the substrate to form a cut-off buffer layer, wherein the thickness of the cut-off buffer layer is more than 10 microns; an underlying metal layer is formed on the lower surface of the substrate. According to the IGBT device, boron ion injection and hydrogen element injection are sequentially carried out on the lower surface of the substrate of the IGBT device to form a cut-off buffer layer, the thickness of the cut-off buffer layer is larger than 10 microns, the thickness of the cut-off buffer layer is increased, the cut-off depth of an electric field is increased, and the breakdown voltage of the device is further increased.

Description

IGBT device and preparation method thereof
Technical Field
The application relates to the technical field of semiconductors, in particular to a preparation method of an Insulated Gate Bipolar Transistor (IGBT) device and the IGBT device.
Background
The IGBT device is a composite fully-controlled voltage-driven power semiconductor device composed of a Bipolar Junction Transistor (BJT) device and a metal-oxide-semiconductor field-effect transistor (MOSFET) device, and has the advantages of high input impedance of the MOSFET device and low on-voltage drop of a power transistor (GTR) device. As a core device in new energy power electronic products, an IGBT device has been recently changed from a conventional product field (e.g., white goods, industrial frequency conversion, welding machine, etc.) to a new product field (e.g., new energy automobile field).
Referring to fig. 1, which shows a schematic cross-sectional view of an IGBT device provided in the related art, as shown in fig. 1, a bottom metal layer 120 is formed below a substrate 110, an interlayer dielectric 130 is formed above the substrate 110, and a trench gate 140 and a field stop layer 101 are formed in the substrate 110, wherein a top of the trench gate 140 is connected to the interlayer dielectric 130, and a bottom of the field stop layer 101 is connected to the bottom metal layer 120.
The IGBT device provided in the related art has a small thickness h1 of the field stop layer 101, typically less than 10 μm, resulting in a shallow cut-off depth of the electric field and a low breakdown voltage of the device.
Disclosure of Invention
The application provides a preparation method of an IGBT device and the IGBT device, which can solve the problems that the cut-off depth of an electric field is shallow and the breakdown voltage of the device is low due to the fact that the thickness of a field cut-off layer of the IGBT device provided in the related technology is low.
On one hand, the embodiment of the application provides a preparation method of an IGBT device, which comprises the following steps:
providing a substrate, wherein a deep groove type grid is formed in the substrate, an interlayer medium is formed on the upper surface of the substrate, a top metal layer is formed on the interlayer medium, and the top end of the deep groove type grid is connected with the interlayer medium;
sequentially performing boron (B) ion implantation and hydrogen (H) element implantation on the lower surface of the substrate to form a cut-off buffer layer, wherein the thickness of the cut-off buffer layer is more than 10 micrometers (mum);
a bottom metal layer is formed on a lower surface of the substrate.
Optionally, the sequentially performing boron (B) ion implantation and hydrogen element implantation on the lower surface of the substrate includes:
carrying out boron ion implantation on the lower surface of the substrate, and then carrying out primary annealing treatment;
and performing secondary annealing treatment after performing hydrogen element implantation on the lower surface of the substrate for at least two times.
Optionally, the temperature for performing the second annealing treatment is 200 degrees celsius (° c) to 500 degrees celsius.
Optionally, the performing of the second annealing treatment includes:
and carrying out the second annealing treatment by a diffusion annealing process.
Optionally, the performing of the first annealing treatment includes:
and carrying out the first annealing treatment by a laser annealing process.
Optionally, before the performing the boron ion implantation and the hydrogen element implantation on the lower surface of the substrate in sequence, the method further includes:
and grinding the lower surface of the substrate.
Optionally, after the grinding process is performed on the lower surface of the substrate, the method further includes:
and processing the lower surface of the substrate by a wet etching process.
Optionally, before forming the bottom metal layer on the lower surface of the substrate, the method further includes:
and processing the lower surface of the substrate by a wet etching process.
On the other hand, the embodiment of the present application provides an IGBT device, including:
the gate structure comprises a substrate, a deep groove type grid is formed in the substrate, a cut-off buffer layer is formed at the bottom of the substrate, the thickness of the cut-off buffer layer is larger than 10 micrometers, and the cut-off buffer layer is formed by sequentially performing boron ion implantation and hydrogen element implantation on the lower surface of the substrate;
the interlayer dielectric is formed on the upper surface of the substrate, and the top end of the deep groove type grid is connected with the interlayer dielectric;
a top metal layer formed on the interlayer dielectric;
a bottom metal layer formed on a lower surface of the substrate.
Optionally, the top metal layer includes aluminum copper, aluminum silicon copper, or aluminum silicon.
The technical scheme at least comprises the following advantages:
the lower surface of the substrate of the IGBT device is sequentially subjected to boron ion implantation and hydrogen element implantation to form a cut-off buffer layer, the thickness of the cut-off buffer layer is larger than 10 microns, and the thickness of the cut-off buffer layer is increased, so that the cut-off depth of an electric field is increased, and the breakdown voltage of the device is further increased.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional view of an IGBT device provided in the related art;
fig. 2 is a flowchart of a method for manufacturing an IGBT device according to an exemplary embodiment of the present application;
fig. 3 and 4 are flow charts of manufacturing an IGBT device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flowchart of a method for manufacturing an IGBT device according to an exemplary embodiment of the present application is shown, where the method includes:
step 201, providing a substrate, forming a deep trench type gate in the substrate, forming an interlayer dielectric on the upper surface of the substrate, forming a top metal layer on the interlayer dielectric, and connecting the top end of the deep trench type gate with the interlayer dielectric.
And step 202, sequentially performing boron ion implantation and hydrogen element implantation on the lower surface of the substrate to form a cut-off buffer layer, wherein the thickness of the cut-off buffer layer is more than 10 microns.
Referring to fig. 3, there is shown a schematic cross-sectional view of forming a cut buffer layer 301 after boron ion implantation and hydrogen element implantation are sequentially performed on the lower surface of a substrate 310. Illustratively, as shown in fig. 3, a deep trench type gate 340 is formed in a substrate 310, an interlayer dielectric 330 is formed on an upper surface of the substrate 310, a top metal layer 350 is formed on the interlayer dielectric 330, and a top end of the deep trench type gate 340 is connected to the interlayer dielectric 330.
Wherein the thickness h2 of the cut-off buffer layer 301 is greater than 10 microns; the interlayer dielectric 330 may include a low dielectric constant (low-K) material, which may be a material having a dielectric constant K less than 4, such as silicon dioxide (SiO)2) (ii) a The top metal layer 350 may comprise aluminum copper, aluminum silicon copper, or aluminum silicon, and the thickness of the top metal layer 350 may be 0.3 microns to 1.2 microns.
Optionally, in step 202, "sequentially implanting boron ions and hydrogen ions on the lower surface of the substrate" includes but is not limited to: after boron ion implantation is performed on the lower surface of the substrate 310, a first annealing treatment is performed; after at least two hydrogen implants are performed on the bottom surface of the substrate 310, a second anneal process is performed. By injecting hydrogen at least twice, the hydrogen element distribution with different gradients in the substrate 310 can be realized, and the softness of the IGBT switching device can be optimized.
Illustratively, the lower surface of the substrate 310 may be subjected to three hydrogen species, each hydrogen species implantation being performed at a dose of 0.7 × 10141.5 × 10 per square centimeter15Each square centimeter, or four hydrogen implants of 0.7 × 10 per hydrogen implant may be performed on the bottom surface of the substrate 310141.5 × 10 per square centimeter15Per square centimeter.
Optionally, in the above step, the first annealing treatment may be performed by a laser annealing process, where the energy of the laser annealing may be 1 millijoule to 3 millijoules, and the time of the laser annealing may be 0.5 microseconds to 5 microseconds.
Optionally, in the above step, a second annealing treatment may be performed through a diffusion annealing process; optionally, the temperature for performing the second annealing treatment may be 200 to 500 degrees celsius.
Optionally, before step 202, the method further includes: grinding the lower surface of the substrate 310; and etching the lower surface of the substrate 310 after the grinding and thinning processes by a wet etching process.
Step 203, a bottom metal layer is formed on the lower surface of the substrate.
Referring to fig. 4, a cross-sectional view of an underlying metal layer 320 formed on a lower surface of a substrate 310 is shown. Illustratively, the bottom metal layer 320 may be formed by depositing a metal on the lower surface of the substrate 310 by a Physical Vapor Deposition (PVD) process. Optionally, before step 203, the method further includes: the lower surface of the substrate 310 is processed by a wet etching process.
In summary, in the embodiment of the present application, boron ion implantation and hydrogen element implantation are sequentially performed on the lower surface of the substrate of the IGBT device to form the cut-off buffer layer, where the thickness of the cut-off buffer layer is greater than 10 microns, so that the thickness of the cut-off buffer layer is increased, the cut-off depth of the electric field is increased, and the breakdown voltage of the device is increased.
Referring to fig. 4, a schematic cross-sectional view of an IGBT device provided by an exemplary embodiment of the present application, which can be prepared by the method provided by the above embodiment, includes:
the substrate 310 is provided with a deep trench type gate 340, the bottom of the deep trench type gate is provided with a stop buffer layer 301, the thickness of the stop buffer layer 301 is larger than 10 microns, and the stop buffer layer 301 is formed by sequentially performing boron ion implantation and hydrogen element implantation on the lower surface of the substrate 310.
And an interlayer dielectric 330 formed on the upper surface of the substrate 310, wherein the top end of the deep trench type gate 340 is connected with the interlayer dielectric 330. Optionally, the interlayer dielectric 330 may include a low dielectric constant (low-K) material, which may be a material having a dielectric constant K less than 4, such as silicon dioxide (SiO)2)。
A top metal layer 350 formed on the interlayer dielectric 330. Alternatively, the top metal layer 350 may comprise aluminum copper, aluminum silicon copper, or aluminum silicon, and the thickness of the top metal layer 350 may be 0.3 microns to 1.2 microns.
And an underlying metal layer 320 formed on the lower surface of the substrate 310.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (10)

1. A preparation method of an IGBT device is characterized by comprising the following steps:
providing a substrate, wherein a deep groove type grid is formed in the substrate, an interlayer medium is formed on the upper surface of the substrate, a top metal layer is formed on the interlayer medium, and the top end of the deep groove type grid is connected with the interlayer medium;
sequentially implanting boron ions and hydrogen elements into the lower surface of the substrate to form a cut-off buffer layer, wherein the thickness of the cut-off buffer layer is more than 10 microns;
a bottom metal layer is formed on a lower surface of the substrate.
2. The method of claim 1, wherein the sequentially performing boron ion implantation and hydrogen implantation on the lower surface of the substrate comprises:
carrying out boron ion implantation on the lower surface of the substrate, and then carrying out primary annealing treatment;
and performing secondary annealing treatment after performing hydrogen element implantation on the lower surface of the substrate for at least two times.
3. The method of claim 2, wherein the second annealing is performed at a temperature of 200 to 500 degrees celsius.
4. The method of claim 3, wherein the performing a second annealing process comprises:
and carrying out the second annealing treatment by a diffusion annealing process.
5. The method of claim 2, wherein the performing a first annealing process comprises:
and carrying out the first annealing treatment by a laser annealing process.
6. The method according to any one of claims 1 to 5, wherein before the sequentially performing the boron ion implantation and the hydrogen element implantation on the lower surface of the substrate, the method further comprises:
and grinding the lower surface of the substrate.
7. The method of claim 6, wherein after the grinding the lower surface of the substrate, further comprising:
and processing the lower surface of the substrate by a wet etching process.
8. The method of any of claims 1 to 5, further comprising, prior to forming an underlying metal layer on the lower surface of the substrate:
and processing the lower surface of the substrate by a wet etching process.
9. An IGBT device, characterized by comprising:
the gate structure comprises a substrate, a deep groove type grid is formed in the substrate, a cut-off buffer layer is formed at the bottom of the substrate, the thickness of the cut-off buffer layer is larger than 10 micrometers, and the cut-off buffer layer is formed by sequentially performing boron ion implantation and hydrogen element implantation on the lower surface of the substrate;
the interlayer dielectric is formed on the upper surface of the substrate, and the top end of the deep groove type grid is connected with the interlayer dielectric;
a top metal layer formed on the interlayer dielectric;
a bottom metal layer formed on a lower surface of the substrate.
10. The device of claim 9, wherein the top metal layer comprises aluminum copper, aluminum silicon copper, or aluminum silicon.
CN202010342098.4A 2020-04-27 2020-04-27 IGBT device and preparation method thereof Pending CN111354639A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015037101A1 (en) * 2013-09-12 2015-03-19 トヨタ自動車株式会社 Semiconductor device and method for manufacturing same
CN105765726A (en) * 2013-12-10 2016-07-13 株式会社爱发科 Insulated gate bipolar transistor and production method therefor
JP2017098318A (en) * 2015-11-19 2017-06-01 三菱電機株式会社 Semiconductor device and manufacturing method of the same
CN109075042A (en) * 2016-04-27 2018-12-21 住友重机械工业株式会社 Laser anneal method and laser anneal device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015037101A1 (en) * 2013-09-12 2015-03-19 トヨタ自動車株式会社 Semiconductor device and method for manufacturing same
CN105765726A (en) * 2013-12-10 2016-07-13 株式会社爱发科 Insulated gate bipolar transistor and production method therefor
JP2017098318A (en) * 2015-11-19 2017-06-01 三菱電機株式会社 Semiconductor device and manufacturing method of the same
CN109075042A (en) * 2016-04-27 2018-12-21 住友重机械工业株式会社 Laser anneal method and laser anneal device

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