WO2015037101A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2015037101A1
WO2015037101A1 PCT/JP2013/074704 JP2013074704W WO2015037101A1 WO 2015037101 A1 WO2015037101 A1 WO 2015037101A1 JP 2013074704 W JP2013074704 W JP 2013074704W WO 2015037101 A1 WO2015037101 A1 WO 2015037101A1
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layer
buffer layer
conductivity type
semiconductor substrate
back surface
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PCT/JP2013/074704
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French (fr)
Japanese (ja)
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佑樹 堀内
亀山　悟
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トヨタ自動車株式会社
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Priority to PCT/JP2013/074704 priority Critical patent/WO2015037101A1/en
Publication of WO2015037101A1 publication Critical patent/WO2015037101A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions

Definitions

  • the technology described in this specification relates to a semiconductor device and a manufacturing method thereof.
  • a buffer layer may be formed between the drift layer and the collector layer.
  • the buffer layer is generally formed by implanting impurity ions into the drift layer.
  • the drift layer is thinned by thinning the semiconductor substrate.
  • the IGBT is off, a depletion layer spreads from the PN junction between the body layer and the drift layer.
  • the depletion layer easily reaches the back side of the semiconductor substrate on which the collector layer is formed.
  • a semiconductor device disclosed in the present specification includes a first conductivity type drift layer, a second conductivity type body layer provided on the surface side of the drift layer and a part of which is exposed on the surface of the semiconductor substrate, and a body layer A first conductivity type emitter layer which is exposed on the surface of the semiconductor substrate and separated from the drift layer by the body layer, and a first conductivity type first layer provided on the back surface of the drift layer.
  • the thickness of the first buffer layer is greater than the thickness of the second buffer layer, and the concentration of carriers due to the first conductivity type impurity ions in the second buffer layer is equal to the first conductivity of the first buffer layer. It is higher than the carrier concentration due to the impurity ions of the mold.
  • the semiconductor device includes the first buffer layer having a large thickness at a position on the drift layer side and the second buffer layer having a small thickness at a position on the collector layer side, and the first conductivity of the second buffer layer.
  • the carrier concentration due to the type impurity ions is higher than the carrier concentration due to the first conductivity type impurity ions in the first buffer layer.
  • the first buffer layer secures the entire thickness of the buffer layer, and contributes to securing the breakdown voltage between the collector and the emitter when scratches or foreign substances are transferred from the surface.
  • the second buffer layer is provided between the collector layer and the first buffer layer, and the region where the second buffer layer is formed has a high impurity concentration of the first conductivity type.
  • the impurity concentration of the first conductivity type in the region where the first buffer layer is formed is low, and the influence on the hole injection amount of the first buffer layer is small. For this reason, by adjusting the impurity concentration of the second buffer layer, the hole injection amount into the drift layer can be adjusted. Further, even when a crystal defect exists in the region of the second buffer layer, it can be suppressed that the crystal defect causes a variation in the amount of hole injection. According to the semiconductor device described above, it is possible to achieve both ensuring the breakdown voltage between the collector and the emitter and suppressing variation in the amount of hole injection.
  • the first buffer layer is formed by implanting first impurity ions of the first conductivity type from the back surface of the semiconductor substrate, and the second buffer layer is implanted lower than the first impurity ions.
  • the semiconductor substrate may be formed by implanting second impurity ions of the first conductivity type from the back surface thereof with energy.
  • the first impurity ions may be hydrogen ions
  • the second impurity ions may be impurity ions of the first conductivity type other than hydrogen ions.
  • the first buffer layer is formed by implanting hydrogen ions from the back surface of the semiconductor substrate
  • the second buffer layer is formed of the first conductivity type other than hydrogen ions from the back surface of the semiconductor substrate. It may be formed by implanting impurity ions.
  • the present specification also discloses a method for manufacturing the semiconductor device.
  • annealing is performed to form a second buffer layer, and the second buffer layer is formed.
  • a step of forming a first buffer layer by performing an annealing process after implanting hydrogen ions from the back surface of the semiconductor substrate.
  • the first impurity ions of the first conductivity type are implanted into the semiconductor substrate from the back surface, and annealing is performed to form the first buffer layer, and the semiconductor is implanted with lower implantation energy than the first impurity ions.
  • FIG. 1 is a longitudinal sectional view of a semiconductor device according to Example 1.
  • FIG. 6 is a diagram showing an impurity concentration distribution of a semiconductor device according to Example 1.
  • FIG. 6 is a diagram showing an impurity concentration distribution in a buffer layer of a semiconductor device according to Example 1.
  • FIG. It is a longitudinal cross-sectional view of the semiconductor device which concerns on a comparative example. It is a figure which shows the impurity concentration distribution of the semiconductor device which concerns on a comparative example.
  • FIG. 1 is an example of a semiconductor device manufactured by the manufacturing method disclosed in this specification.
  • the semiconductor device 10 includes a semiconductor substrate 100, a surface electrode 141 in contact with the surface of the semiconductor substrate 100, and a back electrode 142 in contact with the back surface of the semiconductor substrate 100.
  • the semiconductor substrate 100 includes a p-type collector layer 101, an n-type second buffer layer 111, an n-type first buffer layer 113, an n-type drift layer 102, a p-type first body layer 104, , An n-type emitter layer 105 and a p-type second body layer 106.
  • the first body layer 104 is in contact with the surface of the drift layer 102.
  • the second body layer 106 is provided on a part of the surface of the first body layer 104 and is exposed on the surface of the semiconductor substrate 100.
  • the emitter layer 105 is provided on a part of the surface of the first body layer 104 and is exposed on the surface of the semiconductor substrate 100.
  • the emitter layer 105 is separated from the drift layer 102 by the first body layer 104.
  • the first buffer layer 113 is in contact with the back surface of the drift layer 102.
  • the second buffer layer 111 is in contact with the back surface of the first buffer layer 113 and the surface of the collector layer 101.
  • the collector layer 101 is exposed on the back surface of the semiconductor substrate 100.
  • the emitter layer 105 and the second body layer 106 are in contact with the surface electrode 141.
  • the collector layer 101 is in contact with the back electrode 142.
  • the first buffer layer 113 is thicker than the second buffer layer 111.
  • a trench gate 120 is formed on the surface side of the semiconductor substrate 100.
  • the trench gate 120 covers the trench 121 extending from the surface of the semiconductor substrate 100 through the first body layer 104 to the drift layer 102, the gate insulating film 122 formed on the inner wall surface of the trench 121, and the gate insulating film 122.
  • the gate electrode 123 faces the first body layer 104 in a range separating the emitter layer 105 and the drift layer 102 with the gate insulating film 122 interposed therebetween.
  • FIG. 2 is a diagram showing the p-type or n-type impurity concentration of the semiconductor device 10.
  • the vertical axis in FIG. 2 indicates the position of the semiconductor device 10 in the depth direction, and the horizontal axis indicates the p-type or n-type impurity concentration at that position.
  • A1 shown on the vertical axis indicates the position of the surface of the semiconductor substrate 100.
  • B 1 indicates the position of the boundary between the first body layer 104 and the drift layer 102.
  • C1 indicates the position of the boundary between the drift layer 102 and the first buffer layer 113.
  • D1 indicates the position of the boundary between the first buffer layer 113 and the second buffer layer 111.
  • E1 indicates the position of the boundary between the second buffer layer 111 and the collector layer 101.
  • F ⁇ b> 1 indicates the position of the back surface of the semiconductor substrate 100.
  • A1 to B1 represent p-type impurity concentrations
  • B1 to E1 represent n-type impurity concentrations
  • E1 to F1 represent p-type impurity concentrations.
  • FIG. 3 illustrates the hydrogen ion concentration distribution (indicated by reference numeral 33) of the first buffer layer 113 and the phosphorus ion concentration distribution (indicated by reference numeral 31) of the second buffer layer 111.
  • the vertical axis in FIG. 3 indicates the impurity ion concentration, and the horizontal axis indicates the distance from the back surface of the semiconductor substrate 100.
  • phosphorus ions have an impurity concentration peak at a position closer to the back surface of the semiconductor substrate 100, and the spread in the depth direction of the semiconductor substrate 100 is small.
  • hydrogen ions have an impurity concentration peak at a position close to the surface of the semiconductor substrate 100, and the semiconductor substrate 100 has a large spread in the depth direction.
  • the first buffer layer 113 includes a hydrogen ion concentration peak
  • the second buffer layer 111 includes a phosphorus ion concentration peak.
  • the carrier concentration due to phosphorus ions in the second buffer layer 111 is higher than the carrier concentration due to hydrogen ions in the first buffer layer 113.
  • the manufacturing method of the semiconductor device 10 includes a step of forming the second buffer layer 111 and a step of forming the first buffer layer 113.
  • annealing treatment is performed after implanting n-type impurity ions other than hydrogen ions from the back surface of the semiconductor substrate 100.
  • annealing is performed after hydrogen ions are implanted from the back surface of the semiconductor substrate 100 on which the second buffer layer is formed.
  • the structure and the like on the surface side of the semiconductor device 10 can be manufactured by a conventionally known method for manufacturing a semiconductor device in which an IGBT element is formed, and thus description thereof is omitted.
  • the first buffer layer 113 is formed on the semiconductor substrate 100 after the second buffer layer 111.
  • a structure on the surface side of the semiconductor substrate 100 such as the first body layer 104, the second body layer 106, and the trench gate 120 is formed on an n-type semiconductor wafer (which becomes the drift layer 102).
  • ions for example, phosphorus ions
  • an annealing process is performed at a temperature higher than 500 ° C. (for example, a temperature of about 800 ° C. or higher).
  • Two buffer layers 111 are formed.
  • a first buffer layer 113 is formed.
  • the hydrogen ion implantation position when forming the first buffer layer 113 is located closer to the surface side (emitter layer 105 side) of the semiconductor substrate 100 than the phosphorus ion implantation position when forming the second buffer layer 111. adjust. Thereby, the first buffer layer 113 and the second buffer layer 111 can be formed with the positional relationship and thickness as shown in FIGS.
  • the semiconductor device 90 is different from the semiconductor device 10 in that a buffer layer 903 is provided instead of the first buffer layer 113 and the second buffer layer 111 of the semiconductor device 10 shown in FIG.
  • the buffer layer 903 is in contact with the back surface of the drift layer 902 and the surface of the collector layer 101.
  • the buffer layer 903 is formed by implanting hydrogen ions into the semiconductor substrate 900 from the back side and performing an annealing process at a relatively low temperature of about 500 ° C. or lower.
  • A2 shown on the vertical axis indicates the position of the surface of the semiconductor substrate 900.
  • B2 indicates the position of the boundary between the first body layer 104 and the drift layer 902.
  • C2 indicates the position of the boundary between the drift layer 902 and the buffer layer 903.
  • E2 indicates the position of the boundary between the buffer layer 903 and the collector layer 101.
  • F2 indicates the position of the back surface of the semiconductor substrate 900.
  • A2 to B2 indicate p-type impurity concentrations
  • B2 to E2 indicate n-type impurity concentrations
  • E2 to F2 indicate p-type impurity concentrations.
  • the buffer layer 903 has a higher n-type impurity concentration than the drift layer 902.
  • the buffer layer 903 can prevent the depletion layer extending from the PN junction between the body layer 104 and the drift layer 902 from reaching the collector layer 101 when the IGBT formed in the semiconductor device 90 is turned off. If the semiconductor substrate 900 has scratches or foreign matter on the back side, and the above depletion layer reaches the back side, the collector-emitter breakdown voltage may be reduced. According to the semiconductor device 90, the buffer layer 903 can suppress the depletion layer from reaching the back surface side of the semiconductor substrate 900, so that the collector-emitter breakdown voltage can be prevented from decreasing.
  • the buffer layer 903 when hydrogen ions are implanted from the back side of the semiconductor substrate 900 at a particularly high acceleration voltage, crystal defects may be formed in a region through which the hydrogen ions pass. This crystal defect functions as a lifetime killer, affects the life of holes injected from the collector layer 101 into the drift layer 902, and causes variations in the amount of holes injected. As shown in FIG. 5, the peak of the n-type impurity concentration of the buffer layer 903 is located near the central position in the thickness direction of the buffer layer 903, and the n-type impurity concentration of the buffer layer 903 in the vicinity of the collector layer 101. Is relatively low.
  • the semiconductor device 90 it is difficult to sufficiently increase the n-type impurity concentration with respect to the crystal defect density in the region of the buffer layer 903 in the vicinity of the collector layer 101. For this reason, the influence of crystal defects on the amount of holes injected from the collector layer 101 into the drift layer 902 increases. As a result, variations in IGBT characteristics (ON voltage, breakdown voltage, etc.) are likely to occur.
  • the semiconductor device 10 includes a first buffer layer 113 and a second buffer layer 111. Similar to the buffer layer 903, the first buffer layer 113 suppresses the depletion layer from spreading from the PN junction between the body layer 104 and the drift layer 102 and reaching the collector layer 101. As a result, it is possible to prevent the breakdown voltage between the collector and the emitter of the semiconductor device 10 from decreasing. Since the activation rate of hydrogen ions is about several percent of the activation rate of phosphorus ions, the implantation amount of hydrogen ions is inevitably higher than the implantation amount of phosphorus ions, and crystal defects formed by implantation of hydrogen ions are More than crystal defects formed by implantation of phosphorus ions.
  • the second buffer layer 111 Since the second buffer layer 111 is formed by implanting a relatively small amount of phosphorus ions with low energy into the semiconductor substrate 100, the second buffer layer 111 has a crystal defect in the semiconductor substrate 100 compared to the case where the first buffer layer 113 is formed. Is difficult to form. As shown in FIG. 2, since the semiconductor device 10 includes the second buffer layer 111, the n-type impurity concentration is high in a region near the collector layer 101 of the second buffer layer 111. In the semiconductor device 10, it is easy to increase the impurity concentration of the second buffer layer 111, and in the region near the collector layer 101 of the second buffer layer 111, the n-type impurity concentration is set to the crystal defect density. Can be high enough.
  • the first buffer layer 113 and the second buffer layer are provided, thereby ensuring a breakdown voltage between the collector and the emitter, and variation in the amount of hole injection. It is possible to achieve both. Crystal defects that may occur when forming the first buffer layer 113 may cause variations in the amount of hole injection. However, since the dose amount of the n-type impurity in the second buffer layer is large, the crystal defects are not sufficient in the amount of hole injection. It can suppress that it causes variation. Further, since the first buffer layer 113 can be designed for the purpose of ensuring the breakdown voltage between the collector and the emitter, and the second buffer layer 111 can be designed for the purpose of adjusting the hole injection amount, the degree of freedom in design is improved.
  • the time for irradiating the semiconductor substrate 100 with hydrogen ions when the time for irradiating the semiconductor substrate 100 with hydrogen ions is shortened, the n-type impurity concentration derived from the hydrogen ions decreases in the vicinity of the collector layer 101 side.
  • the time for irradiating the semiconductor substrate 100 with hydrogen ions can be shortened to a time sufficient to ensure the collector-emitter breakdown voltage.
  • the first buffer layer 113 is formed by hydrogen ion implantation and the second buffer layer 111 is formed by phosphorus ion implantation.
  • the second buffer layer can be formed by implanting n-type impurity ions other than phosphorus ions.
  • the n-type impurity ions used for forming the second buffer layer are preferably ions different from the n-type impurity ions used for forming the first buffer layer.
  • the height of the acceleration voltage of the impurity ion implantation when forming the first buffer layer 113 and the second buffer layer 111 is not particularly limited, and either one may be high, or both may be the same level. Also good.
  • n-type impurity ions other than hydrogen ions can be implanted.
  • impurity ions for forming the first buffer layer in order to ensure a breakdown voltage between the collector and the emitter, it is preferable to implant impurity ions for forming the first buffer layer with relatively high energy.
  • impurity ions using a high energy ion implantation apparatus having an acceleration voltage in the energy region of about several hundred keV to several MeV.
  • the second buffer layer is preferably formed by implanting impurity ions with lower energy than when forming the first buffer layer.
  • the amount of beam current is generally limited from several ⁇ A region to several mA region, and it may be difficult to increase the dose amount of impurity ions in the first buffer layer. Even in this case, the n-type impurity ion concentration in the vicinity of the collector layer can be ensured by the second buffer layer. Since the second buffer layer is not intended to ensure a breakdown voltage between the collector and the emitter, impurities can be implanted with relatively low energy.
  • the beam current amount can be made relatively large, about 100 ⁇ A to 2 mA, and the dose amount of the second buffer layer is sufficiently large. Can be high.

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Abstract

In the present invention, a semiconductor device is provided with the following: a drift layer of a first conductivity type; a body layer of a second conductivity type that is disposed on the front side of the drift layer and one part of which is exposed to the front of a semiconductor substrate; an emitter layer of the first conductivity type that is disposed on part of the front of the body layer, is exposed to the front of the semiconductor substrate, and is separated from the drift layer by the body layer; a first buffer layer of the first conductivity type that is disposed on the back of the drift layer; a second buffer layer of the first conductivity type that is disposed on the back of the first buffer layer; a collector layer of the first conductivity type that is in contact with the back of the second buffer layer and is exposed to the back of the semiconductor substrate; and a gate electrode that faces the body layer within the range in which the emitter layer and the drift layer are separated, with an insulating film interposed between the gate electrode and the body layer. In this semiconductor device, the thickness of the first buffer layer is greater than the thickness of the second buffer layer and the carrier concentration due to impurity ions of the first conductivity type in the second buffer layer is greater than the carrier concentration due to impurity ions of the first conductivity type in the first buffer layer.

Description

半導体装置とその製造方法Semiconductor device and manufacturing method thereof
　本明細書に記載の技術は、半導体装置とその製造方法に関する。 The technology described in this specification relates to a semiconductor device and a manufacturing method thereof.
　縦型構造のＩＧＢＴにおいては、ドリフト層とコレクタ層の間に、バッファ層が形成されている場合がある。バッファ層は、一般に、ドリフト層に不純物イオンを注入することによって形成される。ＩＧＢＴのオン時の電力損失を低減する手段として、半導体基板を薄板化してドリフト層を薄くすることが行われている。ＩＧＢＴのオフ時には、ボディ層とドリフト層とのＰＮ接合部から空乏層が広がる。ドリフト層の厚さが薄くなると、この空乏層がコレクタ層の形成されている半導体基板の裏面側に到達し易くなる。半導体基板の製造工程において、半導体基板の裏面側に傷や異物混入があった場合、裏面側に空乏層が到達することによって、コレクタ－エミッタ間の耐圧が低下するという課題がある。この課題を解決するために、バッファ層を厚くした構造が提案されている。厚いバッファ層を形成するために、例えば、特許文献１に記載されているような、水素イオン等の軽イオンをＩＧＢＴのドリフト層内に高い加速電圧で注入し、熱処理を行う手法が用いられている。 In a vertical structure IGBT, a buffer layer may be formed between the drift layer and the collector layer. The buffer layer is generally formed by implanting impurity ions into the drift layer. As a means for reducing the power loss when the IGBT is turned on, the drift layer is thinned by thinning the semiconductor substrate. When the IGBT is off, a depletion layer spreads from the PN junction between the body layer and the drift layer. When the thickness of the drift layer is reduced, the depletion layer easily reaches the back side of the semiconductor substrate on which the collector layer is formed. In the manufacturing process of a semiconductor substrate, if there is a scratch or a foreign substance on the back side of the semiconductor substrate, there is a problem that the breakdown voltage between the collector and the emitter is lowered by the depletion layer reaching the back side. In order to solve this problem, a structure with a thick buffer layer has been proposed. In order to form a thick buffer layer, for example, a method of performing heat treatment by injecting light ions such as hydrogen ions into the IGBT drift layer at a high acceleration voltage as described in Patent Document 1 is used. Yes.
特開２００９－１７６８９２号公報JP 2009-176892 A
　特許文献１に記載されているような手法で厚いバッファ層を形成する場合、水素イオン等を高い加速電圧で半導体基板に注入する際に、注入するイオン等が通過する領域に結晶欠陥が形成される。この結晶欠陥は、ライフタイムキラーとして機能し、コレクタ層からドリフト層に注入されるホールの寿命に影響を与え、ホールの注入量のばらつきの原因となる。ホールの注入量のばらつきは、ＩＧＢＴの特性（オン電圧や耐圧等）のばらつきの原因となる。 When a thick buffer layer is formed by the technique described in Patent Document 1, when a hydrogen ion or the like is implanted into a semiconductor substrate at a high acceleration voltage, a crystal defect is formed in a region through which the implanted ion or the like passes. The This crystal defect functions as a lifetime killer, affects the lifetime of holes injected from the collector layer into the drift layer, and causes variations in the amount of holes injected. Variations in the amount of injected holes cause variations in IGBT characteristics (ON voltage, breakdown voltage, etc.).
　本明細書が開示する半導体装置は、第１導電型のドリフト層と、ドリフト層の表面側に設けられるとともにその一部が半導体基板の表面に露出する第２導電型のボディ層と、ボディ層の表面の一部に設けられ、半導体基板の表面に露出し、ボディ層によってドリフト層と分離されている第１導電型のエミッタ層と、ドリフト層の裏面に設けられた第１導電型の第１バッファ層と、第１バッファ層の裏面に設けられた第１導電型の第２バッファ層と、第２バッファ層の裏面に接するとともに半導体基板の裏面に露出する第２導電型のコレクタ層と、エミッタ層とドリフト層を分離している範囲のボディ層に絶縁膜を介して対向しているゲート電極とを備えている。この半導体装置では、第１バッファ層の厚さは、第２バッファ層の厚さよりも厚く、第２バッファ層の第１導電型の不純物イオンによるキャリアの濃度は、第１バッファ層の第１導電型の不純物イオンによるキャリアの濃度よりも高い。 A semiconductor device disclosed in the present specification includes a first conductivity type drift layer, a second conductivity type body layer provided on the surface side of the drift layer and a part of which is exposed on the surface of the semiconductor substrate, and a body layer A first conductivity type emitter layer which is exposed on the surface of the semiconductor substrate and separated from the drift layer by the body layer, and a first conductivity type first layer provided on the back surface of the drift layer. 1 buffer layer, a first conductivity type second buffer layer provided on the back surface of the first buffer layer, a second conductivity type collector layer in contact with the back surface of the second buffer layer and exposed on the back surface of the semiconductor substrate, And a gate electrode facing the body layer in a range where the emitter layer and the drift layer are separated via an insulating film. In this semiconductor device, the thickness of the first buffer layer is greater than the thickness of the second buffer layer, and the concentration of carriers due to the first conductivity type impurity ions in the second buffer layer is equal to the first conductivity of the first buffer layer. It is higher than the carrier concentration due to the impurity ions of the mold.
　上記の半導体装置は、ドリフト層側となる位置に厚みの厚い第１バッファ層を備え、コレクタ層側となる位置に厚みの薄い第２バッファ層を備えており、第２バッファ層の第１導電型の不純物イオンによるキャリアの濃度は、第１バッファ層の第１導電型の不純物イオンによるキャリアの濃度よりも高い。第１バッファ層は、バッファ層の全体の厚さを確保し、表面から傷や異物の移入があった場合のコレクタ－エミッタ間の耐圧確保に寄与する。第２バッファ層は、コレクタ層と第１バッファ層との間に備えられており、第２バッファ層が形成されている領域は、第１導電型の不純物濃度が高い。すなわち、第１バッファ層が形成されている領域の第１導電型の不純物濃度は低く、第１バッファ層のホール注入量への影響は小さい。このため、第２バッファ層の不純物濃度を調整することによって、ドリフト層へのホール注入量を調整することが可能となる。また、第２バッファ層の領域に結晶欠陥が存在する場合であっても、結晶欠陥がホール注入量のばらつきの原因となることを抑制できる。上記の半導体装置によれば、コレクタ－エミッタ間の耐圧を確保することと、ホール注入量のばらつきを抑制することとを、両立できる。 The semiconductor device includes the first buffer layer having a large thickness at a position on the drift layer side and the second buffer layer having a small thickness at a position on the collector layer side, and the first conductivity of the second buffer layer. The carrier concentration due to the type impurity ions is higher than the carrier concentration due to the first conductivity type impurity ions in the first buffer layer. The first buffer layer secures the entire thickness of the buffer layer, and contributes to securing the breakdown voltage between the collector and the emitter when scratches or foreign substances are transferred from the surface. The second buffer layer is provided between the collector layer and the first buffer layer, and the region where the second buffer layer is formed has a high impurity concentration of the first conductivity type. That is, the impurity concentration of the first conductivity type in the region where the first buffer layer is formed is low, and the influence on the hole injection amount of the first buffer layer is small. For this reason, by adjusting the impurity concentration of the second buffer layer, the hole injection amount into the drift layer can be adjusted. Further, even when a crystal defect exists in the region of the second buffer layer, it can be suppressed that the crystal defect causes a variation in the amount of hole injection. According to the semiconductor device described above, it is possible to achieve both ensuring the breakdown voltage between the collector and the emitter and suppressing variation in the amount of hole injection.
　上記の半導体装置では、第１バッファ層は、半導体基板にその裏面から第１導電型の第１の不純物イオンを注入して形成され、第２バッファ層は、第１の不純物イオンよりも低い注入エネルギーで半導体基板にその裏面から第１導電型の第２の不純物イオンを注入して形成されてもよい。さらには、第１の不純物イオンは、水素イオンであり、第２の不純物イオンは、水素イオン以外の第１導電型の不純物イオンであってもよい。 In the above-described semiconductor device, the first buffer layer is formed by implanting first impurity ions of the first conductivity type from the back surface of the semiconductor substrate, and the second buffer layer is implanted lower than the first impurity ions. The semiconductor substrate may be formed by implanting second impurity ions of the first conductivity type from the back surface thereof with energy. Furthermore, the first impurity ions may be hydrogen ions, and the second impurity ions may be impurity ions of the first conductivity type other than hydrogen ions.
　または、上記の半導体装置では、第１バッファ層は、半導体基板にその裏面から水素イオンを注入して形成され、第２バッファ層は、半導体基板にその裏面から水素イオン以外の第１導電型の不純物イオンを注入して形成されてもよい。 Alternatively, in the above semiconductor device, the first buffer layer is formed by implanting hydrogen ions from the back surface of the semiconductor substrate, and the second buffer layer is formed of the first conductivity type other than hydrogen ions from the back surface of the semiconductor substrate. It may be formed by implanting impurity ions.
　本明細書はまた、上記の半導体装置の製造方法を開示する。この製造方法は、半導体基板の裏面から水素イオン以外の第１導電型の不純物イオンを注入した後、アニール処理を行って、第２バッファ層を形成する工程と、第２バッファ層が形成された半導体基板の裏面から水素イオンを注入した後、アニール処理を行って、第１バッファ層を形成する工程とを含んでいてもよい。または、半導体基板にその裏面から第１導電型の第１の不純物イオンを注入し、アニール処理を行って、第１バッファ層を形成する工程と、第１の不純物イオンよりも低い注入エネルギーで半導体基板にその裏面から第１導電型の第２の不純物イオンを注入し、第２バッファ層を形成する工程とを含んでいてもよい。 The present specification also discloses a method for manufacturing the semiconductor device. In this manufacturing method, after implanting first conductivity type impurity ions other than hydrogen ions from the back surface of the semiconductor substrate, annealing is performed to form a second buffer layer, and the second buffer layer is formed. A step of forming a first buffer layer by performing an annealing process after implanting hydrogen ions from the back surface of the semiconductor substrate. Alternatively, the first impurity ions of the first conductivity type are implanted into the semiconductor substrate from the back surface, and annealing is performed to form the first buffer layer, and the semiconductor is implanted with lower implantation energy than the first impurity ions. A step of implanting second impurity ions of the first conductivity type into the substrate from the back surface thereof to form a second buffer layer.
実施例１に係る半導体装置の縦断面図である。1 is a longitudinal sectional view of a semiconductor device according to Example 1. FIG. 実施例１に係る半導体装置の不純物濃度分布を示す図である。6 is a diagram showing an impurity concentration distribution of a semiconductor device according to Example 1. FIG. 実施例１に係る半導体装置のバッファ層の不純物濃度分布を示す図である。6 is a diagram showing an impurity concentration distribution in a buffer layer of a semiconductor device according to Example 1. FIG. 比較例に係る半導体装置の縦断面図である。It is a longitudinal cross-sectional view of the semiconductor device which concerns on a comparative example. 比較例に係る半導体装置の不純物濃度分布を示す図である。It is a figure which shows the impurity concentration distribution of the semiconductor device which concerns on a comparative example.
　図１は、本明細書が開示する製造方法によって製造される半導体装置の一例である。半導体装置１０は、半導体基板１００と、半導体基板１００の表面に接する表面電極１４１と、半導体基板１００の裏面に接する裏面電極１４２とを備えている。半導体基板１００は、ｐ型のコレクタ層１０１と、ｎ型の第２バッファ層１１１と、ｎ型の第１バッファ層１１３と、ｎ型のドリフト層１０２と、ｐ型の第１ボディ層１０４と、ｎ型のエミッタ層１０５と、ｐ型の第２ボディ層１０６とを備えている。第１ボディ層１０４は、ドリフト層１０２の表面に接している。第２ボディ層１０６は、第１ボディ層１０４の表面の一部に設けられ、半導体基板１００の表面に露出している。エミッタ層１０５は、第１ボディ層１０４の表面の一部に設けられ、半導体基板１００の表面に露出している。エミッタ層１０５は、第１ボディ層１０４によってドリフト層１０２と分離されている。第１バッファ層１１３は、ドリフト層１０２の裏面に接する。第２バッファ層１１１は、第１バッファ層１１３の裏面およびコレクタ層１０１の表面に接する。コレクタ層１０１は、半導体基板１００の裏面に露出している。エミッタ層１０５および第２ボディ層１０６は、表面電極１４１に接している。コレクタ層１０１は、裏面電極１４２に接している。図１に示すように、第１バッファ層１１３の厚さは、第２バッファ層１１１より厚い。 FIG. 1 is an example of a semiconductor device manufactured by the manufacturing method disclosed in this specification. The semiconductor device 10 includes a semiconductor substrate 100, a surface electrode 141 in contact with the surface of the semiconductor substrate 100, and a back electrode 142 in contact with the back surface of the semiconductor substrate 100. The semiconductor substrate 100 includes a p-type collector layer 101, an n-type second buffer layer 111, an n-type first buffer layer 113, an n-type drift layer 102, a p-type first body layer 104, , An n-type emitter layer 105 and a p-type second body layer 106. The first body layer 104 is in contact with the surface of the drift layer 102. The second body layer 106 is provided on a part of the surface of the first body layer 104 and is exposed on the surface of the semiconductor substrate 100. The emitter layer 105 is provided on a part of the surface of the first body layer 104 and is exposed on the surface of the semiconductor substrate 100. The emitter layer 105 is separated from the drift layer 102 by the first body layer 104. The first buffer layer 113 is in contact with the back surface of the drift layer 102. The second buffer layer 111 is in contact with the back surface of the first buffer layer 113 and the surface of the collector layer 101. The collector layer 101 is exposed on the back surface of the semiconductor substrate 100. The emitter layer 105 and the second body layer 106 are in contact with the surface electrode 141. The collector layer 101 is in contact with the back electrode 142. As shown in FIG. 1, the first buffer layer 113 is thicker than the second buffer layer 111.
　半導体基板１００の表面側には、トレンチゲート１２０が形成されている。トレンチゲート１２０は、半導体基板１００の表面から第１ボディ層１０４を貫通してドリフト層１０２に至るトレンチ１２１と、トレンチ１２１の内壁面に形成されたゲート絶縁膜１２２と、ゲート絶縁膜１２２に覆われてトレンチ１２１内に充填されているゲート電極１２３とを備えている。ゲート電極１２３は、エミッタ層１０５とドリフト層１０２を分離している範囲の第１ボディ層１０４にゲート絶縁膜１２２を介して対向している。 A trench gate 120 is formed on the surface side of the semiconductor substrate 100. The trench gate 120 covers the trench 121 extending from the surface of the semiconductor substrate 100 through the first body layer 104 to the drift layer 102, the gate insulating film 122 formed on the inner wall surface of the trench 121, and the gate insulating film 122. And a gate electrode 123 filled in the trench 121. The gate electrode 123 faces the first body layer 104 in a range separating the emitter layer 105 and the drift layer 102 with the gate insulating film 122 interposed therebetween.
　図２は、半導体装置１０のｐ型又はｎ型の不純物濃度を示す図である。図２の縦軸は、半導体装置１０の深さ方向の位置を示しており、横軸は、その位置におけるｐ型又はｎ型の不純物濃度を示している。縦軸に示すＡ１は、半導体基板１００の表面の位置を示す。Ｂ１は、第１ボディ層１０４とドリフト層１０２との境界の位置を示す。Ｃ１は、ドリフト層１０２と第１バッファ層１１３との境界の位置を示す。Ｄ１は、第１バッファ層１１３と第２バッファ層１１１との境界の位置を示す。Ｅ１は、第２バッファ層１１１とコレクタ層１０１との境界の位置を示す。Ｆ１は、半導体基板１００の裏面の位置を示す。Ａ１～Ｂ１はｐ型の不純物濃度を示し、Ｂ１～Ｅ１の間はｎ型の不純物濃度を示し、Ｅ１～Ｆ１はｐ型の不純物濃度を示している。 FIG. 2 is a diagram showing the p-type or n-type impurity concentration of the semiconductor device 10. The vertical axis in FIG. 2 indicates the position of the semiconductor device 10 in the depth direction, and the horizontal axis indicates the p-type or n-type impurity concentration at that position. A1 shown on the vertical axis indicates the position of the surface of the semiconductor substrate 100. B 1 indicates the position of the boundary between the first body layer 104 and the drift layer 102. C1 indicates the position of the boundary between the drift layer 102 and the first buffer layer 113. D1 indicates the position of the boundary between the first buffer layer 113 and the second buffer layer 111. E1 indicates the position of the boundary between the second buffer layer 111 and the collector layer 101. F <b> 1 indicates the position of the back surface of the semiconductor substrate 100. A1 to B1 represent p-type impurity concentrations, B1 to E1 represent n-type impurity concentrations, and E1 to F1 represent p-type impurity concentrations.
　図３に、第１バッファ層１１３の水素イオン濃度分布（参照番号３３で示す）と、第２バッファ層１１１のリンイオン濃度分布（参照番号３１で示す）を図示する。図３の縦軸はそれぞれの不純物イオン濃度を示しており、横軸は、半導体基板１００の裏面からの距離を示している。図３に示すように、リンイオンは、半導体基板１００の裏面により近い位置に不純物濃度のピークを有しており、半導体基板１００の深さ方向の広がりが小さい。水素イオンは、リンイオンと比較して、半導体基板１００の表面に近い位置に不純物濃度のピークを有しており、半導体基板１００の深さ方向の広がりが大きい。第１バッファ層１１３は、水素イオンの濃度のピークを含んでおり、第２バッファ層１１１は、リンイオンの濃度のピークを含んでいる。第２バッファ層１１１のリンイオンによるキャリアの濃度は、第１バッファ層１１３の水素イオンによるキャリアの濃度よりも高い。 3 illustrates the hydrogen ion concentration distribution (indicated by reference numeral 33) of the first buffer layer 113 and the phosphorus ion concentration distribution (indicated by reference numeral 31) of the second buffer layer 111. The vertical axis in FIG. 3 indicates the impurity ion concentration, and the horizontal axis indicates the distance from the back surface of the semiconductor substrate 100. As shown in FIG. 3, phosphorus ions have an impurity concentration peak at a position closer to the back surface of the semiconductor substrate 100, and the spread in the depth direction of the semiconductor substrate 100 is small. Compared with phosphorus ions, hydrogen ions have an impurity concentration peak at a position close to the surface of the semiconductor substrate 100, and the semiconductor substrate 100 has a large spread in the depth direction. The first buffer layer 113 includes a hydrogen ion concentration peak, and the second buffer layer 111 includes a phosphorus ion concentration peak. The carrier concentration due to phosphorus ions in the second buffer layer 111 is higher than the carrier concentration due to hydrogen ions in the first buffer layer 113.
　半導体装置１０の製造方法は、第２バッファ層１１１を形成する工程と、第１バッファ層１１３を形成する工程を含んでいる。第２バッファ層を形成する工程では、半導体基板１００の裏面から水素イオン以外のｎ型の不純物イオンを注入した後、アニール処理を行う。第１バッファ層１１３を形成する工程では、第２バッファ層が形成された半導体基板１００の裏面から水素イオンを注入した後、アニール処理を行う。半導体装置１０の表面側の構造等は、従来公知のＩＧＢＴ素子が形成された半導体装置の製造方法によって製造することができるため、説明を省略する。 The manufacturing method of the semiconductor device 10 includes a step of forming the second buffer layer 111 and a step of forming the first buffer layer 113. In the step of forming the second buffer layer, annealing treatment is performed after implanting n-type impurity ions other than hydrogen ions from the back surface of the semiconductor substrate 100. In the step of forming the first buffer layer 113, annealing is performed after hydrogen ions are implanted from the back surface of the semiconductor substrate 100 on which the second buffer layer is formed. The structure and the like on the surface side of the semiconductor device 10 can be manufactured by a conventionally known method for manufacturing a semiconductor device in which an IGBT element is formed, and thus description thereof is omitted.
　第１バッファ層１１３は、第２バッファ層１１１よりも後に半導体基板１００に形成される。まず、ｎ型の半導体ウェハ（ドリフト層１０２となる）に、第１ボディ層１０４、第２ボディ層１０６、トレンチゲート１２０等の半導体基板１００の表面側の構造を形成する。次に、この半導体ウェハにその裏面側から、水素イオン以外のイオン（例えば、リンイオン）を注入し、５００℃よりも高い温度（例えば８００℃程度以上の温度）でアニール処理を行うことによって、第２バッファ層１１１を形成する。次に、半導体ウェハにその裏面側（コレクタ層１０１側）から、水素イオンを注入し、５００℃程度以下の比較的低い温度（例えば２００～５００℃未満の温度）でアニール処理を行うことによって、第１バッファ層１１３を形成する。第１バッファ層１１３を形成する際の水素イオンの注入位置は、第２バッファ層１１１を形成する際のリンイオンの注入位置よりも、半導体基板１００の表面側（エミッタ層１０５側）となるように調整する。これによって、図１，２に示すような位置関係と厚さで、第１バッファ層１１３、第２バッファ層１１１を形成することができる。 The first buffer layer 113 is formed on the semiconductor substrate 100 after the second buffer layer 111. First, a structure on the surface side of the semiconductor substrate 100 such as the first body layer 104, the second body layer 106, and the trench gate 120 is formed on an n-type semiconductor wafer (which becomes the drift layer 102). Next, ions (for example, phosphorus ions) other than hydrogen ions are implanted into the semiconductor wafer from the back surface side, and an annealing process is performed at a temperature higher than 500 ° C. (for example, a temperature of about 800 ° C. or higher). Two buffer layers 111 are formed. Next, hydrogen ions are implanted into the semiconductor wafer from its back side (collector layer 101 side), and annealing is performed at a relatively low temperature of about 500 ° C. or lower (for example, a temperature of 200 to less than 500 ° C.), A first buffer layer 113 is formed. The hydrogen ion implantation position when forming the first buffer layer 113 is located closer to the surface side (emitter layer 105 side) of the semiconductor substrate 100 than the phosphorus ion implantation position when forming the second buffer layer 111. adjust. Thereby, the first buffer layer 113 and the second buffer layer 111 can be formed with the positional relationship and thickness as shown in FIGS.
　比較のため、図４に示すＩＧＢＴが形成された従来公知の半導体装置９０と、図５に示す半導体装置９０の不純物濃度についても併せて説明する。半導体装置９０は、図１に示す半導体装置１０の第１バッファ層１１３および第２バッファ層１１１に替えて、バッファ層９０３を備えている点において、半導体装置１０と相違する。バッファ層９０３は、ドリフト層９０２の裏面およびコレクタ層１０１の表面に接している。バッファ層９０３は、第１バッファ層１１３と同様に、半導体基板９００にその裏面側から、水素イオンを注入し、５００℃程度以下の比較的低い温度でアニール処理を行うことによって形成される。 For comparison, the impurity concentration of the conventionally known semiconductor device 90 in which the IGBT shown in FIG. 4 is formed and the semiconductor device 90 shown in FIG. 5 will also be described together. The semiconductor device 90 is different from the semiconductor device 10 in that a buffer layer 903 is provided instead of the first buffer layer 113 and the second buffer layer 111 of the semiconductor device 10 shown in FIG. The buffer layer 903 is in contact with the back surface of the drift layer 902 and the surface of the collector layer 101. Similarly to the first buffer layer 113, the buffer layer 903 is formed by implanting hydrogen ions into the semiconductor substrate 900 from the back side and performing an annealing process at a relatively low temperature of about 500 ° C. or lower.
　図５の縦軸は、半導体装置９０の深さ方向の位置を示しており、横軸は、その位置におけるｐ型又はｎ型の不純物濃度を示している。縦軸に示すＡ２は、半導体基板９００の表面の位置を示す。Ｂ２は、第１ボディ層１０４とドリフト層９０２との境界の位置を示す。Ｃ２は、ドリフト層９０２とバッファ層９０３との境界の位置を示す。Ｅ２は、バッファ層９０３とコレクタ層１０１との境界の位置を示す。Ｆ２は、半導体基板９００の裏面の位置を示す。Ａ２～Ｂ２はｐ型の不純物濃度を示し、Ｂ２～Ｅ２の間はｎ型の不純物濃度を示し、Ｅ２～Ｆ２はｐ型の不純物濃度を示している。 5 indicates the position in the depth direction of the semiconductor device 90, and the horizontal axis indicates the p-type or n-type impurity concentration at that position. A2 shown on the vertical axis indicates the position of the surface of the semiconductor substrate 900. B2 indicates the position of the boundary between the first body layer 104 and the drift layer 902. C2 indicates the position of the boundary between the drift layer 902 and the buffer layer 903. E2 indicates the position of the boundary between the buffer layer 903 and the collector layer 101. F2 indicates the position of the back surface of the semiconductor substrate 900. A2 to B2 indicate p-type impurity concentrations, B2 to E2 indicate n-type impurity concentrations, and E2 to F2 indicate p-type impurity concentrations.
　バッファ層９０３は、ドリフト層９０２よりもｎ型の不純物濃度が高い。バッファ層９０３によって、半導体装置９０に形成されたＩＧＢＴのオフ時に、ボディ層１０４とドリフト層９０２とのＰＮ接合部から広がる空乏層がコレクタ層１０１に到達することを抑制することができる。仮に半導体基板９００の裏面側に傷や異物混入があった場合に、裏面側に上記の空乏層が到達すると、コレクタ－エミッタ間の耐圧が低下する可能性がある。半導体装置９０によれば、バッファ層９０３によって、半導体基板９００の裏面側に空乏層が到達することを抑制できるため、コレクタ－エミッタ間の耐圧が低下することを抑制できる。 The buffer layer 903 has a higher n-type impurity concentration than the drift layer 902. The buffer layer 903 can prevent the depletion layer extending from the PN junction between the body layer 104 and the drift layer 902 from reaching the collector layer 101 when the IGBT formed in the semiconductor device 90 is turned off. If the semiconductor substrate 900 has scratches or foreign matter on the back side, and the above depletion layer reaches the back side, the collector-emitter breakdown voltage may be reduced. According to the semiconductor device 90, the buffer layer 903 can suppress the depletion layer from reaching the back surface side of the semiconductor substrate 900, so that the collector-emitter breakdown voltage can be prevented from decreasing.
　一方で、バッファ層９０３の製造工程において、水素イオンを特に高い加速電圧で半導体基板９００の裏面側から注入すると、水素イオンが通過する領域に結晶欠陥が形成されることがある。この結晶欠陥は、ライフタイムキラーとして機能し、コレクタ層１０１からドリフト層９０２に注入されるホールの寿命に影響を与え、ホールの注入量のばらつきの原因となる。図５に示すように、バッファ層９０３のｎ型の不純物濃度のピークは、バッファ層９０３の厚さ方向の中央位置付近に位置し、コレクタ層１０１の近傍におけるバッファ層９０３のｎ型の不純物濃度は、比較的低くなっている。半導体装置９０では、バッファ層９０３のコレクタ層１０１の近傍の領域において、結晶欠陥密度に対して、ｎ型の不純物濃度を十分に高くすることが困難である。このため、コレクタ層１０１からドリフト層９０２に注入されるホールの注入量に対する結晶欠陥の影響が大きくなる。その結果、ＩＧＢＴの特性（オン電圧や耐圧等）のばらつきの生じ易くなる。 On the other hand, in the manufacturing process of the buffer layer 903, when hydrogen ions are implanted from the back side of the semiconductor substrate 900 at a particularly high acceleration voltage, crystal defects may be formed in a region through which the hydrogen ions pass. This crystal defect functions as a lifetime killer, affects the life of holes injected from the collector layer 101 into the drift layer 902, and causes variations in the amount of holes injected. As shown in FIG. 5, the peak of the n-type impurity concentration of the buffer layer 903 is located near the central position in the thickness direction of the buffer layer 903, and the n-type impurity concentration of the buffer layer 903 in the vicinity of the collector layer 101. Is relatively low. In the semiconductor device 90, it is difficult to sufficiently increase the n-type impurity concentration with respect to the crystal defect density in the region of the buffer layer 903 in the vicinity of the collector layer 101. For this reason, the influence of crystal defects on the amount of holes injected from the collector layer 101 into the drift layer 902 increases. As a result, variations in IGBT characteristics (ON voltage, breakdown voltage, etc.) are likely to occur.
　これに対して、実施例に係る半導体装置１０は、第１バッファ層１１３と第２バッファ層１１１とを備えている。第１バッファ層１１３は、バッファ層９０３と同様に、ボディ層１０４とドリフト層１０２とのＰＮ接合部から空乏層が広がって、コレクタ層１０１に到達することを抑制する。これによって、半導体装置１０のコレクタ－エミッタ間の耐圧が低下することを抑制できる。水素イオンの活性化率は、リンイオンの活性化率の数％程度であるため、水素イオンの注入量は、リンイオンの注入量より必然的に高くなり、水素イオンの注入によって形成される結晶欠陥は、リンイオンの注入によって形成される結晶欠陥よりも多くなる。第２バッファ層１１１は、半導体基板１００に低エネルギーで比較的に少量のリンイオンを注入することによって形成されるため、第１バッファ層１１３を形成する場合と比較して、半導体基板１００に結晶欠陥が形成されにくい。また、図２に示すように、半導体装置１０は、第２バッファ層１１１を備えているため、第２バッファ層１１１のコレクタ層１０１の近傍の領域において、ｎ型の不純物濃度が高い。半導体装置１０では、第２バッファ層１１１の不純物濃度を高くすることが容易であり、第２バッファ層１１１のコレクタ層１０１の近傍の領域において、結晶欠陥密度に対して、ｎ型の不純物濃度を十分に高くすることができる。その結果、相対的に、第１バッファ層１１３を形成する際に生じ得る結晶欠陥によるホール注入量への影響を小さくすることができる。すなわち、第１バッファ層１１３を形成する際に生じ得る結晶欠陥がホール注入量のばらつきの原因となることを抑制できる。また、第２バッファ層１１１の不純物濃度を調整することによって、ドリフト層１０２へのホール注入量を調整することができる。 In contrast, the semiconductor device 10 according to the embodiment includes a first buffer layer 113 and a second buffer layer 111. Similar to the buffer layer 903, the first buffer layer 113 suppresses the depletion layer from spreading from the PN junction between the body layer 104 and the drift layer 102 and reaching the collector layer 101. As a result, it is possible to prevent the breakdown voltage between the collector and the emitter of the semiconductor device 10 from decreasing. Since the activation rate of hydrogen ions is about several percent of the activation rate of phosphorus ions, the implantation amount of hydrogen ions is inevitably higher than the implantation amount of phosphorus ions, and crystal defects formed by implantation of hydrogen ions are More than crystal defects formed by implantation of phosphorus ions. Since the second buffer layer 111 is formed by implanting a relatively small amount of phosphorus ions with low energy into the semiconductor substrate 100, the second buffer layer 111 has a crystal defect in the semiconductor substrate 100 compared to the case where the first buffer layer 113 is formed. Is difficult to form. As shown in FIG. 2, since the semiconductor device 10 includes the second buffer layer 111, the n-type impurity concentration is high in a region near the collector layer 101 of the second buffer layer 111. In the semiconductor device 10, it is easy to increase the impurity concentration of the second buffer layer 111, and in the region near the collector layer 101 of the second buffer layer 111, the n-type impurity concentration is set to the crystal defect density. Can be high enough. As a result, the influence on the hole injection amount due to crystal defects that may occur when the first buffer layer 113 is formed can be relatively reduced. That is, it is possible to suppress crystal defects that may occur when forming the first buffer layer 113 from causing variations in the amount of hole injection. Further, the amount of holes injected into the drift layer 102 can be adjusted by adjusting the impurity concentration of the second buffer layer 111.
　上記のとおり、実施例に係る半導体装置１０によれば、第１バッファ層１１３と第２バッファ層とを備えていることによって、コレクタ－エミッタ間の耐圧を確保することと、ホール注入量のばらつきを抑制することとを、両立できる。第１バッファ層１１３を形成する際に生じ得る結晶欠陥は、ホール注入量のばらつきの原因となり得るが、第２バッファ層のｎ型の不純物のドーズ量が多いため、結晶欠陥がホール注入量のばらつきの原因となることを抑制できる。また、第１バッファ層１１３をコレクタ－エミッタ間の耐圧確保を目的として設計し、第２バッファ層１１１をホール注入量の調整を目的として設計することができるため、設計の自由度が向上する。例えば、第１バッファ層１１３について、半導体基板１００に水素イオンを照射する時間を短縮すると、コレクタ層１０１側の近傍において水素イオンに由来するｎ型の不純物濃度が低くなる。この場合、第２バッファ層１１１のｎ型の不純物濃度を十分に高くすることで、結晶欠陥がホール注入量のばらつきの原因となることを抑制できる。すなわち、半導体基板１００に水素イオンを照射する時間をコレクタ－エミッタ間の耐圧を確保するのに十分な時間にまで短縮することができる。 As described above, according to the semiconductor device 10 according to the embodiment, the first buffer layer 113 and the second buffer layer are provided, thereby ensuring a breakdown voltage between the collector and the emitter, and variation in the amount of hole injection. It is possible to achieve both. Crystal defects that may occur when forming the first buffer layer 113 may cause variations in the amount of hole injection. However, since the dose amount of the n-type impurity in the second buffer layer is large, the crystal defects are not sufficient in the amount of hole injection. It can suppress that it causes variation. Further, since the first buffer layer 113 can be designed for the purpose of ensuring the breakdown voltage between the collector and the emitter, and the second buffer layer 111 can be designed for the purpose of adjusting the hole injection amount, the degree of freedom in design is improved. For example, in the first buffer layer 113, when the time for irradiating the semiconductor substrate 100 with hydrogen ions is shortened, the n-type impurity concentration derived from the hydrogen ions decreases in the vicinity of the collector layer 101 side. In this case, by sufficiently increasing the n-type impurity concentration of the second buffer layer 111, it is possible to suppress crystal defects from causing variations in the amount of hole injection. That is, the time for irradiating the semiconductor substrate 100 with hydrogen ions can be shortened to a time sufficient to ensure the collector-emitter breakdown voltage.
　上記においては、第１バッファ層１１３は、水素イオンの注入によって形成され、第２バッファ層１１１は、リンイオンの注入によって形成される例を挙げて説明したが、これに限定されない。例えば、第２バッファ層は、リンイオン以外のｎ型の不純物イオンを注入することで形成することもできる。なお、第２バッファ層を形成するために用いるｎ型の不純物イオンは、第１バッファ層を形成するために用いるｎ型の不純物イオンとは異なるイオンであることが好ましい。第１バッファ層１１３、第２バッファ層１１１を形成する際の不純物イオンの注入の加速電圧の高さは、特に限定されず、いずれか一方が高くてもよいし、双方が同程度であってもよい。 In the above description, the first buffer layer 113 is formed by hydrogen ion implantation and the second buffer layer 111 is formed by phosphorus ion implantation. However, the present invention is not limited to this. For example, the second buffer layer can be formed by implanting n-type impurity ions other than phosphorus ions. Note that the n-type impurity ions used for forming the second buffer layer are preferably ions different from the n-type impurity ions used for forming the first buffer layer. The height of the acceleration voltage of the impurity ion implantation when forming the first buffer layer 113 and the second buffer layer 111 is not particularly limited, and either one may be high, or both may be the same level. Also good.
　また、第１バッファ層を形成するに際して、水素イオン以外のｎ型の不純物イオンを注入することもできる。この場合、コレクタ－エミッタ間の耐圧を確保するために、第１バッファ層を形成するための不純物イオンの注入は、比較的高いエネルギーで注入することが好ましい。例えば、加速電圧が数百ｋｅＶ～数ＭｅＶ程度のエネルギー領域にある高エネルギーイオン注入装置を用いて、不純物イオンの注入を行うことが好ましい。この場合、第２バッファ層は、第１バッファ層を形成する際よりも低いエネルギーで、不純物イオンの注入を行って形成することが好ましい。 Also, when forming the first buffer layer, n-type impurity ions other than hydrogen ions can be implanted. In this case, in order to ensure a breakdown voltage between the collector and the emitter, it is preferable to implant impurity ions for forming the first buffer layer with relatively high energy. For example, it is preferable to implant impurity ions using a high energy ion implantation apparatus having an acceleration voltage in the energy region of about several hundred keV to several MeV. In this case, the second buffer layer is preferably formed by implanting impurity ions with lower energy than when forming the first buffer layer.
　高エネルギーイオン注入装置を用いる場合、一般にビーム電流量は数μＡ領域から数ｍＡ領域に制限され、第１バッファ層の不純物イオンのドーズ量を増加することが困難な場合がある。この場合であっても、第２バッファ層によって、コレクタ層の近傍におけるｎ型の不純物イオン濃度を確保することができる。第２バッファ層は、コレクタ－エミッタ間の耐圧の確保を目的としないことから、比較的低いエネルギーで不純物の注入を行うことができる。例えば、加速電圧か数ｋｅＶ～数百ｋｅＶの領域にある中電流イオン注入装置を用いれば、ビーム電流量は１００μＡ～２ｍＡ程度と比較的大きくすることができ、第２バッファ層のドーズ量を十分に高くすることができる。 When a high energy ion implantation apparatus is used, the amount of beam current is generally limited from several μA region to several mA region, and it may be difficult to increase the dose amount of impurity ions in the first buffer layer. Even in this case, the n-type impurity ion concentration in the vicinity of the collector layer can be ensured by the second buffer layer. Since the second buffer layer is not intended to ensure a breakdown voltage between the collector and the emitter, impurities can be implanted with relatively low energy. For example, if a medium current ion implantation apparatus having an acceleration voltage of several keV to several hundred keV is used, the beam current amount can be made relatively large, about 100 μA to 2 mA, and the dose amount of the second buffer layer is sufficiently large. Can be high.
　以上、本発明の実施例について詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。 As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
　本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 The technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

Claims (6)

  1. 　第１導電型のドリフト層と、
    　ドリフト層の表面側に設けられるとともにその一部が半導体基板の表面に露出する第２導電型のボディ層と、
    　ボディ層の表面の一部に設けられ、半導体基板の表面に露出し、ボディ層によってドリフト層と分離されている第１導電型のエミッタ層と、
    　ドリフト層の裏面に設けられた第１導電型の第１バッファ層と、
    　第１バッファ層の裏面に設けられた第１導電型の第２バッファ層と、
    　第２バッファ層の裏面に接するとともに半導体基板の裏面に露出する第２導電型のコレクタ層と、
    　エミッタ層とドリフト層を分離している範囲のボディ層に絶縁膜を介して対向しているゲート電極とを備え、
    　第１バッファ層の厚さは、第２バッファ層の厚さよりも厚く、
    　第２バッファ層の第１導電型の不純物イオンによるキャリアの濃度は、第１バッファ層の第１導電型の不純物イオンによるキャリアの濃度よりも高い、半導体装置。     A first conductivity type drift layer;
    A body layer of a second conductivity type provided on the surface side of the drift layer and a part of which is exposed on the surface of the semiconductor substrate;
    An emitter layer of a first conductivity type provided on a part of the surface of the body layer, exposed on the surface of the semiconductor substrate and separated from the drift layer by the body layer;
    A first buffer layer of a first conductivity type provided on the back surface of the drift layer;
    A second buffer layer of the first conductivity type provided on the back surface of the first buffer layer;
    A collector layer of a second conductivity type in contact with the back surface of the second buffer layer and exposed on the back surface of the semiconductor substrate;
    A gate electrode facing the body layer in a range separating the emitter layer and the drift layer through an insulating film;
    The first buffer layer is thicker than the second buffer layer,
    The semiconductor device, wherein the carrier concentration due to the first conductivity type impurity ions in the second buffer layer is higher than the carrier concentration due to the first conductivity type impurity ions in the first buffer layer.
  2. 　第１バッファ層は、半導体基板にその裏面から第１導電型の第１の不純物イオンを注入して形成され、
    　第２バッファ層は、第１の不純物イオンよりも低い注入エネルギーで半導体基板にその裏面から第１導電型の第２の不純物イオンを注入して形成される、請求項１に記載の半導体装置。     The first buffer layer is formed by implanting first impurity ions of the first conductivity type from the back surface of the semiconductor substrate,
    2. The semiconductor device according to claim 1, wherein the second buffer layer is formed by implanting second impurity ions of the first conductivity type from a back surface of the semiconductor substrate with an implantation energy lower than that of the first impurity ions.
  3. 　第１の不純物イオンは、水素イオンであり、
    　第２の不純物イオンは、水素イオン以外の第１導電型の不純物イオンである、請求項２に記載の半導体装置。     The first impurity ions are hydrogen ions,
    The semiconductor device according to claim 2, wherein the second impurity ions are impurity ions of a first conductivity type other than hydrogen ions.
  4. 　第１バッファ層は、半導体基板にその裏面から水素イオンを注入して形成され、
    　第２バッファ層は、半導体基板にその裏面から水素イオン以外の第１導電型の不純物イオンを注入して形成される、請求項１に記載の半導体装置。     The first buffer layer is formed by implanting hydrogen ions from the back surface of the semiconductor substrate,
    2. The semiconductor device according to claim 1, wherein the second buffer layer is formed by implanting impurity ions of a first conductivity type other than hydrogen ions from a back surface of the semiconductor substrate.
  5. 　請求項１に記載の半導体装置の製造方法であって、
    　半導体基板の裏面から水素イオン以外の第１導電型の不純物イオンを注入した後、アニール処理を行って、第２バッファ層を形成する工程と、
    　第２バッファ層が形成された半導体基板の裏面から水素イオンを注入した後、アニール処理を行って、第１バッファ層を形成する工程とを含む、半導体装置の製造方法。     A method of manufacturing a semiconductor device according to claim 1,
    A step of forming a second buffer layer by implanting impurity ions of a first conductivity type other than hydrogen ions from the back surface of the semiconductor substrate and then performing an annealing process;
    Forming a first buffer layer by implanting hydrogen ions from the back surface of the semiconductor substrate on which the second buffer layer is formed, and then performing an annealing process.
  6. 　請求項１に記載の半導体装置の製造方法であって、
    　半導体基板にその裏面から第１導電型の第１の不純物イオンを注入し、アニール処理を行って、第１バッファ層を形成する工程と、
    　第１の不純物イオンよりも低い注入エネルギーで半導体基板にその裏面から第１導電型の第２の不純物イオンを注入し、第２バッファ層を形成する工程とを含む、半導体装置の製造方法。     A method of manufacturing a semiconductor device according to claim 1,
    Injecting first impurity ions of the first conductivity type into the semiconductor substrate from its back surface and performing an annealing process to form a first buffer layer;
    And a step of implanting a second impurity ion of the first conductivity type into the semiconductor substrate from its back surface with an implantation energy lower than that of the first impurity ion to form a second buffer layer.
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