CN113990945A - Insulated gate bipolar transistor structure and manufacturing method thereof - Google Patents
Insulated gate bipolar transistor structure and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention relates to the technical field of semiconductor power devices, in particular to an insulated gate bipolar transistor structure and a manufacturing method thereof, compared with the prior art, the insulated gate bipolar transistor structure provided by the invention has the advantages that a collector region, a stop region and a drift region are sequentially formed in a mode of growing on a substrate, metal contact between a collector and the collector region is realized through the arrangement of a deep groove structure and a connecting layer, and the respective doping concentrations of the stop region and the drift region can be controlled in the growing process, so that the substrate has a wider selection range, compared with the mode of forming the collector region of the stop region through back-side high-energy ion implantation and annealing in the prior art, the substrate is usually made of a semiconductor material with low doping concentration, and in order to obtain lower Vce (sat), the wafer is ground to be very thin, and further the strength of the wafer ground to be very thin is improved through a TAIKO process, the invention does not need to adopt expensive equipment in the process, and has lower production cost.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to an insulated gate bipolar transistor structure and a manufacturing method thereof.
Background
An FS (field stop) IGBT (Insulated Gate Bipolar Transistor) is developed based on an NPT (Non-Punch Through) IGBT, and since an N-type electric field termination layer is added to an internal layered structure thereof, an N-type substrate can be thinner than the NPT IGBT. When the reverse blocking is carried out, if the voltage is higher, the electric field linearly decreases after penetrating into the N-type substrate, and the electric field termination layer can cut off the rest electric field.
Most of the existing FS IGBT processes are as shown in FIG. 1, FZ-wafer (N-) is used as a starting material, after a front cell is manufactured into a thinned silicon wafer, phosphorus is injected into the back of silicon to form an N-type field stop layer, finally boron is injected to form a P + collector region, and back metal is deposited to serve as a collector after laser annealing. For example, chinese patent publication No. CN104299900A (published as 1/21/2015) discloses a method for manufacturing a field stop type insulated gate bipolar transistor, in which a heavily doped N-type epitaxial layer is epitaxially grown on a substrate as a field stop layer, then N-type impurities are injected into the field stop layer, then a lightly doped N-type epitaxial layer is epitaxially grown as a voltage-withstanding layer, then a conventional front process is performed, then a back thinning process is performed, then P-type impurities are injected into the back and annealed to form a P-type collector region, and then a conventional back metallization process is performed.
The existing structure needs lower Vce (sat), the wafer needs to be ground to be very thin, in order to reduce the risk of subsequent fragment, a TAIKO process is adopted to improve the strength of the wafer during grinding, and a grinding machine used in the process has higher price, so that the production cost is improved; in addition, in order to cut off the electric field by the field stop layer, the doping concentration must be appropriate (usually, the doping concentration of the field stop layer is 10) in addition to precisely controlling the thickness of the field stop layer15cm-3～1015cm-3In between) so that the back side high energy implantation and laser annealing are required in the manufacturing process, the equipment and the machine needed by the two processes also have the problem of higher price.
In conclusion, the FS IGBT in the prior art has the problem of high manufacturing cost and needs to be solved.
Disclosure of Invention
To overcome the above-mentioned deficiencies in the prior art, the present invention provides an insulated gate bipolar transistor structure and a method for manufacturing the same, wherein the insulated gate bipolar transistor comprises
The substrate is horizontally placed, and an upward surface is defined as a front side and a downward surface is defined as a back side;
an epitaxial layer formed on a front side of the substrate, the epitaxial layer comprising:
a collector region of the first conductivity type, and
a cut-off region of the second conductivity type on the collector region, and
a drift region of the second conductivity type over the cut-off region;
and a collector located on a back side of the substrate or a front side of the epitaxial layer;
the epitaxial layer is provided with a deep groove structure, the deep groove structure penetrates through the cut-off region and the substrate to the back side of the substrate, a connecting layer is formed on the bottom surface and the side wall of the deep groove structure, the connecting layer is of the first conduction type, and the collector electrode is connected with the collector region through the connecting layer.
In an embodiment, the collector comprises a first collector formed on the back side of the substrate, the first collector covering the bottom of the connection layer.
In one embodiment, the collector includes a second collector formed on the positive side of the epitaxial layer and located in and above the deep trench structure, the second collector extending to the bottom of the deep trench structure and connected to the connection layer.
In an embodiment, the substrate has the second conductivity type.
In one embodiment, the substrate has a first concentration of the dopant of the second conductivity type, the cut-off region has a second concentration of the dopant of the second conductivity type, the drift region has a third concentration of the dopant of the second conductivity type, and the first concentration, the second concentration, and the third concentration decrease in sequence;
the collector region has a fourth concentration of the dopant of the first conductivity type and the connection layer has a fourth concentration of the dopant of the first conductivity type.
In one embodiment, the first conductivity type comprises P-type, and the second conductivity type comprises N-type;
the first concentration is 1e19cm-3-9e17cm-3；
The second concentration is 1e15cm-3-9e17cm-3；
The third concentration is 1e13cm-3-9e16cm-3；
The fourth concentration is 1e14cm-3-2.5e19cm-3
In one embodiment, the collector region has a thickness in a range of 2 to 10 microns;
the cut-off region has a thickness in the range of 10 to 30 microns.
The invention also provides a manufacturing method of the insulated gate bipolar transistor, which comprises the following steps:
providing a substrate;
sequentially growing a collector region of a first conduction type, a cut-off region of a second conduction type and a drift region of the second conduction type on the front side of the substrate;
sequentially penetrating the drift region, the cut-off region and the collector region from the front side of the drift region through etching to form a deep groove structure, wherein the bottom surface of the deep groove structure is positioned in the substrate;
implanting impurities of the first conductivity type into the inner wall and the bottom surface of the deep groove structure to form a connecting layer;
removing material from the back side of the substrate to expose the bottom of the connection layer;
and depositing to form a collector electrode in contact with the bottom of the connecting layer.
In one embodiment, forming a guard ring on and in the drift region after growing the drift region is further included.
In one embodiment, the method further comprises forming at least one positive side unit cell on and in the drift region after growing the drift region.
Based on the above, compared with the prior art, the insulated gate bipolar transistor structure provided by the invention, the collector region, the cut-off region and the drift region are formed in sequence by growing on the substrate, and the collector and collector region are in metal contact by the arrangement of the deep groove structure and the connecting layer, the respective doping concentrations of the cut-off region and the drift region can be controlled in the growth process, so that the invention has wider selection range for the substrate, for the prior art method of forming the collector region of the stop region by backside high energy ion implantation and laser annealing, the substrate is usually made of a semiconductor material with low doping concentration, and in order to obtain a low vce (sat), the wafer is very thin to be ground, further, the strength of the wafer polished to be very thin needs to be improved by the TAIKO process, and the present invention does not need expensive equipment in the above process and has a low production cost.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts; in the following description, the drawings are illustrated in a schematic view, and the drawings are not intended to limit the present invention.
FIG. 1 is a schematic process diagram of an FS IGBT in the prior art;
FIG. 2 is a schematic partial cross-sectional view of an IGBT structure provided by the present invention;
FIG. 3 is a simplified top view of the relative distribution among the cell region, the termination region and the deep trench structure according to an embodiment of the present invention;
fig. 4-6 are schematic partial cross-sectional views of the IGBT shown in fig. 2 at various stages in its manufacture;
fig. 7 is a simulation test chart of the withstand voltage curve of the IGBT provided by the present invention.
Reference numerals:
100 substrate 200 epitaxial layer 210 collector region
220 cut-off 230 drift 240 deep trench structure
241 second connection portion 250 connecting the collector of the layer 300
310 first collector 320 second collector 400 cell region
410 positive side cell 411 gate oxide layer 412 gate region
413P well region 414 emitter region 500 termination region
510 guard ring 511 guard ring field 512 field oxide
600 emitter 610 first connection 620 contact
700 passivation layer
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments; the technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other; all other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be noted that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs, and are not to be construed as limiting the present invention; it will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The invention provides an insulated gate bipolar transistor structure which comprises
A substrate 100, wherein when the substrate 100 is horizontally placed, an upward side is defined as a front side, and a downward side is defined as a back side;
an epitaxial layer 200, the epitaxial layer 200 being formed on a front side of the substrate, the epitaxial layer 200 comprising:
a collector region 210 of the first conductivity type, and
a cut-off region 220 of the second conductivity type on the collector region 210, and
a drift region 230 of the second conductivity type on the cut-off region 220;
and a collector 300, the collector 300 being located at a back side of the substrate 100 or a front side of the epitaxial layer 200;
wherein, a deep trench structure 240 is formed on the epitaxial layer 200, the deep trench structure 240 penetrates through the cut-off region 220 and the substrate 100 to the back of the substrate 100, a connection layer 250 is formed on the bottom surface and the sidewall of the deep trench structure 240, the connection layer 250 has the first conductivity type, and the collector 300 is connected to the collector 210 through the connection layer 250.
The present invention is described in the following embodiments, which are all described by taking an FS IGBT in which the collector region 210 is a P-type as an example, and therefore the semiconductor of the first conductivity type in the following embodiments is a P-type semiconductor and the semiconductor of the second conductivity type is an N-type semiconductor.
In one embodiment, referring to fig. 2, an epitaxial layer 200 is formed on the front side of a substrate 100, the substrate 100 having a doping concentration of, for example, 2.5e20cm-3Compared with the prior art, the CZ-wafer of the N + substrateThe FZ-wafer (N-) substrate used in the technology is less expensive, the epitaxial layer 200 comprises a P + collector region 210 having a thickness in the range of 2 to 10 μm formed first on the front side of the substrate 100, the P + collector region 210 having a doping concentration of, for example, 2.5e19cm-3And then forming an N-cut region 220 with a thickness ranging from 10 to 30 micrometers by growing on the front side of the collector region 210, and further forming an N-drift region 230 with a thickness ranging from 30 to 70 micrometers on the front side of the cut region 220. In addition, referring to fig. 2, the IGBT of the present embodiment further includes a deep trench structure 240, the deep trench structure 240 sequentially penetrates the drift region 230, the stop region 220, and the collector region 210 from the front side of the drift region 230 to the substrate 100, and P-type ions are implanted into the sidewalls and the bottom surface of the deep trench structure 240, with implantation parameters, such as B11/20Kev/2E15, B11/35Kev/5E13, to form a P + connection layer 250, and the bottom of the connection layer 250 is flush with the back surface of the substrate 100. The IGBT provided in this embodiment further includes a Collector 300(Collector) metal layer, and the Collector 300 is connected to the P + Collector region 210 through a bottom contact of the connection layer 250.
Referring to fig. 2, in some embodiments, the epitaxial layer 200 further includes a Cell region 400(Cell) having a plurality of cells 410 on the positive side of the drift region 230 and a Termination region 500(Termination) having a guard ring 510, fig. 2 is a partial cross-sectional view including a sidewall of an IGBT transistor, as can be seen from fig. 3, in a top view of the IGBT transistor, the Cell region 400 is distributed in a central region of the transistor, a ring-shaped Termination region 500 is arranged around the Cell region 400, and a ring-shaped deep trench structure 240 is distributed around the periphery of the Termination region 500. Specifically, on the basis of the above embodiment, the cell region 400 includes a plurality of cells 410 having at least one positive side, and the positive side cells 410 are part of a vertical field effect transistor having the gate structure 210. Specifically, referring to fig. 2, the positive side cell 410 includes a gate region 412 surrounding a gate oxide layer 411 formed in the drift region 230 near the positive side, and a P well region 413 and an N + emitter region 414 formed by sequential implantation from the positive side of the drift region 230, wherein the P well region 413 is located between the N + emitter region 414 and the drift region 230, and the gate region 412 surrounding the gate oxide layer 411 passes through the P well region 413. Preferably, the doping concentration of the N + emitter region 414 is relatively higher than the doping concentration of the N-drift region 230.
In the cell area 400 of the IGBT shown in fig. 2, the P + Collector region 210, the N-cut region 220, the N-drift region 230, and the P-well region 413 constitute a vertical PNP bipolar transistor, wherein the P + Collector region 210 is a P-type Collector of the vertical PNP bipolar transistor and is also used as a conductive Collector of the whole IGBT for connecting with a Collector (Collector)300 metal layer, the N-cut region 220 and the N-drift region 230 form an N-type base of the vertical PNP bipolar transistor, and the P-well region 413 is used as a P-type emitter of the vertical PNP bipolar transistor. In the vertical field effect transistor structure of the positive side cell 410, the gate region 412 surrounding the gate oxide layer 411 is used as the gate thereof, the P well region 413 is used as the channel region of the vertical field effect transistor as well as the P-type Emitter of the vertical PNP bipolar transistor, and the N + Emitter region 414 is used as the conductive Emitter of the IGBT as a whole as well as the N-type source of the vertical field effect transistor for metal connection with the Emitter (Emitter) 600. More specifically, the P-well region 413 adjacent to the gate region 412 surrounding the gate oxide 411 provides the vertical P-channel of the field effect transistor, and thus the current conduction between the base of the field effect transistor and the vertical PNP bipolar transistor can be controlled by the voltage applied to the gate region 412.
Preferably, referring to fig. 2, the emitter 600 metal is formed on the positive side of the cell 410 with the positive side and electrically connected to the P-well region 413, i.e., the P-type emitter of the vertical PNP bipolar transistor. The emitter 600 metal further includes a first connection portion 610, the first connection portion 610 is made of, for example, a deposited metal including titanium (Ti), titanium nitride (TiN), and tungsten (W), and the bottom of the first connection portion 610 contacts the P-well region 413, which extends to the emitter 600 metal formed on the front side of the cell region 400 through a via hole.
A gate metal contact (not shown) may be formed on the positive side of the IGBT similar to the emitter 500 metal contact and electrically connected to the gate region 412 of the positive side cell 410, and the gate oxide 411 may provide an opening (not shown) while covering the protective gate region 412 so that the gate region 412 and the gate metal conductive contact of the IGBT form an external electrical connection.
Preferably, referring to fig. 2, in some embodiments, the emitter 600 metal contact structure further includes a P + contact region 620 formed in a region where the P well region 413 contacts the first connection portion 610, and the P + contact region 620 is formed by implanting highly doped P-type ions, such as B11/20Kev/2E15, B11/35Kev/5E13, at the bottom of the via hole and performing a high temperature anneal (1000C/0.25min) before depositing the first connection portion 610.
Referring to fig. 2, in some embodiments, the collector 300 includes a first collector 310, the first collector 310 is formed on the backside of the substrate 100, and the first collector 310 covers the metal contact of the connection layer 250 exposed at the bottom of the substrate 100 to form the drip collector 310. Alternatively, the collector 300 includes a second collector 320 formed in the deep trench structure 240 and above the deep trench structure 240, specifically, the deep trench structure 240 includes an inter-level dielectric (ILD) covering sidewalls of the connection layer 250 but exposing a bottom of the connection layer 250, the second collector 320 includes a second connection portion 241 deposited in the deep trench structure 240 covering the ILD, the second connection portion 241 is, for example, a deposited metal including titanium (Ti), titanium nitride (TiN), and tungsten (W), a bottom of the second connection portion 241 is in contact with a bottom of the connection layer 250, and a metal of the second collector 320 is formed on an upper portion of the second connection portion 241.
Preferably, in some embodiments,.
In summary, in the igbt structure provided by the present invention, the collector region, the stop region, and the drift region are sequentially formed by growing on the substrate, and the collector and collector region are in metal contact by the arrangement of the deep trench structure and the connection layer, and the doping concentrations of the stop region and the drift region can be controlled during the growth process, so that the substrate has a wider selection range, whereas for the prior art in which the collector region of the stop region is formed by back-side high-energy ion implantation and laser annealing, the substrate is usually made of a semiconductor material with a low doping concentration, and in order to obtain a lower vce (sat), the wafer is ground to be very thin, and further the strength of the wafer ground to be very thin needs to be improved by the TAIKO process, and the present invention does not need to adopt expensive equipment in the above processes, and has a lower production cost.
The invention also provides a manufacturing method of the insulated gate bipolar transistor, which comprises the following steps:
providing a substrate 100;
sequentially growing a collector region 210 of a first conductivity type, a cut-off region 220 of a second conductivity type and a drift region 230 of the second conductivity type on the front side of the substrate 100;
forming a deep trench structure 240 by etching from the front side of the drift region 230 to penetrate the drift region 230, the stop region 220 and the collector region 210 in sequence, wherein the bottom surface of the deep trench structure 240 is located in the substrate 100;
implanting the first conductive type impurities into the inner wall and the bottom surface of the deep trench structure 240 to form a connection layer 250;
removing material from the back side of the substrate 100 to expose the bottom of the connection layer 250;
a collector electrode 300 is deposited in contact with the bottom of the connection layer 250.
Preferably, forming a guard ring 510 on said drift region 230 and in said drift region 230 after growing said drift region 230 is further included.
Preferably, the method further comprises forming at least one positive side unit cell 410 on the drift region 230 and in the drift region 230 after growing the drift region 230.
In specific implementation, referring to fig. 4 to 6 and fig. 2, the present embodiment will be described by taking a manufacturing method of a novel FS IGBT with a withstand voltage of 600V as an example.
Referring to FIG. 4, a concentration of 2.5e20cm is provided-3The CZ-wafer as the N + substrate 100 grows a 4um thick P + collector region 210 on the substrate 100, then grows an 18um N-stop region 220, and then grows an 53um thick N-drift region 230 to form the structure shown in fig. 4;
next, referring to fig. 5, a guard ring pattern is formed on the surface of the positive side of the N-drift region 230 by photolithography, B11/130Kev/8E12 is implanted, the photoresist is removed, a high temperature anneal (1175C/80min) is performed to form a guard ring Field 511, then a Field Oxide layer 512(Field Oxide) with a thickness of 1.0um is grown on the surface of the positive side of the N-drift region 230 to cover the guard ring Field 511, and then the Field Oxide layer 512 is removed by photolithography etching so that the remaining Field Oxide layer 512 is located right above the guard ring Field 511.
Then, an oxide layer (not shown) with a certain thickness is grown on the front side surface of the whole structure under the state, the oxide layer and the N-drift region 230 are respectively removed by photolithography and etching to form a gate trench, and after the etching is finished, the photoresist and the remaining oxide layer (not shown) are removed. Then, a gate oxide layer 411 with a thickness of 4000 angstroms is formed on the inner wall of the gate trench by oxidation, polysilicon is deposited in the gate trench with the gate oxide layer 411 attached, and the polysilicon is etched by photolithography to the position of the positive side surface of the N-drift region 230 at this time, so as to form a gate region 412. Then, B11/40Kev/1.4E13, B11/90Kev/1.1E13 and B11/120Kev/1.4E13 are implanted in sequence, and then high-temperature annealing (1175C/80min) is carried out to form the P well region 413. Followed by a photolithographic implantation of As75/60Kev/8E15 followed by a high temperature anneal (950C/30min) to form N + emitter region 414.
Then an oxide layer HM of a certain thickness is grown, the oxide is removed by photolithography etching, and referring to fig. 3, the N-drift region 230 is etched outside the termination region 400 from a top view to form a deep trench structure 240 and sequentially penetrates through the N-drift region 230, the N-stop region 220 and the P + collector region 210 so that the bottom of the deep trench structure 240 is in the N + substrate 100 in this state. After etching, B11/20Kev/2E15 and B11/35Kev/5E13 are implanted in sequence, high-temperature annealing (1000C/0.25min) is carried out to form a connecting layer 250, and finally the structure shown in FIG. 5 is formed. It should be noted that the implantation direction of the dopant ions during the formation of the connection layer 250 should be 5-15 degrees, preferably 7 degrees in the present embodiment, with respect to the sidewall of the deep trench structure, so that the connection layer 250 covers the inner wall of the deep trench structure 240.
Next, referring to fig. 6, the blocking oxide layer HM is removed, and in this state, an ILD layer with a thickness of 0.4um is grown on the surface of the whole front side of the structure as an insulating protection layer, and at this time, the ILD covers all the surfaces exposed on the whole front side of the structure, including the surface of the front side of the N + emitter 414 and the sidewalls and bottom of the P + connection layer 250. Photolithography and etching are then performed to remove the N + emitter 414 and ILD above the P + contact 620 to form a connecting via, and at the same time, the ILD overlying the bottom of the connecting layer 250 is removed to expose a side of the bottom of the connecting layer 250 facing the front side. Then, B11/20Kev/2E15 and B11/35Kev/5E13 are sequentially implanted into the exposed P well region 413 at the bottom of the connecting via hole, and high-temperature annealing (1000C/0.25min) is performed to form a P + contact region 620(contact), so that the structure shown in FIG. 6 is formed.
Then, referring to fig. 2, a Ti or TiN layer is plated in the connection via and the ILD deep trench structure 240 covered, tungsten is deposited, and then etched to the surface position of the ILD to form a first connection portion 610 and a second connection portion 241; next, metal is deposited on the surface of the ILD and a metal Emitter 500(Emitter), a second Collector 320(Collector) and a gate (gate, not shown) are formed by photolithography etching, and a passivation layer 700 is deposited and passivation protection is formed by photolithography etching to complete the front side process.
For the backside, the N + substrate 100 is first ground to a desired thickness where the bottom of the connection layer 250 is exposed, and then the backside of the substrate 100 is polished, cleaned, evaporated, alloyed to form a backside metal as the first Collector 310 (Collector).
As shown in a voltage withstanding curve diagram of FIG. 7 obtained through simulation tests, the IGBT voltage withstanding value obtained through the method is about 625V, and the requirement of >600V is met.
In summary, according to the IGBT manufacturing method provided by the present invention, by providing a deep trench structure outside the termination region of the IGBT, the FS IGBT manufacturing process can be performed using CZ-wafer (N +) as a starting material, and since the bottom N + substrate does not participate in the conduction, a certain thickness of the wafer can be ensured during the grinding without affecting vce (sat) and the TAIKO process is avoided to prevent the wafer from being broken; the formation of the P + collector region and the N-type field stop layer can be realized by growing instead of implanting, so that the thickness and doping concentration of the field stop layer can be controlled more easily during processing and back high-energy implantation and laser annealing are not needed.
In addition, if the structure IGBT adopts clip technology in subsequent packaging, the device has better heat dissipation effect because the front side and the back side are conducted simultaneously.
In addition, it will be appreciated by those skilled in the art that, although there may be many problems with the prior art, each embodiment or aspect of the present invention may be improved only in one or several respects, without necessarily simultaneously solving all the technical problems listed in the prior art or in the background. It will be understood by those skilled in the art that nothing in a claim should be taken as a limitation on that claim.
Although terms such as substrate, epitaxial layer, collector region, cut-off region, drift region, deep trench structure, second connection, connection layer, collector, first collector, second collector, cell region, positive side cell, gate oxide, gate region, P-well region, emitter region, termination region, guard ring field, field oxide layer, emitter, first connection, contact region, and passivation layer are used more often herein, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed as being without limitation to any additional limitations that may be imposed by the spirit of the present invention; the terms "first," "second," and the like in the description and in the claims, and in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. An insulated gate bipolar transistor structure is characterized by comprising
The substrate is horizontally placed, and an upward surface is defined as a front side and a downward surface is defined as a back side;
an epitaxial layer formed on a front side of the substrate, the epitaxial layer comprising:
a collector region of the first conductivity type, and
a cut-off region of the second conductivity type on the collector region, and
a drift region of the second conductivity type over the cut-off region;
and a collector located on a back side of the substrate or a front side of the epitaxial layer;
the epitaxial layer is provided with a deep groove structure, the deep groove structure penetrates through the cut-off region and the substrate to the back side of the substrate, a connecting layer is formed on the bottom surface and the side wall of the deep groove structure, the connecting layer is of the first conduction type, and the collector electrode is connected with the collector region through the connecting layer.
2. The igbt structure of claim 1, wherein: the collector includes a first collector formed on a backside of the substrate, the first collector covering a bottom of the connection layer.
3. The igbt structure of claim 1, wherein: the collector comprises a second collector, the second collector is formed on the positive side of the epitaxial layer and is positioned in the deep groove structure and above the deep groove structure, and the second collector extends to the bottom of the deep groove structure and is connected with the connecting layer.
4. The igbt structure of claim 1, wherein: the substrate has the second conductivity type.
5. The igbt structure of claim 4, wherein: the substrate has a first concentration of the dopant of the second conductivity type, the cut-off region has a second concentration of the dopant of the second conductivity type, the drift region has a third concentration of the dopant of the second conductivity type, the first concentration, the second concentration, and the third concentration decrease in sequence;
the collector region has a fourth concentration of the dopant of the first conductivity type and the connection layer has a fourth concentration of the dopant of the first conductivity type.
6. The igbt structure of claim 5, wherein: the first conductivity type comprises a P-type, and the second conductivity type comprises an N-type;
the first concentration is 1e19cm-3-9e17cm-3；
The second concentration is 1e15cm-3-9e17cm-3；
The third concentration is 1e13cm-3-9e16cm-3；
The fourth concentration is 1e14cm-3-2.5e19cm-3。
7. The igbt structure of claim 6, wherein: the collector region has a thickness in a range of 2 to 10 microns;
the cut-off region has a thickness in the range of 10 to 30 microns.
8. A method for manufacturing an Insulated Gate Bipolar Transistor (IGBT) is characterized by comprising the following steps:
providing a substrate;
sequentially growing a collector region of a first conduction type, a cut-off region of a second conduction type and a drift region of the second conduction type on the front side of the substrate;
sequentially penetrating the drift region, the cut-off region and the collector region from the front side of the drift region through etching to form a deep groove structure, wherein the bottom surface of the deep groove structure is positioned in the substrate;
implanting impurities of the first conductivity type into the inner wall and the bottom surface of the deep groove structure to form a connecting layer;
removing material from the back side of the substrate to expose the bottom of the connection layer;
and depositing to form a collector electrode in contact with the bottom of the connecting layer.
9. The method for manufacturing an insulated gate bipolar transistor according to claim 8, wherein: and forming a guard ring on and in the drift region after the drift region is grown.
10. The method for manufacturing an insulated gate bipolar transistor according to claim 9, wherein: and forming at least one positive side unit cell on the drift region and in the drift region after the drift region is grown.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116544272A (en) * | 2023-07-06 | 2023-08-04 | 上海陆芯电子科技有限公司 | Reverse-conduction IGBT device and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006054248A (en) * | 2004-08-10 | 2006-02-23 | Fuji Electric Device Technology Co Ltd | Semiconductor and its manufacturing method |
| CN101378073A (en) * | 2007-08-30 | 2009-03-04 | 东部高科股份有限公司 | Insulated gate bipolar transistor and method for manufacturing the same |
| DE102008046388A1 (en) * | 2008-09-09 | 2010-03-18 | Infineon Technologies Ag | Vertical bipolar transistor has collecting region and collector connecting trench for fixing collecting region, where collector connecting trench is filled with electrically conductive filling material |
| KR101259895B1 (en) * | 2011-12-29 | 2013-05-02 | 주식회사 동부하이텍 | Lateral insulated-gate bipolar transistor and method for configuring thereof |
| CN216389384U (en) * | 2021-11-30 | 2022-04-26 | 厦门芯达茂微电子有限公司 | Insulated gate bipolar transistor structure |
-
2021
- 2021-11-30 CN CN202111472626.9A patent/CN113990945B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006054248A (en) * | 2004-08-10 | 2006-02-23 | Fuji Electric Device Technology Co Ltd | Semiconductor and its manufacturing method |
| CN101378073A (en) * | 2007-08-30 | 2009-03-04 | 东部高科股份有限公司 | Insulated gate bipolar transistor and method for manufacturing the same |
| DE102008046388A1 (en) * | 2008-09-09 | 2010-03-18 | Infineon Technologies Ag | Vertical bipolar transistor has collecting region and collector connecting trench for fixing collecting region, where collector connecting trench is filled with electrically conductive filling material |
| KR101259895B1 (en) * | 2011-12-29 | 2013-05-02 | 주식회사 동부하이텍 | Lateral insulated-gate bipolar transistor and method for configuring thereof |
| CN216389384U (en) * | 2021-11-30 | 2022-04-26 | 厦门芯达茂微电子有限公司 | Insulated gate bipolar transistor structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116544272A (en) * | 2023-07-06 | 2023-08-04 | 上海陆芯电子科技有限公司 | Reverse-conduction IGBT device and preparation method thereof |
| CN116544272B (en) * | 2023-07-06 | 2023-10-03 | 上海陆芯电子科技有限公司 | Reverse-conduction IGBT device and preparation method thereof |
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