CN111354396A - Memory and write assist circuit thereof - Google Patents
Memory and write assist circuit thereof Download PDFInfo
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- CN111354396A CN111354396A CN201811567627.XA CN201811567627A CN111354396A CN 111354396 A CN111354396 A CN 111354396A CN 201811567627 A CN201811567627 A CN 201811567627A CN 111354396 A CN111354396 A CN 111354396A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
A memory and a write assist circuit thereof. The write assist circuit includes: the potential pull-down circuit is coupled with a pre-charge signal end of a write bit line of the memory and is suitable for carrying out more than two times of potential pull-down operations through a capacitor contained in the memory before triggering the memory to carry out write operation, and the potential of the pre-charge signal end is pulled down to a preset negative potential. By applying the scheme, the area occupied by the capacitor in the write auxiliary circuit can be reduced.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a memory and a write assist circuit thereof.
Background
With the development of the process, the design of Static Random-Access Memory (SRAM) is more and more challenging due to the variation of the process parameters, wherein the stability of the write operation is a big difficulty.
In order to improve the noise resistance of the write operation of the SRAM, a write assist circuit is added in the SRAM, the output of the write assist circuit is connected with a bit line of the write operation circuit, and the bit line of the write operation circuit is pulled down to a negative value by the write assist circuit, so that the speed of the write operation can be improved, and the stability of the write operation can be improved.
In the conventional write assist circuit, the bit line is pulled down by a charge pump, and the charge pump function is completed by a capacitor. However, in the conventional write assist circuit, the capacitance value of the required capacitor is large, so that the required capacitor occupies a small area in a layout, and finally the whole area of the SRAM is increased, which is not beneficial to the mass production of the SRAM.
Disclosure of Invention
The invention aims to solve the problems that: how to reduce the area occupied by the capacitor in the write assist circuit.
To solve the above problem, an embodiment of the present invention provides a write assist circuit for a memory, where the write assist circuit includes: the potential pull-down circuit is coupled with a pre-charge signal end of a write bit line of the memory and is suitable for carrying out more than two times of potential pull-down operations through a capacitor contained in the memory before triggering the memory to carry out write operation, and the potential of the pre-charge signal end is pulled down to a preset negative potential.
Optionally, the potential pull-down circuit includes: switch sub-circuit, electric potential pull-down sub-circuit and electric potential pull-up sub-circuit, wherein: the input end of the switch sub-circuit is respectively coupled with the potential pull-down sub-circuit and the potential pull-up sub-circuit, the output end of the switch sub-circuit is coupled with the pre-charging signal end, and the control end of the switch sub-circuit is coupled with the first control signal output end and is suitable for controlling the connection between the potential pull-down sub-circuit and the pre-charging signal end to be switched on and off based on a first control signal; the input end of the potential pull-down sub-circuit is coupled with the output end of the driving voltage signal, the output end of the potential pull-down sub-circuit is coupled with the switch sub-circuit and the potential pull-up sub-circuit, and the potential pull-down sub-circuit is suitable for carrying out potential pull-down operation on the potential of the pre-charging signal end through a capacitor contained in the potential pull-down sub-circuit when the potential pull-down sub-circuit is connected with the pre-charging signal end; the input end of the potential pull-up sub-circuit is coupled with the output end of the potential pull-down sub-circuit, the output end of the potential pull-up sub-circuit is grounded, the control end of the potential pull-up sub-circuit is coupled with the output end of the second control signal, and the potential pull-up sub-circuit is suitable for executing potential pull-up operation on the potential of the output end of the potential pull-down sub-circuit based on the second control signal when the connection between the potential pull-down sub-circuit and the pre-charge.
Optionally, the first control signal, the driving voltage signal, and the second control signal are all periodic digital signals.
Optionally, the switch sub-circuit is adapted to control the potential pull-down sub-circuit to maintain connection with the pre-charge signal terminal during a rising edge period of the first control signal, and control the potential pull-down sub-circuit to disconnect from the pre-charge signal terminal during a falling edge period of the first control signal; the number of times of the first control signal being on the rising edge is greater than or equal to two times from the starting time of the writing auxiliary circuit to the time of triggering the memory to execute the writing operation.
Optionally, the switch is a self-circuit comprising: a first MOS transistor.
Optionally, the potential pull-down sub-circuit is adapted to perform a potential pull-down operation on the potential of the pre-charge signal terminal during a period when the driving voltage signal is at a falling edge.
Optionally, the potential pull-down sub-circuit includes: a first inverter coupled to the driving voltage signal output terminal; a second inverter coupled to the first inverter; a capacitor coupled to the second inverter.
Optionally, the potential pull-up sub-circuit is adapted to perform a potential pull-up operation on a potential at an output terminal of the potential pull-down sub-circuit during a period in which the second control signal is at a falling edge.
Optionally, the potential pull-up sub-circuit comprises: and a second MOS transistor.
Optionally, the write assist circuit further comprises: and the switching circuit is suitable for triggering the start or end of the operation of the potential pull-down circuit.
Optionally, the switching circuit comprises: and the grid electrode of the third MOS tube is coupled with the output end of a third control signal, the drain electrode of the third MOS tube is coupled with the output end of the potential pull-down circuit, and the source electrode of the third MOS tube is grounded.
Optionally, the write assist circuit further comprises: and the input end of the signal generating circuit is coupled with the bit line signal output end, the input ends of the signal generating circuit are respectively coupled with the first control signal output end, the driving voltage signal output end, the second control signal output end and the third control signal output end, and the signal generating circuit is suitable for generating the first control signal, the driving voltage signal, the second control signal and the third control signal based on the bit line signal.
Optionally, the memory is a dual port memory.
Optionally, the potential pull-down circuit is adapted to perform a potential pull-down operation on the potential of the pre-charge signal terminal two or more times from a start time of the memory read operation to before triggering the memory to perform the write operation.
The embodiment of the invention also provides a memory, which comprises the write-assist circuit of any one of the memories.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
by applying the scheme of the invention, the potential pull-down circuit is arranged, more than two times of potential pull-down operation can be adopted before the memory is triggered to execute the writing operation, the potential of the writing bit line is pulled down to the preset negative potential, and compared with the situation that the potential of the writing bit line is pulled down to the preset negative potential only by adopting one time of potential pull-down operation, the capacitance value in the potential pull-down circuit can be reduced by at least 1/2, the capacitance value is reduced, the layout area occupied by the capacitance is reduced, the whole area of the memory is reduced finally, and the mass production of the memory is facilitated.
Drawings
FIG. 1 is a timing diagram of signals of a write assist circuit of a memory according to the prior art;
FIG. 2 is a schematic diagram of a write assist circuit of a memory according to an embodiment of the present invention;
FIG. 3 is a timing diagram of signals of a write assist circuit of a memory according to an embodiment of the present invention.
Detailed Description
The traditional dual-port SRAM not only has one group of write operation ports, but also has one group of read operation ports, and the two groups of ports are independent. In the same clock cycle, when performing read-write operation, the first half cycle of the clock cycle may be used to perform read operation, and the second half cycle may be used to complete write operation.
Referring to fig. 1, in the timing of the dual port SRAM read/write operation, the clock signal CK completes the read/write operation from time T0 to time T3. In the read-before-write operation, the time T0 to the time T1 are read operations, and the time T1 to the time T3 are write operations. The rising edge of the Write enable signal Write enable triggers a Write operation at time T2.
At present, before the Write enable signal Write enable triggers a Write operation, the Write assist circuit starts to perform a pull-down operation on the potential of the Write bit line WBL at a start time T0 of the clock signal CK by the output signal BL _ PRE, and pulls down the potential of the Write bit line WBL to a stable negative potential before a time T2, so that when the Write enable signal Write enable triggers a Write operation, the potential of the Write bit line WBL is lowered below VSS, thereby increasing the speed of the Write operation and improving the stability of the Write operation.
However, in the write assist circuit, since the pull-down operation is performed only once on the potential of the write bit line WBL, the capacitance value of the required capacitor is large, so that the required capacitor occupies a small area in the layout, which finally increases the overall area of the SRAM, and is not favorable for mass production of the SRAM.
In order to solve the problem, the invention provides a write assist circuit of a memory, wherein a potential pull-down circuit is arranged in the write assist circuit, and the potential pull-down circuit can pull down the potential of a write bit line to a preset negative potential through more than two potential pull-down operations before triggering the memory to execute write operation, so that the capacitance value in the potential pull-down circuit can be reduced by at least 1/2, the layout area occupied by a capacitor is reduced, the whole area of the memory is reduced, and the mass production of the memory is facilitated.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
An embodiment of the present invention provides a write assist circuit of a memory, and referring to fig. 2, the write assist circuit may include: a potential pull-down circuit 21.
The voltage pull-down circuit 21 is coupled to the precharge signal terminal S1 of the memory write bit line, and is adapted to perform two or more voltage pull-down operations through the capacitor included in the memory before triggering the memory to perform a write operation, so as to pull down the voltage of the precharge signal terminal S1 to a predetermined negative voltage.
In a specific implementation, the potential pull-down circuit 21 includes a capacitor, and before triggering the memory to perform a write operation, only two potential pull-down operations may be performed, or three or less potential pull-down operations may be performed, where the number of times of performing the potential pull-down operations is not limited as long as the potential of the write bit line can be pulled down to a preset negative potential. It can be understood that the more times the potential pull-down operation is performed, the smaller the capacitance value of the capacitor in the potential pull-down circuit is, and the smaller the layout area occupied by the capacitor is.
In a specific implementation, the magnitude of the pull-down of the potential at the end of the pre-charge signal is not limited every time the potential pull-down circuit 21 performs the pull-down operation of the potential. In other words, the magnitude of the potential pull-down on the precharge signal terminal may be the same or different in two adjacent potential pull-down operations.
In a specific implementation, the circuit structure of the potential pull-down circuit is not limited as long as the potential pull-down operation can be performed more than twice through the included capacitor.
In an embodiment of the present invention, referring to fig. 2, the potential pull-down circuit 21 may include: a switch sub-circuit 211, a potential pull-down sub-circuit 212, and a potential pull-up sub-circuit 213. Wherein:
the switch sub-circuit 211, the input terminal of which is coupled to the potential pull-down sub-circuit 212 and the potential pull-up sub-circuit 213, respectively, the output terminal of which is coupled to the pre-charge signal terminal S1 of the write bit line of the memory, and the control terminal of which is coupled to the first control signal output terminal S2, is adapted to control the connection between the potential pull-down sub-circuit 212 and the pre-charge signal terminal S1 based on the first control signal NG 1;
the potential pull-down sub-circuit 212, the input terminal of which is coupled to the driving voltage signal output terminal S3, and the output terminal of which is coupled to the switch sub-circuit 211 and the potential pull-up sub-circuit 213, is adapted to perform a potential pull-down operation on the potential of the pre-charge signal terminal S1 through a capacitor included therein when the potential pull-down sub-circuit 212 is connected to the pre-charge signal terminal S1;
the potential pull-up sub-circuit 213, having an input coupled to the output of the potential pull-down sub-circuit 212, an output coupled to VSS, and a control coupled to the second control signal output S3, is adapted to perform a potential pull-up operation on the potential at the output of the potential pull-down sub-circuit 212 based on the second control signal NG2 when the potential pull-down sub-circuit 212 is disconnected from the pre-charge signal output S1.
In a specific implementation, the switch sub-circuit 211 may control the potential pull-down sub-circuit 212 to be connected to the pre-charge signal terminal S1, and may also control the potential pull-down sub-circuit 212 to be disconnected from the pre-charge signal terminal S1. The potential pull-down sub-circuit 212 performs a potential pull-down operation on the potential of the precharge signal terminal S1 while the connection between the potential pull-down sub-circuit 212 and the precharge signal terminal S1 is maintained, and the potential pull-up sub-circuit 213 performs a potential pull-up operation on the potential of the precharge signal terminal S1 while the connection between the potential pull-down sub-circuit 212 and the precharge signal terminal S1 is disconnected. Wherein the potential pull-down sub-circuit 212 performs the potential pull-down operation on the potential of the precharge signal terminal S1 two or more times before triggering the memory to perform the write operation.
In a specific implementation, for convenience of circuit implementation, the first control signal NG1, the driving voltage signal BoostSignal 1, and the second control signal NG2 may all be periodic digital signals.
In an embodiment of the invention, the periods of the first control Signal NG1, the driving voltage Signal Boost Signal1 and the second control Signal NG2 are the same.
In a specific implementation, the switch sub-circuit 211 is adapted to control the potential pull-down sub-circuit 212 to maintain connection with the pre-charge signal terminal S1 during a rising edge of the first control signal NG1, and to control the potential pull-down sub-circuit 212 to disconnect from the pre-charge signal terminal S1 during a falling edge of the first control signal NG 1.
The number of times that the first control signal NG1 is on a rising edge is greater than or equal to two times from the start time of the operation of the write assist circuit to the time of triggering the memory to perform a write operation. During this period, the switch sub-circuit 211 performs the potential pull-down operation on the pre-charge signal terminal S1 more than twice.
In specific implementations, the switch sub-circuit 211 may have various circuit structures, and is not limited in particular.
In an embodiment of the present invention, the switch sub-circuit 211 may include: the first MOS transistor N1. The first MOS transistor N1 may be a PMOS transistor or an NMOS transistor.
Taking the first MOS transistor N1 as a PMOS transistor, the gate of the first MOS transistor N1 can be coupled to the first control signal output terminal S2, the source thereof is coupled to the output terminal of the potential pull-down sub-circuit 212, and the drain thereof is coupled to the pre-charge signal terminal S1. During the rising edge of the first control signal NG1, the first MOS transistor N1 is turned on, so that the connection between the potential pull-down sub-circuit 212 and the pre-charge signal terminal S1 is maintained, otherwise, the first MOS transistor N1 is turned off, so that the connection between the potential pull-down sub-circuit 212 and the pre-charge signal terminal S1 is disconnected.
In a specific implementation, the potential pull-down sub-circuit 212 is adapted to perform a potential pull-down operation on the potential of the pre-charge Signal terminal S1 during a period when the driving voltage Signal Boost Signal1 is at a rising edge. It is understood that when the driving voltage Signal Boost Signal1 is at the falling edge, the first control Signal NG1 is at the rising edge, i.e. when the connection between the potential pull-down sub-circuit 212 and the pre-charge Signal terminal S1 is maintained, so that the potential pull-down operation on the potential of the pre-charge Signal terminal S1 can be performed by the potential pull-down sub-circuit 212.
In specific implementations, the potential pull-down sub-circuit 212 may have various circuit structures, and is not limited in particular.
In an embodiment of the present invention, the potential pull-down sub-circuit 212 may include: a first inverter INV1 coupled to the driving voltage signal output terminal S3, a second inverter INV2 coupled to the first inverter INV1, and a capacitor C1 coupled to the second inverter INV 2.
The first inverter INV1 inverts the driving voltage Signal Boost Signal1 output from the driving voltage Signal output terminal S3, and the second inverter INV2 inverts the output of the first inverter INV1 again, so that the inverted result is used as the input of the capacitor C1. By providing the first inverter INV1 and the second inverter INV2, the drive voltage Signal Boost Signal1 Signal can be shaped, and a standard potential Signal having the same phase as the drive voltage Signal Boost Signal1 can be generated.
Specifically, when the driving voltage Signal Boost Signal1 is at a falling edge, the potential at the right end a of the capacitor C1 is at the falling edge, so that the potential at the left end b of the capacitor C1 is at the falling edge, and the potential at b is pulled down.
In a specific implementation, the potential pull-up sub-circuit 213 is adapted to perform a potential pull-up operation on the potential at the output terminal of the potential pull-down sub-circuit 212 during the falling edge of the second control signal NG 2. It is understood that the second control signal NG2 is at the falling edge, and the first control signal NG1 is also at the falling edge, i.e. when the connection between the potential pull-down sub-circuit 212 and the pre-charge signal terminal S1 is broken, the potential pull-up sub-circuit 213 performs the potential pull-up operation on the potential at the output terminal of the potential pull-down sub-circuit 212.
In specific implementations, the potential pull-up sub-circuit 213 may have various circuit structures, and is not limited in particular.
In an embodiment of the present invention, the potential pull-up sub-circuit 213 may include: and a second MOS transistor N2. The second MOS transistor N2 may be an NMOS transistor, and has a gate connected to the second control signal output terminal S4, a source connected to the output terminal (i.e., point b) of the potential pull-down sub-circuit 212, and a drain connected to the ground VSS.
When the second control signal NG2 is at the falling edge, the second MOS transistor N2 is turned off, so that the pull-up operation can be performed on the potential at the output terminal of the potential pull-down sub-circuit 212.
In an embodiment of the present invention, in order to more conveniently control an operating state of the write assist circuit of the memory, the write assist circuit of the memory may further include: and the switch circuit 22 is suitable for triggering the start operation or the end operation of the potential pull-down circuit 21.
For example, when the switch circuit 22 is closed, the potential pull-down circuit 21 ends its operation. When the switch circuit 22 is turned off, the potential pull-down circuit 21 starts operating.
In specific implementations, the switch circuit 22 may have various circuit configurations, and is not limited in particular. For example, the switching circuit 22 may include: and a third MOS transistor. The gate of the third MOS transistor may be coupled to the third control signal output terminal S5, the source thereof is coupled to the output terminal of the potential pull-down circuit 21, and the drain thereof is grounded to VSS.
In an embodiment of the present invention, to facilitate circuit implementation, the write assist circuit of the memory may further include: a signal generating circuit 23. The Signal generating circuit 23 may have inputs coupled to a bit line Signal output S6, and inputs coupled to the first control Signal output S2, the driving voltage Signal output S3, the second control Signal output S4, and the third control Signal output S5, respectively, and is adapted to generate the first control Signal NG1, the driving voltage Signal Boost Signal1, the second control Signal NG2, and the third control Signal NG3 based on a bit line Signal.
In specific implementation, the write assist circuit of the memory in the embodiment of the present invention may be applied to a single-port memory, and may also be applied to a dual-port memory.
When the write auxiliary circuit is applied to the single-port memory, the single-port memory only has the write operation circuit, so that the write auxiliary circuit can be adopted to perform pull-down operation on the potential of the precharge signal end of the write operation circuit for more than two times from the initial moment of the clock signal corresponding to the write operation circuit until the potential reaches the preset negative potential.
When the method is applied to the dual-port memory, the dual-port memory not only has one group of write operation ports, but also has one group of read operation ports, and the two groups of ports are mutually independent, so that more than two times of potential pull-down operation can be performed on the potential of the pre-charge signal end from the initial time of the memory read operation to before the memory is triggered to perform the write operation. Although the initial time of the memory read operation is also the initial time of one clock cycle, the clock cycle length of the dual-port memory is longer than that of the single-port memory, and at this time, the potential of the pre-charge signal end can be pulled down to a preset negative potential within a sufficient time, so that the circuit implementation is simpler.
The following describes the working process of the write assist circuit in the implementation of the present invention in detail by taking a dual port memory as an example and combining fig. 2 and fig. 3:
the bit line signal Dummy BL enters the signal generating circuit 23, which generates the following four waveform signals: waveforms of the first control Signal NG2, the driving voltage Signal Boost Signal1, the second control Signal NG2 and the third control Signal NG3 are shown in fig. 3. The Write enable signal Write enable triggers the memory to perform a Write operation at time T7.
At time T0, the third control signal NG3 is at the falling edge, at this time, the third MOS transistor N3 is turned off, the input precharge signal BL _ PRE at the precharge signal terminal S1 is VSS, and the write assist circuit starts to operate, i.e., the potential of the precharge signal BL _ PRE is pulled down to the preset negative potential. The write assist circuit works as follows:
at time T0, the first control signal NG1 is at a high level, the first MOS transistor N1 is closed, and the potential pull-down sub-circuit 212 is connected to the pre-charge signal terminal S1. Since the second control Signal NG2 is at a low level at this time, the second MOS transistor N2 is turned off, and the driving voltage Signal Boost Signal1 is at a falling edge, so that the potential at the point a of the right end of the capacitor C1 is at a falling edge, and the potential at the point b of the left end of the capacitor C1 is pulled down to the negative voltage V1, so that the potential of the precharge Signal BL _ PRE is pulled down to the negative voltage V1.
At time T1, the first control signal NG1 is at a low level, the first MOS transistor N1 is turned off, and the connection between the potential pull-down sub-circuit 212 and the pre-charge signal terminal S1 is also turned off. Since the second control Signal NG2 is at a low level at this time, the second MOS transistor N2 is disconnected, so that the connection between the capacitor C1 and the drain VSS of the second MOS transistor N2 is disconnected, and the driving voltage Signal1 is at a rising edge, so that the potential at the point b at the left end of the capacitor C1 is pulled up to a positive voltage.
At time T2, the second control signal NG2 is at high level, and the second MOS transistor N2 is closed, so that the potential at the point b on the left end of the capacitor C1 is pulled to VSS from a positive voltage.
At time T3, the first control signal NG1 goes high, the first MOS transistor N1 is turned on, and the potential pull-down sub-circuit 212 is connected to the pre-charge signal terminal S1. Since the second control Signal NG2 is at a low level at this time, the second MOS transistor N2 is turned off, and the driving voltage Signal Boost Signal1 is at a falling edge, so that the potential at the point b at the left end of the capacitor C1 is pulled down to the negative voltage V2, and the potential of the precharge Signal BL _ PRE is also pulled down to the negative voltage V2.
At time T4, the first control signal NG1 is at a low level, the first MOS transistor N1 is turned off, and the potential pull-down sub-circuit 212 is disconnected from the precharge signal terminal S1. At this time, the second control Signal NG2 is at a low level, so the second MOS transistor N2 is disconnected, the connection between the capacitor C1 and the second MOS transistor drain VSS is disconnected, and the driving voltage Signal Boost Signal1 is at a rising edge, so the potential at the right end a of the capacitor C1 is at a rising edge, and the potential at the left end b of the capacitor C1 is at a rising edge, and is pulled up to a positive voltage.
At time T5, the second control signal NG2 is at high level, and the second MOS transistor N2 is closed, so that the potential at the point b on the left end of the capacitor C1 is pulled to VSS from a positive voltage.
At time T6, the first control signal NG1 is at a high level, the first MOS transistor N1 is closed, and the potential pull-down sub-circuit 212 is connected to the pre-charge signal terminal S1. Since the second control Signal NG2 is at a low level at this time, the second MOS transistor N2 is turned off, and the driving voltage Signal Boost Signal1 is at a falling edge, so that the potential at the point b at the left end of the capacitor C1 is pulled down to the negative voltage V3, and the potential of the precharge Signal BL _ PRE is also pulled down to the negative voltage V3.
In a specific implementation, before time T7, i.e., before the Write enable signal Write enable reaches a rising edge, the potential of the precharge signal BL _ PRE may be pulled down by a minimum negative potential of about-200 mV. From the beginning of the read operation in the current clock cycle to before the rising edge of the write enable signal comes, the driving voltage signal Boost signal1 can reach a plurality of falling edges, so that a plurality of pull-down operations can be performed on the PRE-charge signal BL _ PRE until the potential of the PRE-charge signal BL _ PRE is pulled down to about-200 mV. It is understood that the more active periods of the driving voltage signal Boost signal1, the smaller the capacitance of the capacitor C1, and the more area is saved.
As can be seen from the above, in the write assist circuit of the memory in the embodiment of the present invention, the potential pull-up operation and the potential pull-down operation are respectively performed on the capacitor C1, so that the potential pull-up operation and the potential pull-down operation on the capacitor C1 are isolated, and thus the potential pull-down operation can be performed on the capacitor C1 for multiple times to reach a final negative potential, and since the magnitude of the pull-down potential is small each time, the capacitance value required by the capacitor C1 is small, so that the layout area occupied by the capacitor can be reduced, the layout area of the write assist circuit can be reduced, and the mass production of the memory is facilitated.
An embodiment of the present invention further provides a memory, where the memory may include the write assist circuit of the memory in any of the above embodiments.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A write assist circuit for a memory, comprising:
the potential pull-down circuit is coupled with a pre-charge signal end of a write bit line of the memory and is suitable for carrying out more than two times of potential pull-down operations through a capacitor contained in the memory before triggering the memory to carry out write operation, and the potential of the pre-charge signal end is pulled down to a preset negative potential.
2. A write assist circuit for a memory as claimed in claim 1, wherein the potential pull-down circuit comprises: switch sub-circuit, electric potential pull-down sub-circuit and electric potential pull-up sub-circuit, wherein:
the input end of the switch sub-circuit is respectively coupled with the potential pull-down sub-circuit and the potential pull-up sub-circuit, the output end of the switch sub-circuit is coupled with the pre-charging signal end, and the control end of the switch sub-circuit is coupled with the first control signal output end and is suitable for controlling the connection between the potential pull-down sub-circuit and the pre-charging signal end to be switched on and off based on a first control signal;
the input end of the potential pull-down sub-circuit is coupled with the output end of the driving voltage signal, the output end of the potential pull-down sub-circuit is coupled with the switch sub-circuit and the potential pull-up sub-circuit, and the potential pull-down sub-circuit is suitable for carrying out potential pull-down operation on the potential of the pre-charging signal end through a capacitor contained in the potential pull-down sub-circuit when the potential pull-down sub-circuit is connected with the pre-charging signal end;
the input end of the potential pull-up sub-circuit is coupled with the output end of the potential pull-down sub-circuit, the output end of the potential pull-up sub-circuit is grounded, the control end of the potential pull-up sub-circuit is coupled with the output end of the second control signal, and the potential pull-up sub-circuit is suitable for executing potential pull-up operation on the potential of the output end of the potential pull-down sub-circuit based on the second control signal when the connection between the potential pull-down sub-circuit and the pre-charge.
3. The write assist circuit of claim 2 wherein the first control signal, the drive voltage signal, and the second control signal are periodic digital signals.
4. The write assist circuit of claim 3, wherein the switch sub-circuit is adapted to control the potential pull-down sub-circuit to remain connected to the pre-charge signal terminal during a rising edge of the first control signal, and to control the potential pull-down sub-circuit to be disconnected from the pre-charge signal terminal during a falling edge of the first control signal;
the number of times of the first control signal being on the rising edge is greater than or equal to two times from the starting time of the writing auxiliary circuit to the time of triggering the memory to execute the writing operation.
5. The write assist circuit of claim 4 wherein the switch self circuit comprises: a first MOS transistor.
6. The write assist circuit of the memory according to claim 4, wherein the potential pull-down sub-circuit is adapted to perform a potential pull-down operation on the potential of the precharge signal terminal during a falling edge of the driving voltage signal.
7. The write assist circuit of claim 6 wherein the potential pull-down sub-circuit comprises:
a first inverter coupled to the driving voltage signal output terminal;
a second inverter coupled to the first inverter;
a capacitor coupled to the second inverter.
8. The write assist circuit of claim 4, wherein the potential pull-up sub-circuit is adapted to perform a potential pull-up operation on a potential at an output terminal of the potential pull-down sub-circuit during a falling edge of the second control signal.
9. The write assist circuit of claim 8 wherein the potential pull-up sub-circuit comprises: and a second MOS transistor.
10. A write assist circuit for a memory as claimed in claim 3, further comprising:
and the switching circuit is suitable for triggering the start or end of the operation of the potential pull-down circuit.
11. A write assist circuit for a memory as claimed in claim 10, wherein said switching circuit comprises:
and the grid electrode of the third MOS tube is coupled with the output end of a third control signal, the drain electrode of the third MOS tube is coupled with the output end of the potential pull-down circuit, and the source electrode of the third MOS tube is grounded.
12. A write assist circuit for a memory as claimed in claim 11, further comprising:
and the input end of the signal generating circuit is coupled with the bit line signal output end, the input ends of the signal generating circuit are respectively coupled with the first control signal output end, the driving voltage signal output end, the second control signal output end and the third control signal output end, and the signal generating circuit is suitable for generating the first control signal, the driving voltage signal, the second control signal and the third control signal based on the bit line signal.
13. A write assist circuit for a memory as claimed in any one of claims 1 to 12 wherein the memory is a dual port memory.
14. The write assist circuit of claim 13, wherein the potential pull-down circuit is adapted to perform the potential pull-down operation on the potential of the precharge signal terminal two or more times from a start time of the memory read operation to before triggering the memory to perform the write operation.
15. A memory comprising the write assist circuit of any one of 1 to 14.
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| CN201811567627.XA CN111354396B (en) | 2018-12-20 | 2018-12-20 | Memory and write assist circuit thereof |
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| CN201811567627.XA CN111354396B (en) | 2018-12-20 | 2018-12-20 | Memory and write assist circuit thereof |
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| US20070268738A1 (en) * | 2006-05-16 | 2007-11-22 | Stephen Keith Heinrich-Barna | Methods and apparatus to provide voltage control for SRAM write assist circuits |
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| CN105009216A (en) * | 2013-03-15 | 2015-10-28 | 美商新思科技有限公司 | Circuit for generating negative bitline voltage |
| CN107507643A (en) * | 2016-06-14 | 2017-12-22 | 展讯通信（上海）有限公司 | SRAM write circuit control method |
| US20180226109A1 (en) * | 2012-03-15 | 2018-08-09 | Intel Corporation | Negative bitline write assist circuit and method for operating the same |
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| US20070268738A1 (en) * | 2006-05-16 | 2007-11-22 | Stephen Keith Heinrich-Barna | Methods and apparatus to provide voltage control for SRAM write assist circuits |
| US20120307574A1 (en) * | 2011-05-31 | 2012-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM READ and WRITE Assist Apparatus |
| US20180226109A1 (en) * | 2012-03-15 | 2018-08-09 | Intel Corporation | Negative bitline write assist circuit and method for operating the same |
| CN105009216A (en) * | 2013-03-15 | 2015-10-28 | 美商新思科技有限公司 | Circuit for generating negative bitline voltage |
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