TW201730885A - Five-transistor static random access memory characterized by controlling the source electrode voltages of the first NMOS transistor (M11) and the second NMOS transistor (M12) according to different operating modes - Google Patents

Abstract

The present invention provides a five-transistor static random access memory mainly comprising a memory array, a plurality of control circuits (2), a plurality of precharging circuits (3), a standby starting circuit (4) and a plurality of word line voltage level conversion circuits (5); the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with one of the control circuits, and each memory cell (1) comprises a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12) and an access transistor (composed of a third NMOS transistor M13). Each of the control circuits (2) is connected to the source electrodes of the first NMOS transistor (M11) and the second NMOS transistor (M12)of each memory cell in the corresponding columns of memory cells to ensure that the source electrode voltages of the first NMOS transistor (M11) and the second NMOS transistor (M12) are controlled according to different operating modes, so that the difficulty of writing in a logic 1 can be effectively avoided during the write-in mode, unnecessary power consumption can also be avoided when the reading speed is increased during a read mode, the leakage current can be effectively reduced during a standby mode, and the original electric characteristics can be kept during the hold mode. Moreover, because of the design of the standby starting circuit (4), a static random access memory ( SRAM) with a single port is effectively promoted to enter the standby mode rapidly, and therefore, the standby efficiency of the SRAM with the single port is effectively increased; in addition, by the design of the plurality of word line voltage level conversion circuits (5), the on-resistance of the third NMOS transistor (M13) in the reading mode is improved, and the interference of half-selected cells during reading is effectively reduced accordingly.

Description

5T static random access memory

The invention relates to a single port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 單埠SRAM, and can effectively improve the reading speed and effectively reduce Leakage current and can solve the problem that SRAM is difficult to write logic 1 with a single bit line.

As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB _1). , MB _{2 ,} etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic diagram of a 6T單埠 SRAM cell, in which PMOS transistors (P1) and (P2) are called load transistors, NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL And BLB are a bit line and a complementary bit line, respectively, since the 單埠SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V _AR ) of the node A must satisfy the equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) < V _TM2 (1)

To effectively prevent half-selected cell disturbance during reading, wherein V _AR represents the initial instantaneous voltage of the reading of node A, and R _M1 and R _M3 respectively represent the NMOS transistor (M1) and The on-resistance of the NMOS transistor (M3), and V _DD and V _TM2 represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), respectively, which results in current driving capability between the driving transistor and the access transistor. The ratio (cell ratio) is usually set between 2.2 and 3.5 (refer to the second column of lines 8-10 of the patent specification No. US76060B2 of October 20, 1998).

The HSPICE transient analysis results of the 6T單埠 SRAM cell shown in Figure 1b during the write operation, as shown in Figure 2, are simulated using the TSMC 90 nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistors P1 and P2. As well as the channel aspect ratio of the NMOS transistors M1, M2, and M3 (i.e., maintaining the same transistor channel width to length ratio as the 6T SRAM cell), there is a problem that writing logic 1 is quite difficult. Considering that the node A on the left side of the memory cell originally stores a logic 0, since the charge of the node A is transmitted only from the bit line (BL) alone, the logic 0 previously written in the node A is overwritten with a logic 1 write. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of the write of node A, R _M1 And R _M3 respectively indicate the on-resistances of the NMOS transistor (M1) and the NMOS transistor (M3). Comparing Equation (1) with Equation (2), the initial transient voltage (V _AW ) is smaller than the NMOS transistor (M2). The threshold voltage (V _TM2 ), and thus the operation of writing logic 1 cannot be completed. The 5T SRAM cell shown in Figure 3, the HSPICE transient analysis simulation result during the write operation, as shown in Figure 4, is simulated using the TSMC 90 nm CMOS process parameters. The simulation results confirm that the 5T SRAM cell with a single bit line has a problem in writing logic 1 that is quite difficult.

In the past, there have been many techniques for a 5T SRAM cell with a single bit line, such as the "Memory System" proposed in Patent Document 1 (US Pat. No. 7,706,062 B2, April 27, 1999), Patent Literature 2 ("TWI426514 B", February 11, 103, "Standard Static Random Access Memory with Reduced Power Supply Voltage During Write Operation", Patent Document 3 (US2014/0029333 A1, January 30, 103) "Five Transistor SRAM Cell", Non-Patent Document 4 (Satyanand Nalam et al., "5T SRAM with asymmetric sizing for improved read stability", IEEE Journal of Solid-State Circuits ., Vol. 46. No. 10, pp 2431-2442, Oct. 2011.), Patent Document 5 (TWI478165, March 21, 104), "High-performance Static Random Access Memory", Non-Patent Document 6 ( Chua-Chin Wang et al., "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40nm process", 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) Patent Document 7 (Shyam Akashe et al., "High d Ensity and low leakage current based 5T SRAM cell using 45nm technology", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov.2011.), etc., which can effectively solve The problem of writing logic 1 is difficult, but none of these techniques considers the word line voltage level conversion circuit to drop the word line voltage applied to the access transistor of the selected cell during the read operation. Up to the power supply voltage, in conjunction with the two-stage read operation, and effective in the first phase of the read operation by pulling the source voltage of the NMOS transistor (M11) from the original ground voltage to below the ground voltage. While increasing the reading speed, it can also effectively reduce the half-selected cell interference during reading, so there is still room for improvement.

In view of the above, the main object of the present invention is to provide a 單埠 static random access memory capable of being applied to a selected cell by a word line voltage level conversion circuit during a read operation. The word line voltage of the crystal is pulled down below the power supply voltage to effectively reduce the half-selected cell interference during reading.

A secondary object of the present invention is to provide a 單埠 static random access memory capable of effectively increasing the reading speed by a control circuit and capable of improving the reading speed by two-stage read control. It also avoids unnecessary power consumption.

Still another object of the present invention is to provide a static random access memory capable of It is quite difficult to control the circuit to effectively avoid the existence of write logic 1 in the SRAM with a single bit line.

The present invention provides a 單埠 static random access memory, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), and a plurality of characters. a line voltage level conversion circuit (5), the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a control circuit, and each memory cell (1) comprising a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS transistor P12 and a first The second NMOS transistor M12 is composed of an access transistor (consisting of a third NMOS transistor M13). Each control unit (2) is connected to a source of the first NMOS transistor (M11) of each memory cell of the corresponding column memory cell and a source of the second NMOS transistor (M12) In order to control the source voltage of the first NMOS transistor (M11) and the source voltage of the second NMOS transistor (M12) in response to different operation modes, thereby effectively preventing the write logic in the write mode 1 difficult problem, in the read mode, can improve the reading speed, but also avoid unnecessary power consumption, in the standby mode, can effectively reduce the leakage current, while maintaining the original electrical mode characteristic. Furthermore, the standby start circuit (4) is designed to effectively prompt the SRAM to quickly enter the standby mode, thereby effectively improving the standby performance of the static random access memory; furthermore, by the plurality of The word line voltage level conversion circuit (5) is designed to increase the on-resistance of the third NMOS transistor (M13) in the read mode, and thus effectively reduce the half-selected cell interference during reading.

BLB ₁ ^... BLB _m ‧‧‧complementary bit line

BLB‧‧‧complementary bit line

MB ₁ ^... MB _k ‧‧‧ memory block

WL ₁ ^... WL _n ‧‧‧ character line

BL ₁ ^... BL _m ‧‧‧ bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

5‧‧‧Word line voltage level conversion Circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

BL‧‧‧ bit line

WLC‧‧‧ word line control signal

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

P21‧‧‧ Third PMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

WC‧‧‧ write control signal

/WC‧‧‧Inverted write control signal

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧4th NMOS transistor

P‧‧‧Precharge signal

M41‧‧11 eleventh NMOS transistor

P41‧‧‧ Fifth PMOS transistor

D2‧‧‧second delay circuit

V _DD ‧‧‧Power supply voltage

WL‧‧‧ character line

R‧‧‧Read signal

/W‧‧‧Inverted write signal

/RW‧‧‧Inverted read/write control signal

P51‧‧‧6th PMOS transistor

M51‧‧‧12th NMOS transistor

M52‧‧‧Thirteenth NMOS transistor

C‧‧‧ node

Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. The write operation timing chart; the third figure shows the circuit diagram of the conventional 5T static random access memory unit cell; the fourth figure shows the write operation timing chart of the conventional 5T static random access memory unit cell; 5 is a schematic circuit diagram showing a preferred embodiment of the present invention; FIG. 6 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 5 during writing; and FIG. 7 is a view showing the fifth drawing; FIG. 8 is a simplified circuit diagram showing a preferred embodiment of the present invention in the fifth embodiment of the present invention; and FIG. 9 is a preferred embodiment of the present invention shown in FIG. Simplified circuit diagram during standby.

According to the above main object, the present invention provides a 單埠 static random access memory, which mainly includes a memory array composed of a plurality of column memory cells and a plurality of row memory cells, each A column of memory cells and each row of memory cells include a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharges Circuit (3), each row of memory cells is provided with a pre-charging circuit (3); a standby starting circuit (4), which causes the SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM; And a plurality of word line voltage level conversion circuits (5), each column memory cell is provided with a word line voltage level conversion circuit (5).

For the sake of explanation, the static random access memory shown in FIG. 5 is only a memory cell (1), a word line (WL), a bit line (BL), a control circuit (2), a precharge circuit (3), a standby start circuit (4), and a word The line voltage level conversion circuit (5) is explained as an embodiment. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS) a first NMOS transistor (M13), wherein the first NMOS transistor and the second NMOS transistor are in an inter-coupled connection, that is, the first The output of the inverter (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell. It should be noted here that the first NMOS transistor (M11) and the second NMOS transistor (M12) have the same channel width to length ratio, the first PMOS transistor (P11) and the second PMOS transistor. (P12) also has the same channel width to length ratio

Referring again to FIG. 5, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), and an inverted write control signal (/) WC), a standby mode control signal (S) and an inverted standby mode control signal (/S). a source, a gate and a drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and a second low voltage node (VL2); a source, a gate and a drain of the fifth NMOS transistor (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); The source of the sixth NMOS transistor (M23) is connected to a ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the seventh NMOS transistor (M24) a source, a gate and a drain are respectively connected to a drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); the eighth NMOS transistor a source, a gate and a drain of (M25) are respectively connected to the accelerated read voltage (RGND), an output of the first delay circuit (D1), and a source of the seventh NMOS transistor (M24); The first delay circuit (D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is Receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source, the gate and the drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage The tenth NM a drain of the OS transistor (M27) and the first low voltage node (VL1); a source, a gate and a drain of the tenth NMOS transistor (M27) are respectively connected to the write control signal (WC) The standby mode control signal (S) and the gate of the ninth NMOS transistor (M26); and the source, the gate and the drain of the third PMOS transistor (P21) are respectively connected to the inverted write The control signal (/WC), the standby mode control signal (S) and the drain of the tenth NMOS transistor (M27). It should be noted here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter, and the inverted write control signal (/WC) is The write control signal (WC) is obtained via another inverter.

It is worth noting here that the drain of the third PMOS transistor (P3), the drain of the tenth NMOS transistor (M27), and the gate of the ninth NMOS transistor (M26) Connected together to form a node (C), when the standby mode control signal (S) is logic low, the voltage level of the node (C) is the voltage level of the inverted write control signal (/WC) When the standby mode control signal (S) is at a logic high level, the voltage level of the node (C) is the voltage level of the write control signal (WC), thereby effectively preventing the write logic At 1 o'clock, the standby mode control signal (S) is at a logic high level due to an unintended factor and thus causes a problem of being unable to write.

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage (ie, the first low voltage node VL1) of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) is set to be a predetermined voltage higher than the ground voltage (ie, The gate-source voltage V _{GS(M23) of} the sixth NMOS transistor (M23) and the source voltage of the other driving transistor (ie, the second NMOS transistor M12) in the selected unit cell (ie, the second The low voltage node VL2) is set to the ground voltage to prevent the difficulty of writing logic 1.

In the first stage of the read mode, the source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) in the cell is selected (ie, the first low voltage node VL1) The acceleration read voltage (RGND) is set to be lower than the ground voltage, and the accelerated read voltage (RGND) is lower than the ground voltage to effectively increase the read speed, and in the second stage of the read mode And setting a source voltage of a driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) in the selected unit cell to a ground voltage to reduce unnecessary power consumption, wherein the reading mode The time between the second phase and the first phase is equal to the read control signal (RC) is changed from the logic low level to the logic high level, and the gate voltage of the eighth NMOS transistor (M25) is reached. Sufficient to close the eighth NMOS transistor (M25), The value can be adjusted by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

The write control signal (WC) in Table 1 is an AND gate operation result of a write signal (W) and the word line (WL) signal, and only the write signal (W) When the signal and the word line (WL) signal are both logic high, the write control signal (WC) is a logic high level; the read control signal (RC) is a read signal (R) and the word The result of the gate operation of the line (WL) signal. It is worth noting here that this read during non-read mode The control signal (RC) is set to the level of the accelerated read voltage (RGND) to prevent leakage current of the seventh NMOS transistor (M24).

Referring to FIG. 5, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P), and the source and gate of the fourth PMOS transistor (P31). Connected to the power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), respectively, to facilitate the precharge signal (P) by logic low level during precharge To precharge the bit line (BL) to the level of the power supply voltage (V _DD ).

Referring to FIG. 5 again, the standby starting circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. The source, the gate and the drain of the fifth PMOS transistor (P41) are respectively connected to a power supply voltage (V _DD ), the inverted standby mode control signal (/S) and the eleventh NMOS transistor ( a drain of M41); a source, a gate and a drain of the eleventh NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) a drain of the fifth PMOS transistor (P41); an input of the second delay circuit (D2) is coupled to the inverted standby mode control signal (/S), and an output of the delay circuit (D1) is coupled to the The gate of the eleventh NMOS transistor (M41).

Referring to FIG. 5 again, the word line voltage level conversion circuit (5) is composed of a sixth PMOS transistor (P51), a twelfth NMOS transistor (M51), and a thirteenth NMOS transistor ( M52), the read signal (R), an inverted write signal (/W), an inverted read/write control signal (/RW), and a word line control signal (WLC), wherein the reading The signal (R) and the inverted write signal (/W) may be from a read/write control pin of the SRAM, and the read operation is indicated when the read/write control pin is at a logic high level (ie, the read signal R is a logic high bit) quasi), The read/write control pin is a logic low-level on-time indicating write operation (ie, the inverted write signal /W is a logic low level, and the write signal W is a logic high level), and the read/write control pin is The inverted signal is equivalent to the inverted read/write control signal (/RW). a source, a gate and a drain of the sixth PMOS transistor (P51) are respectively connected to the word line (WL), the inverted write signal (/W) and the word line control signal (WLC) The source, gate and drain of the twelfth NMOS transistor (M51) are respectively connected to the word line control signal (WLC), the read signal (R) and the word line (WL); The source, gate and drain of the thirteenth NMOS transistor (M52) are respectively connected to the word line control signal (WLC), the inverted read/write control signal (/RW) and the word line. (WL).

The detailed operating voltage level of the word line voltage level conversion circuit (5) is shown in Table 2.

Where V _TN51 represents the threshold voltage of the twelfth NMOS transistor (M51). It should be noted here that the present invention uses two-stage read control to improve the reading speed while avoiding unnecessary power consumption, and on the other hand, the word line voltage level conversion circuit ( 5), in order to effectively lower the word line voltage applied to the access transistor of the selected cell during the read operation to be lower than the power supply voltage (ie, V _DD -V _TN51 ) Selected cell interference.

The working principle of the preferred embodiment of the present invention in FIG. 5 is as follows:

(1) Write mode

Before the start of the write operation, the standby mode control signal (S) is at a logic low level, such that the third PMOS transistor (P21) is turned "ON", and the tenth NMOS transistor (M27) is turned off (OFF). Since the inverted write control signal (/WC) is at a logic high level at this time, the drain of the third PMOS transistor (P21) is at a logic high level, and the logic is at a high level of the third PMOS transistor ( The drain of P21) turns on the ninth NMOS transistor (M26) and causes the low voltage node (VL1) to be grounded.

During the write operation period, the standby mode control signal (S) is a logic low level, but at this time, the inverted write control signal (/WC) is a logic low level, so that the third PMOS transistor (P21) The drain of the third PMOS transistor (P21) causes the ninth NMOS transistor (M26) to be turned off, and the low voltage node (VL1) is equal to the The gate-source voltage V _{GS (M26) of the} sixth NMOS transistor (M23) is thereby effectively prevented from being difficult to write to the logic 1. Figure 6 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during writing.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the SRAM.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V _DD ) when the write operation starts. When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned from OFF (OFF) to Turn on (ON). At this time, because the bit line (BL) is the ground voltage, the node A will maintain the original ground voltage until the end of the write cycle.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, when the writing operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), the node A The voltage will rise following the voltage of the word line control signal (WLC).

When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. Because the bit line (BL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (M11) is still ON and the node B is still at a voltage level close to the power supply voltage ( The initial state of the voltage level of V _DD ), so the first PMOS transistor (P11) is still off (OFF), and the initial transient voltage (V _AW ) of the node A satisfies equation (3): V _AW =V _DD ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TN12 (3)

Wherein, V _AW represents the initial transient voltage of the node A, and R _M11 , R _M13 and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor, respectively. (M23) the on-resistance, and V _DD and V _TN12 respectively represent the power supply voltage and the threshold voltage of the second NMOS transistor (M12), so that the problem of writing logic 1 is difficult to avoid, at this time, because of the third The NMOS transistor (M13) still operates in a saturation region and the first NMOS transistor (M11) still operates in a triode region, although the on-resistance of the third NMOS transistor (M13) (R) _M13 ) is greater than the on-resistance (R _M11 ) of the first NMOS transistor (M11), but since the sixth NMOS transistor (M23) is diode-connected, the first low-voltage node (VL1) Providing a voltage level equal to the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23), and the resulting voltage-divided voltage level at node A is higher than that of the fourth It is known that the voltage level of the node A of the 5T static random access memory cell is much higher. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M12), thus causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance (R _M11 ) of an NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) obtains a higher voltage level at the node A. The higher voltage level of the node A is again passed through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level, the node The lower voltage level of B is again passed through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, and thus cycles The node A can be charged to the power supply voltage (V _DD ) to complete the logic 1 write operation.

It should be noted here that the first low voltage node (VL1) originally stores logic 0 at node A, and has a gate source voltage equal to the sixth NMOS transistor (M23) while logic 1 is being written. The voltage level of V _{GS (M23)} , after writing logic 1, will have the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (M13) At the threshold voltage, the third NMOS transistor (M13) is turned from OFF to ON; at this time, since the bit line (BL) is High (the power supply voltage V _DD ), and because of the A PMOS transistor (P11) is still ON, so the voltage at node A is maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line control signal WLC is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (M13) At the threshold voltage, the third NMOS transistor (M13) is turned from OFF to ON. At this time, since the bit line (BL) is Low (ground voltage), the node A and the node are The first low voltage node (VL1) is discharged to complete the logic 0 write operation until the end of the write cycle.

In the preferred embodiment of the present invention shown in FIG. 6, the HSPICE transient analysis simulation result during the write operation, as shown in FIG. 7, is simulated using the TSMC 90 nm CMOS process parameters, from which the simulation result is obtained. It can be confirmed that the 5T static random access memory proposed by the present invention can effectively improve the voltage level of the first low voltage node (VL1) during writing to effectively avoid It is quite difficult to know that it is difficult to write logic 1 in a static random access memory cell with a single bit line.

(II) Read mode (read mode)

The read control signal (RC), the write control signal (WC), and the standby mode control signal (S) are both logic low levels before the start of the read operation, so that the third PMOS transistor (P13) is turned on. And causing the tenth NMOS transistor (M27) to be turned off, then the node C is at a logic high level, and the node C of the logic high level turns on the ninth NMOS transistor (M26), and causes the first low voltage node ( VL1) is at ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned "ON".

The preferred embodiment of the present invention shown in FIG. 6 is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the reading operation, the reading is performed. The control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is grounded. The accelerated read voltage (RGND) is low, and the accelerated read voltage (RGND), which is lower than the ground voltage, can effectively increase the read speed.

In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but since the eighth NMOS transistor is at this time (M25) is turned off, so that the first low voltage node (VL1) is grounded via the turned-on ninth NMOS transistor (M26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit. (D1) The delay time provided is adjusted. Furthermore, regardless of the first phase of the read operation or the second phase, the ninth NMOS transistor (M26) is in an on state (since the gate of the ninth NMOS transistor (M26) is at a power supply voltage The level of V _DD ). Figure 8 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during reading.

Next, how to set the accelerated read voltage (RGND) and how to reduce the half-selected cell interference during reading according to the preferred embodiment of the present invention in FIG. 8 is illustrated by the two read states of the SRAM.

(1) Read logic 1 (node A stores logic 1):

Before the reading operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), and the node A and the node B are respectively the power supply voltage (V _DD ) and the ground voltage, and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading, since the word line control signal (WLC) is the threshold voltage of the twelfth NMOS transistor (M51) (ie, V _DD -V _TN51 ), the third NMOS is charged. The crystal (M13) is turned on (ON), whereby the bit line (BL) can be effectively maintained for the power supply voltage until the end of the read cycle and the operation of reading the logic 1 is successfully completed. It is worth noting here that since the first low voltage node (VL1) is the accelerated read voltage (RGND) at this time, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, it is necessary to The accelerated read voltage (RGND) is set lower than the threshold voltage (V _TM11 ) of the first NMOS transistor (M11), that is, |RGND|<V _TM11 (4) where |RGND| and V _TM11 respectively indicate Accelerating the absolute value of the read voltage and the threshold voltage of the first NMOS transistor (M11).

(2) Read logic 0 (node A stores logic 0):

Before the reading operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), and the node A and the node B are respectively grounded voltage and The power supply voltage (V _DD ), and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). Since the first NMOS transistor (M11) is ON, when the reading operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage is applied to the twelfth NMOS). The threshold voltage of the transistor M51 is V _DD -V _TN51 ). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. The initial instantaneous voltage (V _AR ) of the reading of node A must satisfy equation (5): V _AR = V _DD × (R _M11 + (R _M24 + R _M25 ) ∥ R _M26 ) / (R _M13 + R _M11 + ( R _M24 +R _M25 )∥R _M26 )+RGND×(R _M11 +R _M13 )∥R _M26 /(R _M24 +R _M25 +(R _M11 +R _M13 )∥R _M26 )×R _M13 /(R _M11 + R _M13 ) < V _TM12 (5) where V _AR represents the initial instantaneous voltage when node A reads logic 0, and R _M11 , R _{M13 ,} R _{M24 ,} R _M25 and R _M26 represent the first NMOS transistor (M11, respectively) The on-resistance of the third NMOS transistor (M13), the seventh NMOS transistor (M24), the eighth NMOS transistor (M25), and the ninth NMOS transistor (M26), and V _DD , RGND The power supply voltage (V _DD ), the accelerated read voltage (RGND), and the threshold voltage of the second NMOS transistor (M12) are respectively indicated by V _TM12 . It is worth noting here that the accelerated read voltage (RGND) is designed to be lower than the ground voltage and the absolute value of the accelerated read voltage is designed to be smaller than the threshold voltage of the first NMOS transistor (M11). Furthermore, the word line control signal (WLC) of the present invention during reading is set such that the power supply voltage is _{biased against} the threshold voltage (V _DD -V _TM51 ) of the eleventh NMOS transistor (M51). On the one hand, it is possible to effectively reduce the half-selected cell interference at the time of reading, and on the other hand, it is easy to satisfy the equation (5) by increasing the on-resistance (R _M13 ) of the third NMOS transistor (M13).

(III) Standby mode

First, how the standby start circuit (4) of Fig. 5 causes the 單埠SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: (1) the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fifth PMOS transistor (P41) to be turned off (OFF), and causes the eleventh NMOS transistor (M41) to be turned on (ON) (2) After entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fifth PMOS transistor (P41) ON (ON), but in the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from logic High to logic Low, to the eleventh NMOS transistor (M41) The gate voltage is sufficient to turn off the eleventh NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2), the eleventh NMOS transistor ( M41) is still turned on (ON), so the first low voltage node (VL1) can be quickly charged to reach the sixth NMOS transistor (M2) 3) The voltage level of the threshold voltage (V _TM23 ), that is, the 單_埠 SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the eleventh NMOS transistor (M41) is turned off and the supply current is stopped.

Referring to FIG. 5, in the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (M21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (M22) is turned on (ON), and the fifth NMOS transistor (M22) is used as an equalizer, so that the fifth NMOS transistor (M22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V _TM23 ). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during standby.

Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 9, FIG. 9 depicts a leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. I ₂ , I ₃ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage node (VL2) due to the standby mode The voltage level is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the voltage level of the node A is the logic Low and is maintained at the voltage level of the V _TM23 ) And the output of the second inverter (ie, node B) is a logic high (power supply voltage V _DD ). Referring to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9, the comparison between the static random access memory of the present invention and the 6T SRAM of FIG. 1b in terms of leakage current is first described. Leakage current I _{1 of the} third NMOS transistor (M13), since the voltage level of the node A is maintained at the voltage level of the V _{TM 23} in the standby mode, and the word line (WL) is assumed to be in the standby mode. The ground voltage is set, and the bit line (BL) is set to the power supply voltage (V _DD ) in the standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (M13) of the present invention is set. Negative value, in contrast to the standby mode, the gate-source voltage (V _GS ) of the prior art NMOS transistor (M3) of Fig. 1b is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect. Or, as shown in the results of Figures 3(A) and 3(B) of the US Pat. No. 6,865,119, issued March 8, 2005, it is known that for an NMOS transistor, the sub-critical current of the gate-source voltage is -0.1 volt is approximately the gate. The source voltage is 1% of the subcritical current at 0 volts, and thus is caused by the GIDL effect and flows through the present invention. The leakage current I _{1 of} the third NMOS transistor (M13) is much smaller than that of the prior art NMOS transistor (M3) of FIG. 1b; further, the threshold voltage of the third NMOS transistor (M13) of the present invention ( V _DS ) _deducts the voltage level of the V _TM23 for the power supply voltage (V _DD ), and the source voltage of the NMOS transistor (M3) of the conventional 1b FIG. 6T SRAM is in the standby mode. (V _DS ) is equal to the power supply voltage (V _DD ), according to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor flowing through the present invention due to the DIBL effect (M13) the drain current I ₁ is also smaller than the prior art of FIG. 1b NMOS transistor (M3) are; As a result, the third NMOS transistor (M13) of the present invention to flow through the drain current I ₁ is much smaller than the previous section in FIG. 1b The NMOS transistor (M3) of the art.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the _VTM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V) _DD ) deducting the voltage level of the V _TM23 , and in the standby mode, the source drain voltage (V _SD ) of the prior art PMOS transistor (P1) of FIG. 1b is equal to the power supply voltage (V _DD ), according to The DIBL effect, therefore, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of Figure 1b.

Finally, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the _VTM23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V _TM23 , and the voltage level of the node B is equal to the power supply voltage (V _DD ) and the base of the second NMOS transistor (M12) is the ground voltage, so The base-source voltage (V _BS ) of the second NMOS transistor (M12) of the invention is a negative value, and the 汲 source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V) _DD ) deducting the voltage level of the V _TM23 , in contrast to the standby mode, the base-source voltage (V _BS ) of the prior art NMOS transistor (M2) of FIG. 1b is equal to 0, and the NMOS transistor (M2) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than the first 1b is a prior art NMOS transistor (M2). It can be seen from the above analysis that the 單埠 static random access memory proposed by the present invention has a lower leakage current than the prior art of Fig. 1b.

(IV) hold mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to a ground voltage, the working principle is the same as that of the conventional 5T SRAM cell with a single bit line in FIG. This is not repeated here.

【Effects of invention】

The 5T static random access memory proposed by the present invention has the following effects: (1) high design freedom: since the present invention reads the logic 0, the storage node (A) is pulled down to be lower than the second NMOS transistor. The threshold voltage (V _TM12 ) of (M12) has two mechanisms, one is by the word line voltage level conversion circuit (5) to apply the access transistor to the selected unit cell (ie, the third NMOS transistor) The word line voltage of M13) is _pulled down to the power supply voltage (ie, V _DD -V _TM51 ), and the other is to pull the storage node (A) by the accelerated read voltage (RGND) below the ground voltage, thus having High design freedom; (2) Effectively reduce half-selected cell interference during reading: The present invention can be applied to selected crystals by a word line voltage level conversion circuit (5) during a read operation The word line voltage of the cell access transistor (ie, the third NMOS transistor N13) is _pulled down below the power supply voltage (ie, V _DD -V _TN51 ), which on the one hand reduces the third of the semi-selected cells Read disturb of the NMOS transistor (M13), on the other hand, by reducing the accelerated read voltage required to satisfy equation (5) ( RGND) to reduce the read interference of the first NMOS transistor (N11) in the half-selected cell, thus having the effect of effectively reducing the half-selected cell interference during reading; (3) high read speed and avoiding unnecessary Power consumption: The present invention employs a two-stage read operation, which is effective in the first phase of the read operation by setting the first low voltage node (VL1) to an accelerated read voltage (RGND) that is lower than the ground voltage. Increasing the reading speed, and in the second phase of the reading operation, the first low voltage node (VL1) is set back to the ground voltage to reduce unnecessary power consumption; (4) quickly enter standby mode: due to the present invention There is a standby start circuit (4) to prompt the SRAM to quickly enter the standby mode, and thereby seek to improve the standby performance of the 單埠SRAM; (5) avoid the difficulty of writing the logic 1: the present invention can be borrowed during the write operation It is quite difficult to increase the voltage level of the first low voltage node (VL1) to effectively avoid the existence of writing logic 1 in the SRAM with a single bit line; (6) low standby current: due to the present invention In standby mode, it can be turned on a fifth NMOS transistor (M22) such that a voltage level of the first low voltage node (VL1) is equal to a voltage level of the second low voltage node (VL2), and the voltage levels are equal to the The sixth NMOS transistor (M23) threshold voltage level, so the present invention also has the effect of low standby current; (7) low transistor number: for 1024 columns of 1024 rows of SRAM array, the traditional 1b The 6T static random access memory array requires a total of 1024×1024×6=6,291,456 transistors, and the static random access memory proposed by the present invention only needs at least 1024×1024×5+1024×24+6=5,267,462 A transistor that reduces the number of transistors by 16.3%.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

5‧‧‧Word line voltage level conversion circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

BL‧‧‧ bit line

WLC‧‧‧ word line control signal

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

P21‧‧‧ Third PMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

WC‧‧‧ write control signal

/WC‧‧‧Inverted write control signal

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧4th NMOS transistor

P‧‧‧Precharge signal

M41‧‧11 eleventh NMOS transistor

P41‧‧‧ Fifth PMOS transistor

D2‧‧‧second delay circuit

V _DD ‧‧‧Power supply voltage

WL‧‧‧ character line

R‧‧‧Read signal

/W‧‧‧Inverted write signal

/RW‧‧‧Inverted read/write control signal

P51‧‧‧6th PMOS transistor

M51‧‧‧12th NMOS transistor

M52‧‧‧Thirteenth NMOS transistor

C‧‧‧ node

Claims (10)

A 5T static random access memory comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory cells The cell comprises a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory cells Setting a pre-charging circuit (3); a standby starting circuit (4), the standby starting circuit (4) prompting the static random access memory to quickly enter the standby mode to effectively improve the 5T static random access memory The standby performance of the body; and a plurality of word line voltage level conversion circuits (5), each column memory cell is provided with a word line voltage level conversion circuit (5); wherein each memory cell (1) Further comprising: a first inverter consisting of a first PMOS transistor (P11) and a first NMOS transistor (M11) connected to a power supply voltage (V) _DD ) is between a first low voltage node (VL1); a second inverter is connected by a The second PMOS transistor (P12) is composed of a second NMOS transistor (M12) connected between the power supply voltage (V _DD ) and a second low voltage node (VL2) a storage node (A) formed by the output of the first inverter; an inverting storage node (B) formed by the output of the second inverter; a third NMOS a crystal (M13) connected between the storage node (A) and a bit line (BL), and the gate is connected to a word line control signal (WLC); wherein the first inverter and the The second inverter is connected in an alternating manner, that is, the output end of the first inverter (ie, the storage node A) is connected to the input end of the second inverter, and the second inverter is The output terminal (ie, the inverting storage node B) is connected to the input end of the first inverter; and each control circuit (2) further comprises: a fourth NMOS transistor (M21), a fifth NMOS device Crystal (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), and a tenth NMOS device Crystal (M27), a third PMOS transistor (P 21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a An inverted write control signal (/WC), a standby mode control signal (S), and an inverted standby mode control signal (/S); wherein the source and gate of the fourth NMOS transistor (M21) The drain is connected to a ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2), and the source, gate and drain of the fifth NMOS transistor (M22) Connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low voltage node (VL1); the source of the sixth NMOS transistor (M23) is connected to the ground voltage, The gate is connected to the drain and connected to the first low voltage node (VL1); the source, the gate and the drain of the seventh NMOS transistor (M24) are respectively connected to the eighth NMOS transistor a drain of (M25), the read control signal (RC) and the first low voltage node (VL1); a source, a gate and a drain of the eighth NMOS transistor (M25) are respectively connected to the acceleration Read voltage (R GND), an output of the first delay circuit (D1) and a source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to an output of the third inverter (INV) Between the gates of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the first delay circuit (D1) The input, the gate, the gate and the drain of the ninth NMOS transistor (M26) are respectively connected to a ground voltage, a drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1) The source, gate and drain of the tenth NMOS transistor (M27) are respectively connected to the write control signal (WC), the standby mode control signal (S) and the ninth NMOS transistor (M26) a gate of the third PMOS transistor (P21), the gate and the drain are respectively connected to the inverted write control signal (/WC), the standby mode control signal (S) and the first The drain of the ten NMOS transistor (M27); note here that the drain of the third PMOS transistor (P3), the drain of the tenth NMOS transistor (M27), and the ninth NMOS transistor (M26) the gates are connected together Forming a node (C), when the standby mode control signal (S) is at a logic low level, the voltage level of the node (C) is the voltage level of the inverted write control signal (/WC), and When the standby mode control signal (S) is at a logic high level, the voltage level of the node (C) is the voltage level of the write control signal (WC), thereby effectively preventing the writing logic 1 from being caused by The standby mode control signal (S) is expected to be a logic high level and thus causes a problem of being unwritable; wherein the read control signal (RC) during the non-read mode is set to the accelerated read voltage (RGND) level to prevent leakage current of the seventh NMOS transistor (M24) during the non-read mode; further, the standby start circuit (4) is designed to enter one of the initial modes of the standby mode And rapidly charging the parasitic capacitance at the first low voltage node (VL1) to a voltage level of a threshold voltage ( _VTM23 ) of the sixth NMOS transistor (M23); further, each word line voltage level conversion The circuit (5) further comprises: a sixth PMOS transistor (P51), a twelfth NMOS transistor (M51), and a tenth An NMOS transistor (M52), a read signal (R), an inverted write signal (/W), an inverted read/write control signal (/RW), and the word line control signal (WLC); The source, the gate and the drain of the sixth PMOS transistor (P51) are respectively connected to a word line (WL), the inverted write signal (/W) and the word line control signal (WLC) The source, gate and drain of the twelfth NMOS transistor (M51) are respectively connected to the word line control signal (WLC), the read signal (R) and the word line (WL); The source, gate and drain of the thirteenth NMOS transistor (M52) are respectively connected to the word line control signal (WLC), the inverted read/write control signal (/RW) and the word line. (WL); it is worth noting here that each word line voltage level conversion circuit (5) supplies the word line (WL) of the selected unit cell from the power supply voltage (V _DD ) during the read operation. Transforming the power supply voltage (V _DD ) to the threshold voltage (V _TN51 ) of the twelfth NMOS transistor (M51) (ie, V _DD -V _TN51 ) and supplying the word line control signal (WLC) ); while in the write operation, the word line (WL) of the selected unit cell will be selected The supply voltage (V _DD) supplied to the word line control signal (WLC). 5T static random access memory according to claim 1, wherein each record The first NMOS transistor (M11) in the memory cell (1) has the same channel width to length ratio as the second NMOS transistor (M12), and the first PMOS transistor (P11) and the second The PMOS transistor (P12) also has the same channel width to length ratio. The 5T static random access memory according to claim 2, wherein the accelerated read voltage (RGND) in each control circuit (2) is set lower than each memory cell. The threshold voltage (V _TM11 ) of the first NMOS transistor (M11) in (1). The 5T static random access memory according to claim 3, wherein the read signal (R) and the inverted write signal in each word line voltage level conversion circuit (5) (/W) is a read/write control pin from the static random access memory, and the read operation is indicated when the read/write control pin is logic high (that is, the read signal R is a logic high level) And the read/write control pin is a logic low-level on-time indicating write operation (ie, the inverted write signal /W is a logic low level), and the inverted read/write control signal (/RW) is the read/write control Inverted signal of the pin. 5. The 5T static random access memory according to claim 4, wherein the write control signal (WC) in each control circuit (2) is a write signal (W) and the character The result of the AND gate operation of the line (WL) signal, that is, the write control signal (WC) side only when the write signal (W) and the word line (WL) signal are both at a logic high level. The logic high level, wherein the inverted write signal (/W) is the inverted signal of the write signal (W). 5. The 5T static random access memory according to claim 5, wherein the read control signal (RC) in each control circuit (2) is the read signal (R) and the character. The result of the AND gate operation of the line (WL) signal, that is, the read control signal (RC) side only when the read signal (R) and the word line (WL) signal are both at a logic high level. It is logically high. The 5T static random access memory according to claim 6, wherein each precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P); The source, the gate and the drain of the fourth PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), so that During a precharge period, the precharge signal (P) is logic low to precharge the bit line (BL) to the level of the power supply voltage (V _DD ). The 5T static random access memory according to claim 7, wherein the standby start circuit (4) is a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fifth PMOS transistor (P41) are respectively connected to the power supply a voltage (V _DD ), the inverted standby mode control signal (/S) and a drain of the eleventh NMOS transistor (M41); a source, a gate and a gate of the eleventh NMOS transistor (M41) The poles are respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fifth PMOS transistor (P41); the input connection of the second delay circuit (D2) Up to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the eleventh NMOS transistor (M41). The 5T static random access memory according to claim 8, wherein the initial period of the standby start circuit (4) entering the standby mode is equal to the inverted standby mode control signal (/S) being logic high The quasi-transition is a logic low level, until the gate voltage of the eleventh NMOS transistor (M41) is sufficient to turn off the eleventh NMOS transistor (M41), and the second delay circuit (D2) ) One of the delay times provided to adjust. The 5T static random access memory according to claim 9, wherein the read operation of each memory cell (1) can be subdivided into two stages, one of the reading operations. The first stage is to increase the read speed by setting the first low voltage node (VL1) to the accelerated read voltage (RGND) lower than the ground voltage, and in the second stage of the read operation Then, by setting the first low voltage node (VL1) back to the ground voltage, so as to reduce unnecessary power consumption, the time between the second phase of the read operation and the first phase is equal to the read control signal. (RC) from the logic low level to the logic high level, until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), which can be performed by the third The falling delay time of the inverter (INV) is adjusted with another delay time provided by the first delay circuit (D1).