CN111326570A - Novel bonded silicon wafer and preparation method thereof - Google Patents
Novel bonded silicon wafer and preparation method thereof Download PDFInfo
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- CN111326570A CN111326570A CN202010219325.4A CN202010219325A CN111326570A CN 111326570 A CN111326570 A CN 111326570A CN 202010219325 A CN202010219325 A CN 202010219325A CN 111326570 A CN111326570 A CN 111326570A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 38
- 239000010703 silicon Substances 0.000 title claims abstract description 38
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 38
- 230000007704 transition Effects 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 239000013078 crystal Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 33
- 238000005498 polishing Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000008093 supporting effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention mainly aims to provide a novel bonded silicon wafer and a preparation method thereof, and the method adopts the bonding of a substrate silicon wafer and a shallow junction diffusion silicon wafer to replace an epitaxial wafer or a deep junction diffusion wafer with high cost, thereby reducing the cost. The manufacturing process adopts the steps of firstly diffusing the active region silicon wafer, then directly bonding the substrate silicon wafer as a support, and reducing the high-low concentration transition region, wherein the silicon wafer is formed by directly bonding two parts of a high-concentration substrate wafer 10 and a diffusion silicon wafer 30, the thickness of the bonding region 20 is less than 2nm, and the diffusion wafer 30 is divided into a high-concentration diffusion region 31, a transition region 32 and a low-concentration active region 33. The silicon chip can be widely used for vertically conducted semiconductor devices, reduces the cost and ensures low forward voltage drop.
Description
Technical Field
The invention belongs to the technical field of silicon wafers and preparation thereof, and particularly relates to a silicon wafer with multiple layers of concentrations formed in a bonding mode without epitaxy and with low cost and a preparation method thereof.
Background
The substrate growth methods used above generally have three modes: 1. and (4) epitaxial growth. The method is simple and the transition area between the growing epitaxial layer and the substrate concentration is narrow, so that the on-resistance is small. The disadvantage is the high growth cost, especially for thick epitaxy, which increases with increasing thickness; the manufactured device is not as good as a single chip in the aspects of reverse voltage withstand voltage and reverse leakage; the quality of the substrate used is demanding. 2. Triple diffusion growth mode. High-concentration impurities are diffused on the two sides of the single crystal wafer, for example, phosphorus is diffused to form N +/phosphorus is diffused to form a P + layer, then the P + layer is diffused at high temperature for a long time, in order to achieve the thickness of the supporting effect, the junction depth generally reaches more than 150 microns, the high temperature is needed to be more than 1280 ℃ for one week, and then the single side is thinned and polished. The advantages are low manufacturing cost and good quality of single crystal layer; the disadvantage is that the formed transition region is wide, usually more than 50um, resulting in large on-resistance; the diffusion period is long; the quality requirement of the single crystal is high. 3. Direct silicon wafer bonding mode: the two silicon chips are directly bonded to form an N-/N + or P-/P + type. The method has the advantages of low cost and the disadvantage that when the upper silicon wafer is lower than 10um, the upper silicon wafer is easy to fall off or fragment during thinning and polishing.
Disclosure of Invention
The invention mainly aims to provide a novel bonded silicon wafer and a preparation method thereof, and the method adopts the bonding of a substrate silicon wafer and a shallow junction diffusion silicon wafer to replace an epitaxial wafer or a deep junction diffusion wafer with high cost, reduces the cost, is easy to thin and the like. The manufacturing process adopts the steps of firstly diffusing the silicon wafer in the active area, and then directly bonding the substrate silicon wafer as a support, so as to reduce the transition area of high and low concentration, as shown in the structure of figure 2, the silicon wafer is formed by directly bonding two parts of a high-concentration substrate wafer 10 and a diffusion silicon wafer 30, the thickness of the bonding area 20 is less than 2nm, and the diffusion wafer 30 is divided into a high-concentration diffusion area 31, a transition area 32 and a low-concentration active area 33.
The substrate slice is a high-concentration layer to reduce the on-resistance; the diffusion silicon wafer is divided into a high-concentration diffusion area, a transition area and a low-concentration active area. The width of the transition region is 1-20um., the thickness of the oxide layer in the bonding region is less than 2nm, and the substrate can be semiconductor-grade purity single crystal wafer or solar photovoltaic-grade purity single crystal wafer.
The preparation method of the bonded silicon wafer comprises the following steps: the upper silicon wafer is diffused to form a high concentration region and a transition region, then the diffusion and the polished surface of the substrate wafer are oppositely and directly bonded, and then the diffusion is thinned and polished to form a low concentration region according to the requirements of devices.
The width of the transition layer formed by diffusion is closely related to the depth of the high concentration layer, and the deeper the junction, the wider the transition region. When it is desired to reduce the width of the transition region, the junction depth of the high concentration layer is reduced as much as possible. As shown in fig. 3 for transition zone comparison. 1 is a substrate grown in an epitaxial mode, and a transition region is narrowest; 2, the bonding diffusion silicon wafer of the invention has a transition slightly wider than that of an epitaxial wafer, but can be controlled in a proper range; 3 is a deep diffusion sheet with wide transition zone.
The substrate of the invention is used as a support by directly bonding a high-concentration substrate slice, the thickness of the substrate processed by a subsequent chip is usually more than 450um, and the thickness of the substrate slice of the invention is more than 450um, thus avoiding fragments. The substrate slice does not participate in the functions of electric field distribution of the active region and the like, so that a low-purity single chip with lower cost, such as a 99.9999% purity solar photovoltaic grade chip, can be used. In the diffusion sheet part, the diffusion junction depth of the high-concentration diffusion region can be reduced to several microns, so that the transition region can be as low as 1 um. According to the requirements of different devices, such as a high-back-pressure device, a low-resistance region requires high thickness, such as a 600V device, the thickness is more than 50um, a transition region is desirably wide, a field termination punch-through structure is achieved, the voltage resistance is improved, meanwhile, the on-resistance is reduced, the junction depth of a high-concentration region is increased, the width of the transition region is increased, but the width is not more than 20um., so that the junction depth of a diffusion region is not more than 50um, and the transition region is ensured to be lower than 20um.
The invention discloses a preparation method of a novel bonded silicon wafer, which comprises the following steps: n +/P + type lining plate-single side polishing-N-/P-type single wafer-single side polishing-diffusion of high concentration N +/P + layer-two polished surface attaching-low temperature 100 ℃ baking for more than 2 hours-high temperature 1000 ℃ bonding for 2 hours-diffusion sheet thinning-polishing
The bonding of the bonded silicon wafer adopts two steps of low-temperature treatment and high-temperature bonding, the polished surface is free from an oxide layer, the thickness of the oxide layer is less than 2nm, and a current carrier directly passes through the oxide layer in a tunnel penetrating mode without blocking.
Compared with the substrate manufactured by an epitaxial method, the bonded substrate sheet of the scheme has the advantages that the material cost is reduced by more than 50%, and the forward voltage drop and the reverse leakage current are also reduced.
Drawings
FIG. 1 is a schematic diagram of a standard substrate. 10: a high-concentration substrate sheet; 21: a transition layer; 22: low concentration layer
Fig. 2 is a schematic view of a bonded diffusion substrate of the present invention. 10: a high-concentration substrate sheet; 20: a bonding region; 31: a high concentration diffusion layer; 32: a transition zone; 33: low concentration single crystal wafer.
FIG. 3 is a schematic diagram comparing transition zones. 1 is a substrate grown in an epitaxial mode, and a transition region is narrowest; 2 is the bonding diffusion silicon chip of the invention, the transition is slightly wider than the epitaxial wafer, but can be controlled in a more appropriate range; 3 is a deep diffusion sheet with wide transition zone.
FIG. 4 is a schematic illustration of the I-V curve of the example.
Detailed Description
The present invention is further illustrated by the following specific examples, which are not intended to limit the scope of the invention.
Examples
Taking an N-type single crystal wafer (with the resistivity of 2 omega cm and the thickness of 300um) with a single polished surface, introducing a POCL3 diffusion source for 30 minutes at 1100 ℃, taking an N + type single crystal wafer (with the resistivity of 5E-3 omega cm and the thickness of 450um) with the single polished surface, carrying out RCA cleaning, rinsing DHF, drying, attaching two polished surfaces, drying for 2 hours at 200 ℃, then placing the wafer in a diffusion furnace at 1100 ℃ for 2 hours, and thinning and polishing until the thickness of an N-region is 8um. to obtain a diffusion region of 6um and a transition region width of nearly 2 um.
The Schottky diode is manufactured by using the substrate, a general plane Schottky diode manufacturing method is adopted, as shown in figure 4, the obtained diode has the advantages that the reverse cut-off (breakdown) voltage is 135V, the reverse leakage current is 1uA, and the forward voltage drop is 0.75V.
Of course, those skilled in the art should realize that the above embodiments are illustrative only and not limiting of the present invention, and that changes and modifications to the above described embodiments are intended to fall within the scope of the appended claims, as long as they fall within the true spirit and scope of the present invention.
Claims (5)
1. A novel bonded silicon wafer structurally comprises: the silicon chip is formed by directly bonding a high-concentration substrate chip and a diffusion silicon chip.
2. The novel bonded silicon wafer according to claim 1, wherein the substrate sheet is a high concentration layer to reduce on-resistance; the diffusion silicon wafer is divided into a high-concentration diffusion area, a transition area and a low-concentration active area. The width of the transition region is 1-20um., the thickness of the oxide layer in the bonding region is less than 2nm, and the substrate can be semiconductor-grade purity single crystal wafer or solar photovoltaic-grade purity single crystal wafer.
3. A preparation method of a novel bonded silicon wafer comprises the following steps: the upper silicon wafer is diffused to form a high concentration region and a transition region, then the diffusion and the polished surface of the substrate wafer are oppositely and directly bonded, and then the diffusion is thinned and polished to form a low concentration region according to the requirements of devices.
4. The bonded silicon wafer manufacturing method according to claim 3, wherein the high temperature forms a high concentration diffusion region having a width of not more than 50 μm to ensure that the transition region is less than 20 μm.
5. The bonded silicon wafer bonding of claim 3 wherein the low temperature process and the high temperature bonding are performed in two steps, the polished surface is free of an oxide layer, and the oxide layer has a thickness of less than 2nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010219325.4A CN111326570A (en) | 2020-05-12 | 2020-05-12 | Novel bonded silicon wafer and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010219325.4A CN111326570A (en) | 2020-05-12 | 2020-05-12 | Novel bonded silicon wafer and preparation method thereof |
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| Publication Number | Publication Date |
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| CN111326570A true CN111326570A (en) | 2020-06-23 |
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| CN202010219325.4A Pending CN111326570A (en) | 2020-05-12 | 2020-05-12 | Novel bonded silicon wafer and preparation method thereof |
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