GB2051475A - High frequency high power P-I-N substrate semiconductor device and method for making same - Google Patents

High frequency high power P-I-N substrate semiconductor device and method for making same Download PDF

Info

Publication number
GB2051475A
GB2051475A GB8012595A GB8012595A GB2051475A GB 2051475 A GB2051475 A GB 2051475A GB 8012595 A GB8012595 A GB 8012595A GB 8012595 A GB8012595 A GB 8012595A GB 2051475 A GB2051475 A GB 2051475A
Authority
GB
United Kingdom
Prior art keywords
substrate
intrinsic
region
semiconductor device
eutectic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB8012595A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northrop Grumman Space and Mission Systems Corp
Original Assignee
TRW Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TRW Inc filed Critical TRW Inc
Publication of GB2051475A publication Critical patent/GB2051475A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01038—Strontium [Sr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01063—Europium [Eu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Abstract

A high-frequency, high power bipolar transistor formed in a P-I-N substrate and permitting horizontal isolation from other active devices by shallow V-grooves 62 or diffused regions, comprises a collector region 52 adjoining an intrinsic semiconductor region ???, and base and emitter regions 58, 60 in an epitaxial layer 54 the intrinsic region being connected to a support pad by an eutectic bonding process utilizing a doped eutectic forming material whereby dopant atoms diffuse into the intrinsic region thereby forming a contact region for the transistor simultaneously with the formation of the eutectic bond. Typically, the support pad is of Cu, and boron from boron doped gold layer diffuses into the intrinsic region to form a P + contact region during the eutectic bonding of the pad. <IMAGE>

Description

SPECIFICATION High frequency high power P-I-N substrate semiconductor device and method for making same BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to the construction and fabrication of P-I-N isolated substrates to allow construction of isolated collector RF power transistors. In particular a method of construction is provided which (a) eliminates the need for deep V-grooves to provide horizontal isolation and (b) produces improved thermal conductivity and vertical capacitive isolation.
2. Prior Art RF power transistors have typically been constructed on P-I-N isolated substrates.
These substrates are formed by beginning with a < 1 00 > crystal oriented silicon substrate doped to exhibit P + characteristics. An intrinsic epitaxial layer is then deposited on the substrate approximately 1 5y thick having a resistivity of greater than 400 ohm-cm. An epitaxial layer of N + characteristics is then deposited on top of that and lastly an N epitaxial layer is added. The requirement of adding the three epitaxial layers produces quality control problems. For proper operation of the device the profile and thickness of these layers must be carefully controlled. Accurate control is difficult to achieve. To horizontally isolate the active devices which will be formed in the upper most epitaxial layer, deep V-grooves are used. These deep Vgrooves must extend through the three epitaxial layers to the intrinsic layer.Once the deep V-grooves are formed they must be back-filled with a polycrystalline and polished back to the surface of the upper epitaxial layer. This polishing removes the excess polycrystalline material and must be carefully controlled to provide a very flat surface which is parallel to the opposite surface of the substrate. The use of such deep V-grooves with < 100 > silicon wafers tends to cause the wafer to break easily.
This substrate is directly attached to the package base and has a difficult to control vertical P-I-N junction thickness which at higher frequencies results in undesirable capacitive coupling between the collector and the substrate region of active devices. In addition, the use of a substrate which is heavily doped and exhibiting P + characteristics results in poor thermal conductivity to the package base thus severely limiting the power capacity of the device.
It is thus an object of the present invention to provide a method for fabricating a P-I-N isolated substrate for use in construction of RF power transistors which will not require the difficult to control deposition of multiple epitaxial layers and the concomitant requirement of deep V-grooves to provide horizontal isolation.
It is a further object of the invention to provide a method for fabricating a very thick P-I-N isolated substrate for use in construction of RF power transistors which exhibits improved thermal transfer characteristics.
Another object is to provide a method for attaching such an RF power transistor die to a package base which does not# produce a great number of metal interfaces thereby increasing the thermal resistance to the package base.
SUMMARY OF THE INVENTION An area of N + semiconductive material is formed such as by diffusion into the surface of a high resistivity (greater than 5000 ohmcm) P-type (sir) intrinsic semiconductor substrate having a < 100 > crystalline structure.
Over this surface of the substrate there is epitaxially deposited a relatively thin layer (4-7y) of N - semiconductor material. The active devices are formed in the exposed surface of the N - semiconductor material and horizontally isolated from one another by shallow, rather than deep, V-grooves. For effective horizontal isolation the shallow Vgrooves need only be slightly deeper than the 4-71l N - epitaxial layer.
The P portion of this P-I-N isolated substrate is formed during the die-attach procedure by a method which minimizes the number of metal interfaces between the die and the base pad and forms the P portion by diffusion of dopant material from the eutectic solder into the base portion of the substrate.
By controlling the amount of dopant in the solder the P + layer can be maintained very narrow thus producing a highly conductive thermal path to the base pad. The minimal number of metal interfaces greatly reduces the thermal resistance to the base pad (ground).
The intrinsic portion of the substrate depletes at low collector voltage, thus controlling the collector isolation and capacitive coupling to the base pad (ground). The higher the frequency, the lower the collector to ground capacitance is required to be.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross section showing the typical configuration of RF power transistors of the prior art as mounted on its copper package flange; Figure 2 is a cross section showing the configuration of the RF power transistors of the present invention, prior to mounting on its copper package; and Figure 3 is a cross section of the RF power transistor of the present invention as mounted on the copper flange.
DETAILED DESCRIPTION OF THE INVEN TION Understanding of the present invention is facilitated if one first has a basis with which to compare the invention. Toward this end a description of the configuration and method of fabrication of RF power transistors of the prior art is offered.
Isolated collector RF power transistors fabricated on P-I-N isolated substrates typically took on the configuration shown in Fig. 1. A substrate wafer 10 exhibiting P + semiconductor characteristics and having a < 100 > crystal orientation was provided. This substrate wafer was approximately 3.0 mils thick when the device was completed. To one side of this wafer there was epitaxially deposited a sr intrinsic layer 12 approximately 10 microns thick. Similarly, an N + epitaxial layer 14 was deposited to a thickness of approximately 10 microns followed by epitaxial deposition of an N~ epitaxial layer 1 6 about 7 microns thick.
A typical active device 18 (such as an RF power transistor) was then diffused in the N - epitaxial layer 16. The active device 18 comprised the emitter region 20, base region 22 and a collector comprised of the N + epitaxial layer which was accessed by means of a collector groove 24 which extended through the N - epitaxial layer 16 to contact the N + epitaxial layer 14 at 25.
In the above construction process each epitaxial deposition must be carefully monitored to ensure layers of uniform thickness, flatness, and parallel alignment with the plane of the substrate wafer 10.
Horizontal isolation of one active device 18 from adjacent active devices is accomplished by providing deep V-grooves 26 which extend through each epitaxial layer 16, 14 and 12 and slightly into the substrate wafer 10 as shown at point 28. The presence of such deep V-grooves 26 gives the substrate wafer 10 a tendency to break easily during handling. The above-described assembly is referred to as P-I-N isolated since the active device 18 is isolated from its mounting by the substrate wafer 10 (P-type material), the 7r intrinsic layer 12 and the N + epitaxial layer 14 (N-type material).
The mounting of the above-described assembly, as shown in Fig. 1, on its copper pad 32 typically proceeded according to a method called eutectic bonding. Generally a copper base pad 32 comprising the package was coated with gold 34 and subjected to sufficient heat to form an eutectic bond of the assembly to the copper base pad.
This method of fabrication and attachment has one particularly undesirable characteristic with respect to RF power transistors. The active device 18 is formed at high temperatures, this tends to cause the substrate wafer 10 dopant material (P + impurities) to diffuse and enlarge the P + region into the 7r intrinsic layer 12. This narrowing of the sr intrinsic layer 12 causes increased parasitic capacitance between the active device 18 and the copper base pad 32 thus degrading high frequency performance. In addition, the expansion of the P + region (substrate wafer 1 0) results in reduced thermal conductivity from the active device 18 to the copper base pad 32. Since at high frequencies a greater percentage of the energy of a signal goes to produce heat the high frequency performance is further degraded.
The RF power transistor of the present invention, and its method of fabrication can be illustrated with Fig. 2 in mind. The method of the present invention produces a P-I-N isolated RF power transistor just as does the method of the prior art, but for reasons soon to be explained the device of the present invention exhibits superior high frequency characteristics and greatly improved heat dissipation capabilities.
A high resistivity P-type (so) intrinsic wafer 50 is provided. This wafer 50 is typically about 3.5 mils thick after completion with a resistivity exceeding 5000 ohm-cm. The wafer is of < 100 > crystal orientation. Into the upper surface of the wafer 50 is diffused an N + diffused collector 52 having a resistivity less than 0.01 ohm-cm to a depth of approximately 10 microns. Over this same surface there is deposited an N - epitaxial layer 54 having a resistivity of approximately 0.8 to 1.0 ohm-cm and a thickness of 4 to 7 microns. An active device 56, comprising a base 58 and an emitter 60 may then be diffused into the N - epitaxial layer 54 directly above the N + diffused collector 52. A collector groove 62 is formed to access the collector 52 as at 64.
Because of the geometry of this device, horizontal isolation may be accomplished by shallow V-grooves 66 which need only be slightly deeper than the thickness of the N epitaxial layer 54 (4 to 7 microns) to encounter the intrinsic wafer 50 as at 68. Since the N N - epitaxial layer 54 is so shallow, horizontal isolation could alternatively be accomplished by a P-type diffusion 72 through the layer 54 to the wafer 50 as shown in Fig. 3.
In addition, electrical contact with the collector 52 could be accomplished by a N + type diffusion 70 through the layer 54 to the collector 52 as shown in Fig. 3.
As shown in Fig. 2 there has been formed an active device 56, an N-type region 52 and an intrinsic region (ir) 50. To complete the formation of the desired P-I-N substrate P + contact region must be formed in the bottom of the wafer substrate 50. One of the unique features of this invention is the formation of this P + contact region during the process of attaching the substrate wafer 50 to its copper package 80.
To facilitate mounting of a semiconductor assembly upon a copper package 80, the copper package is provided with a thin base plate 82 typically made of gold. To this base plate 82 may be applied a thin layer 84 of boron doped gold which acts as a eutectic solder. The wafer substrate 50, with the active device 56 already formed, is placed in physical contact with the layer 84 of boron doped gold and heated to the eutectic temper- ature. The P + impurities in the boron doped gold are thereby caused to diffuse slightly into the 7r intrinsic wafer substrate 50 forming a thin layer 86 of P + characteristic. Thus, the P portion of the P-I-N substrate is formed.
The temperature is lowered, the eutectic solidifies, and the assembly is thereby affixed to the copper base pad 82. The thickness of this P + contact region 86 may be controlled by controlling the degree to which the gold has been doped with the boron impurities. It is preferable for purposes of the present invention that the P + contact region 86 be kept to approximately 1000 angstroms in thickness with a resiStivity less than 0.01 ohm-cm.
As is evident from an examination of Fig. 3 this method of attaching the substrate wafer 50 to the base pad 82 produces a minimum of metal-to-metal interfaces. As a result the high frequency capacitive coupling between the base pad 82 and collector region 52 is greatly reduced. In addition, the use of heavily doped silicon regions (P + region 10 as in Fig. 1 vs. 86 as in Fig. 3) has been greatly reduced. This results in very low thermal resistance, thus permitting better thermal transfer from the active device 56 to the base pad 82. The active device 56 is thus able to operate at higher power levels without significant increase in temperature. Stated in other terms the active device 56 can operate at power levels approximately 30% above equivalent devices of the prior art without degrading performance.
In addition, because the N - epitaxial layer 54 is very thin (4-7y) horizontal isolation can be accomplished by a shallow V-groove whereas with prior art devices a deep Vgroove was required to pierce the epitaxial layers totaling approximately 27it. The use of shallow V-grooves reduces the likelihood that the substrate will break during handling. Alter- natively horizontal isolation may be accomplished by diffusion of a P - region such as 72 of Fig. 3. The collector contact can also be formed by diffusion such as the N + region 70.
Another benefit of the method of the present invention is that the P + contact region 86 is not subject to the high temperatures required to form the active device 56, since the P + contact region 86 is not even formed until the substrate attach step. Thus, the P + region 86 stays narrow and allows improved heat transfer to the base pad 82.
There has thus been described a method for constructing a uniquely structured P-l-.N isolated collector RF power transistor having an intrinsic substrate. RF power transistors fabricated according to the present invention exhibit improved capacitive isolation at high frequencies and improved heat transfer characteristics which allow increased power handling capability. The structure allows the use of shallow V-grooves or even diffusion techniques to accomplish horizontal isolation, as opposed to the deep V-grooves of the prior art which gave the substrate a tendency to break during handling.
While the present invention has been described with reference to the embodiments of Figs 2 and 3, it is obvious that one of ordinary skill in the art could make various changes in the method and structure without departing from the spirit and scope of the invention. For example, it is contemplated that to construct the RF power transistor one could begin with a back-to-back N +, N - structure. This would be thinned to about 1 mil thickness and a thick poly intrinsic handle could be deposited over the N + layer to form the intrinsic isolation region 50. This would result in the disadvantage of having to make a thick deposition on very thin starting material, but at least theoretically this procedure could be followed.
The method of the present invention can be used for both P-type and N-type intrinsic substrates. In the case of P-type intrinsic substrates the P-type contact region forms an ohmic contact, whereas for N-type intrinsic substrates the P-type region actually forms a junction. Thus, for the N-type substrate the dopant concentration must be higher than for the P-type substrate. For the N-type substrate the P-type region should be as thin as possible but it must be at least as thick as necessary to prevent it from ever allowing the Ptype contact region to become forward biased which would cause injection of carriers into the N-type region thereby destroying the electrical characteristics of the N-type region. The invention is thus not to be interpreted as limited to N-type intrinsic substrates.
The embodiments illustrated herein are not intended to limit the scope of the invention defined by the following claims.

Claims (10)

1. A semiconductor device for mounting upon the base pad of a package; said semiconductor device comprising an intrinsic substrate, a base region and an emitter region which are isolated from a collector region by an epitaxial layer; said collector region being in contact with said intrinsic substrate; said intrinsic substrate being joined to said base pad by an eutectic bonding process utilizing a doped eutectic forming material whereby dopant atoms diffuse slightly into the intrinsic substrate thereby forming the contact region of said semiconductive device simulta neously with the formation of the eutectic bond.
2. A semiconductor device according to Claim 1 wherein horizontal isolation of the active device is accomplished by V-grooves having a depth less than 1OIL.
3. A semiconductor device according to Claim 2 wherein the intrinsic semiconductor substrate is P-type silicon and the eutectic forming material is a material having P-type dopant therein.
4. A semiconductor device according to Claim 3 wherein the intrinsic semiconductor substrate has a conductivity within the range of 300 to 50,000 ohm centimeters.
5. A semiconductor device according to Claim 4 wherein the eutectic forming material is a gold solder having P-type dopant therein.
6. A semiconductor device according to Claim 5 wherein the eutectic forming material is boron doped gold solder.
7. A semiconductor device according to Claim 1 wherein horizontal isolation of the active device is accomplished by a P-type diffusion to a depth of less than 10 microns.
8. A method of fabricating a semiconductor device and mounting same upon the base pad of a package so as to provide for improved high frequency performance and increased thermal transfer from said device to said base pad comprising the steps of; selecting an intrinsic semiconductor substrate; providing a collector region in contact with said intrinsic semiconductor substrate; providing an epitaxial layer over said collector region and substrate; forming an emitter region and base region in said epitaxial layer proximate to said collector region; applying a doped eutectic forming material onto the surface of the base pad of said package; and heating said base pad and intrinsic substrate in contact with one another to a sufficiently high temperature to form a eutectic and cause some of the dopant atoms therein to diffuse into said intrinsic substrate to dope said substrate and thereby form the contact region of said substrate simultaneously with the formation of the eutectic bond between said substrate and said base pad.
9. A semiconductor device substantially as hereinbefore described with reference and as illustrated in the accompanying drawings.
10. A method of fabricating a semiconductor device substantially as herein described with reference to the drawings.
GB8012595A 1979-06-11 1980-04-16 High frequency high power P-I-N substrate semiconductor device and method for making same Withdrawn GB2051475A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US4734079A 1979-06-11 1979-06-11

Publications (1)

Publication Number Publication Date
GB2051475A true GB2051475A (en) 1981-01-14

Family

ID=21948401

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8012595A Withdrawn GB2051475A (en) 1979-06-11 1980-04-16 High frequency high power P-I-N substrate semiconductor device and method for making same

Country Status (5)

Country Link
JP (1) JPS568844A (en)
DE (1) DE3021102A1 (en)
FR (1) FR2458906A1 (en)
GB (1) GB2051475A (en)
NL (1) NL8003057A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988002554A1 (en) * 1986-09-27 1988-04-07 Robert Bosch Gmbh High-frequency power transistor with bipolar epitaxial technology
US7191916B2 (en) * 2003-03-06 2007-03-20 Alcon, Inc. Device for dispensing fluid medicine

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4433727A (en) * 1981-06-19 1984-02-28 Marathon Oil Company Oil recovery process
JPS58103541A (en) * 1981-12-16 1983-06-20 Toa Nenryo Kogyo Kk Padiation-resistant polyolefin composition

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988002554A1 (en) * 1986-09-27 1988-04-07 Robert Bosch Gmbh High-frequency power transistor with bipolar epitaxial technology
US5032886A (en) * 1986-09-27 1991-07-16 Robert Bosch Gmbh High-frequency power transistor
US7191916B2 (en) * 2003-03-06 2007-03-20 Alcon, Inc. Device for dispensing fluid medicine

Also Published As

Publication number Publication date
DE3021102A1 (en) 1981-01-08
NL8003057A (en) 1980-12-15
FR2458906A1 (en) 1981-01-02
JPS568844A (en) 1981-01-29

Similar Documents

Publication Publication Date Title
JP2995723B2 (en) Vertical current semiconductor device using wafer bonding and method of manufacturing the same
US2861018A (en) Fabrication of semiconductive devices
US3600651A (en) Bipolar and field-effect transistor using polycrystalline epitaxial deposited silicon
US4897362A (en) Double epitaxial method of fabricating semiconductor devices on bonded wafers
US3611067A (en) Complementary npn/pnp structure for monolithic integrated circuits
US7611953B2 (en) Bipolar transistor with isolation and direct contacts
US4146905A (en) Semiconductor device having complementary transistor structures and method of manufacturing same
US3648123A (en) Epitaxial base high-speed pnp power transistor
US4131910A (en) High voltage semiconductor devices
JPH02272758A (en) Transistor and its manufacture
JPH04283914A (en) Cladded semiconductor substrate and production method thereof
US5256896A (en) Polysilicon-collector-on-insulator polysilicon-emitter bipolar transistor
GB2051475A (en) High frequency high power P-I-N substrate semiconductor device and method for making same
JP2017531317A (en) Method for manufacturing a semiconductor device comprising a thin semiconductor wafer
US3993512A (en) Method of manufacturing an integrated circuit utilizing outdiffusion and multiple layer epitaxy
US3959039A (en) Method of manufacturing vertical complementary bipolar transistors each with epitaxial base zones
US3677280A (en) Optimum high gain-bandwidth phototransistor structure
US4165516A (en) Semiconductor device and method of manufacturing same
US4141136A (en) Method of fabricating semiconductor devices with a low thermal resistance and devices obtained by the method
US3614560A (en) Improved surface barrier transistor
US3761326A (en) Process for making an optimum high gain bandwidth phototransistor structure
US3455748A (en) Method of making a narrow base transistor
JP3450095B2 (en) Semiconductor device and manufacturing method thereof
US4122482A (en) Vertical complementary bipolar transistor device with epitaxial base zones
US3443174A (en) L-h junction lateral transistor

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)