CN111326103A - Pixel circuit and display device - Google Patents
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- 239000003990 capacitor Substances 0.000 claims description 21
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- 238000007667 floating Methods 0.000 description 3
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- 230000005540 biological transmission Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
Abstract
The invention discloses a pixel circuit which comprises a light-emitting unit, a driving transistor, a reset circuit, a compensation circuit and a data circuit. The light emitting unit is used for emitting light according to the driving current. The driving transistor is used for providing a driving current to the light emitting unit. The reset circuit includes a first reset switch coupled to a first power source terminal and a first node for providing a first voltage. The compensation circuit is used for detecting the critical voltage of the driving transistor and comprises a first compensation switch coupled between a first node and a second power supply end. When the light emitting unit emits light, the first reset switch and the first compensation switch are turned off, and the first reset switch, the first node and the first compensation switch form a leakage current path between the first power terminal and the second power terminal to balance the first voltage. The first power supply terminal and the second power supply terminal are used for supplying different voltages.
Description
Technical Field
The present invention relates to display technologies, and more particularly, to a pixel circuit suitable for low frame refresh rate and a related display device.
Background
Modern people pay attention to the health management of individuals, and often measure various physiological indices using wearable devices (e.g., smartband and watch). Wearable devices typically perform data collection, storage, and wireless communication functions for long periods of time without external power supplies. Therefore, one of the design requirements of the wearable device is to reduce power consumption as much as possible with a limited total amount of power. Reducing the refresh rate of the display module is one of the effective means for saving power, but the brightness of the pixel circuit is gradually changed due to leakage at a low refresh rate, thereby reducing the display quality. In addition, the pixel circuits at different positions in the display module may have different device characteristics due to manufacturing process factors, so that the brightness of the display screen is not uniform.
Disclosure of Invention
The invention provides a pixel circuit which comprises a light-emitting unit, a driving transistor, a reset circuit, a compensation circuit and a data circuit. The light emitting unit is used for emitting light according to the driving current. The driving transistor comprises a control end, wherein the driving transistor is used for providing driving current to the light-emitting unit. The reset circuit includes a first reset switch and a first node for providing a first voltage, wherein the first reset switch is coupled between the first node and a first power source terminal, the first node is coupled to the control terminal of the driving transistor, the compensation circuit is coupled to the first node and the driving transistor for detecting a threshold voltage of the driving transistor, and the compensation circuit includes a first compensation switch, wherein the first compensation switch is coupled between the first node and a second power source terminal. The data circuit is coupled to the compensation circuit for providing a data voltage to the compensation circuit. When the light emitting unit emits light, the first reset switch and the first compensation switch are turned off, and the first reset switch, the first node and the first compensation switch form a leakage current path between the first power terminal and the second power terminal to balance the first voltage, and the first power terminal and the second power terminal are used for providing different voltages.
The invention also provides a display device, which comprises a gate driver, a source driver and a plurality of pixel circuits. Each pixel circuit is coupled to the source driver and the gate driver. Each pixel circuit includes a light emitting unit, a driving transistor, a reset circuit, a compensation circuit, and a data circuit. The light emitting unit is used for emitting light according to the driving current. The driving transistor comprises a control end, wherein the driving transistor is used for providing driving current to the light-emitting unit. The reset circuit comprises a first reset switch and a first node for receiving a first voltage, wherein the first reset switch is coupled between the first node and a first power supply end, and the first node is coupled to the control end of the driving transistor. The compensation circuit is coupled to the first node and the driving transistor for detecting a threshold voltage of the driving transistor, and includes a first compensation switch coupled between the first node and a second power source terminal. The data circuit is coupled to the compensation circuit for providing a data voltage to the compensation circuit. When the light emitting unit emits light, the first reset switch and the first compensation switch are turned off, and the first reset switch, the first node and the first compensation switch form a leakage current path between the first power terminal and the second power terminal to balance the first voltage, and the first power terminal and the second power terminal are used for providing different voltages.
The pixel circuit and the display device are suitable for relevant applications with strict requirements on leakage current, and can generate uniform brightness.
Drawings
Fig. 1 is a circuit schematic diagram of a pixel circuit according to an embodiment of the invention.
Fig. 2 is a simplified timing diagram of driving signals when the pixel circuit of fig. 1 operates.
FIG. 3A is a circuit diagram illustrating the pixel circuit of FIG. 2 in a reset phase.
FIG. 3B is a schematic circuit diagram illustrating the operation of the pixel circuit of FIG. 2 in the compensation phase.
FIG. 3C is a circuit diagram illustrating the pixel circuit of FIG. 2 in a write phase.
FIG. 3D is a circuit diagram illustrating the pixel circuit of FIG. 2 in a light-emitting stage.
FIG. 4 is a simplified functional block diagram of a display device according to an embodiment of the invention.
Wherein, the reference numbers:
100: pixel circuit
110: light emitting unit
120: driving transistor
130: reset circuit
140: compensation circuit
150: data circuit
PW 1: first power supply terminal
PW 2: the second power supply terminal
PW 3: third power supply terminal
PW 4: third power supply terminal
PW 5: the fifth power supply terminal
SW 1: first reset switch
SW 2: second reset switch
SW 3: first compensation switch
SW 4: second compensation switch
SW 5: third compensation switch
SW 6: fourth compensation switch
SW 7: data switch
C1: first compensation capacitor
C2: second compensation capacitor
n 1: first node
n 2: second node
n 3: third node
S1: a first drive signal
S2: second drive signal
S3: third drive signal
S4: fourth drive signal
OVDD: high voltage of system
OVSS: low voltage of system
Vref 1: a first reference voltage
Vref 2: second reference voltage
Vdata: data voltage
T1: reset phase
T2: compensation phase
T3: write phase
T4: stage of luminescence
200: pixel circuit
210: gate driver
220: source driver
230: pixel circuit
240[1] to 240[ n ]: data line
250[1] to 250[ n ]: gate line
CT1[1] -CT 1[ n ], CT2[1] -CT 2[ n ], CT3[1] -CT 3[ n ]: control signal
R < 1 > -R < n >: line of pixels
Detailed Description
The following detailed description of the embodiments in conjunction with the accompanying drawings is provided to better understand the aspects of the present invention, but the embodiments are not intended to limit the scope of the present disclosure, and the description of the structural operations is not intended to limit the order of execution thereof, and any structure resulting from a rearrangement of elements to produce a device with equivalent efficacy is within the scope of the present disclosure. Moreover, the drawings are for illustrative purposes only and are not drawn to scale in accordance with established standards and practice in the industry, and the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. In the following description, the same elements will be described with the same reference numerals for ease of understanding.
Fig. 1 is a circuit diagram of a pixel circuit 100 according to an embodiment of the invention. The pixel circuit 100 includes a light emitting unit 110, a driving transistor 120, a reset circuit 130, a compensation circuit 140, and a data circuit 150. The pixel circuit 100 also includes a first power source terminal PW1, a second power source terminal PW2, a third power source terminal PW3, a fourth power source terminal PW4 and a fifth power source terminal PW 5. The reset circuit 130 receives the system high voltage OVDD through the first power source terminal PW 1; the compensation circuit 140 receives a first reference voltage Vref1 and a system low voltage OVSS through a second power source terminal PW2 and a third power source terminal PW3, respectively; the data circuit 150 receives the data voltage Vdata or the second reference voltage Vref2 through the fourth power source terminal PW 4.
As shown in fig. 1, the driving transistor 120 includes a first terminal, a second terminal and a control terminal. The second terminal of the driving transistor 120 is used for providing a driving current (e.g., the driving current idri shown in fig. 3D) to the light emitting unit 110, so that the light emitting unit 110 generates a corresponding luminance according to the magnitude of the driving current. The first terminal and the control terminal of the driving transistor 120 are coupled to the compensation circuit 140.
A first terminal of the light emitting unit 110 is coupled to a second terminal of the driving transistor 120; a second terminal of the light emitting unit 110 is coupled to a fifth power source terminal PW 5. In some embodiments, the light emitting unit 110 is an organic light-emitting diode (OLED), and the first end and the second end of the light emitting unit 110 are an anode end and a cathode end, respectively. In some embodiments, the light emitting unit 110 is a Micro light-emitting diode (Micro LED).
In some embodiments, the driving transistor 120 is a P-type or N-type Thin Film Transistor (TFT). In some embodiments, the driving transistor 120 is a P-type or N-type metal-oxide-semiconductor field-effect transistor (MOSFET). In the embodiment of the present invention, the driving transistor 120 is exemplified by a P-type transistor. The first terminal of the driving transistor 120 is a source, the second terminal is a drain, and the control terminal is a gate.
Since the driving transistors 120 have different threshold voltages due to material or manufacturing process, the threshold voltages of the driving transistors 120 may be different in a display device using a plurality of pixel circuits 100. Therefore, in each pixel circuit 100, the compensation circuit 140 detects the threshold voltage of the driving transistor 120, so as to compensate for the variation of the driving transistor 120. Therefore, the driving current value outputted by the driving transistor 120 is not affected, and the brightness of each light emitting unit 110 is consistent.
As shown in fig. 1, the compensation circuit 140 includes a plurality of switches, capacitors and nodes, which are respectively a first compensation switch SW3, a second compensation switch SW4, a third compensation switch SW5 and a fourth compensation switch SW 6; a first compensation capacitor C1 and a second compensation capacitor C2; and a second node n2 and a third node n 3. A first terminal of the first compensation switch SW3 is coupled to the control terminal of the driving transistor 120, and is coupled to a second terminal of the first compensation capacitor C1 through a first node n 1; a second terminal of the first compensation switch SW3 is coupled to a second power source terminal PW 2. A first terminal of the second compensation switch SW4 is coupled to the first terminal of the first compensation capacitor C1 and the second terminal of the second compensation capacitor C2, and is also coupled to the second node n 2; the second terminal of the second compensation switch SW4 is coupled to the first terminal of the driving transistor 120. A first terminal of the third compensation switch SW5 is coupled to the second terminal of the driving transistor 120 and also coupled to the first terminal of the light emitting unit 110; a second terminal of the third compensation switch SW5 is coupled to a second terminal of the fourth compensation switch SW6 and a third power source terminal PW 3. The first terminal of the fourth compensation switch SW6 is coupled to the first terminal of the second compensation capacitor C2 and also coupled to the third node n 3.
The reset circuit 130 includes a first reset switch SW1, a second reset switch SW2, and a first node n 1. A first terminal of the first reset switch SW1 is coupled to a first power supply terminal PW 1; the second terminal of the first reset switch SW1 is coupled to the first terminal of the first compensation capacitor C1, the first terminal of the first compensation switch SW3 and the control terminal of the driving transistor 120 through a first node n 1. The first terminal of the second reset switch SW2 is also coupled to the first power source terminal PW 1; the second terminal of the second reset switch SW2 is coupled to the first terminal of the first compensation capacitor C1, the second terminal of the second compensation capacitor C2 and the first terminal of the second compensation switch SW4 through a second node n 2.
In some embodiments, the first reset switch SW1, the second reset switch SW2, the first compensation switch SW3, the second compensation switch SW4, the third compensation switch SW5, the fourth compensation switch SW6 and the data switch SW7 are implemented as P-type transistors. The first reset switch SW1, the second reset switch SW2, the first compensation switch SW3, the second compensation switch SW4, the third compensation switch SW5, the fourth compensation switch SW6 and the data switch SW7 respectively have a first end, a second end and a control end, wherein the first end is a source, the second end is a drain and the control end is a gate.
Fig. 2 is a simplified timing diagram of a plurality of driving signals provided to the pixel circuit 100 of fig. 1.
The plurality of driving signals includes a first driving signal S1, a second driving signal S2, a third driving signal S3, and a fourth driving signal S4. Referring to fig. 2 and fig. 1, the first driving signal S1 is provided to the control terminal of the first reset switch SW 1. The second driving signal S2 is provided to the control terminal of the first compensation switch SW3, the control terminal of the third compensation switch SW5 and the control terminal of the data switch SW 7. The third driving signal S3 is provided to the control terminal of the second compensation switch SW 4. The fourth driving signal S4 is provided to the control terminal of the second reset switch SW2 and the control terminal of the fourth compensation switch SW 6.
Fig. 3A to 3D are circuit schematic diagrams of the pixel circuit 100 of fig. 1 at respective operation stages of fig. 2. As shown in fig. 3A to 3D, the first node n1 is used for providing a first voltage V1; the second node n2 is used for providing a second voltage V2; the third node n3 is used to provide a third voltage V3, as described in more detail below.
In the reset period T1, the first driving signal S1, the third driving signal S3 and the fourth driving signal S4 provide a Logic High level (e.g., a low voltage that can turn on the P-type transistor) to turn on the corresponding first reset switch SW1, the second reset switch SW2, the second compensation switch SW4 and the fourth compensation switch SW 6. The second driving signal S2 provides a Logic High level (e.g., a High voltage that can turn off the P-type transistor) to turn off the corresponding first compensation switch SW3, third compensation switch SW5 and data switch SW 7.
As shown in fig. 3A, the first reset switch SW1 receives the system high voltage OVDD through the first power source terminal PW1, and the system high voltage OVDD is transmitted to the control terminal of the driving transistor 120 through the first node n 1.
The second reset switch SW2 receives the system high voltage OVDD via the first power terminal PW1, and the system high voltage OVDD is transmitted to the first terminal of the driving transistor 120 via the second node n 2.
The fourth compensation switch SW6 receives the system low voltage OVSS through the third power terminal PW3, and the system low voltage OVSS is transmitted to the third node n 3.
Since the level of the control terminal of the driving transistor 120 is the same as the level of the first terminal of the driving transistor 120, the driving transistor 120 is in an off state in the reset phase.
In the compensation phase T2, the second driving signal S2 and the third driving signal S3 provide logic high level to turn on the corresponding first compensation switch SW3, second compensation switch SW4, third compensation switch SW5 and data switch SW 7; the first driving signal S1 and the fourth driving signal S4 provide logic low levels to turn off the corresponding first reset switch SW1, second reset switch SW2 and fourth compensation switch SW 6.
As shown in fig. 3B, the first compensation switch SW3 receives the first reference voltage Vref1 through the second power source terminal PW2, so that the level of the first voltage V1 supplied from the first node n1 is changed from the system high voltage OVDD to the first reference voltage Vref 1.
At this time, the level of the control terminal of the driving transistor 120 is the first reference voltage Vref1, and the level of the first terminal of the driving transistor 120 is the system high voltage OVDD. In the compensation phase, the first reference voltage Vref1 is lower than the system high voltage OVDD, and the driving transistor 120 is turned on.
The first compensation capacitor C1 discharges to the third power terminal PW3 through the second compensation switch SW4, the driving transistor 120 and the fourth compensation switch SW 5.
The first compensation capacitor C1 is continuously discharged until the difference between the level of the first terminal of the driving transistor 120 (equivalent to the second voltage V2 at the second node n 2) and the level of the control terminal of the driving transistor 120 (equivalent to the first voltage V1 at the first node n 1) reaches the threshold voltage of the driving transistor 120. At this time, the voltage difference between the control terminal and the first terminal of the driving transistor 120 reaches the threshold voltage, so that the driving transistor 120 is changed from the original on state to the off state.
In other words, the second voltage V2 provided by the second node n2 has the level shown in the following equation 1:
v2 Vref1+ | Vth | equation 1
Vth in equation 1 represents the threshold voltage of the driving transistor 120. In addition, the data switch SW7 receives the second reference voltage Vref2 through the fourth power terminal PW4, and the second reference voltage Vref2 is transmitted to the third node n 3.
In addition, the third compensation switch SW5 receives the system low voltage OVSS through the third power source terminal PW3, so that the first terminal of the light emitting cell 110 receives the system low voltage OVSS through the third compensation switch SW5, thereby removing the residual charges of the parasitic capacitance of the light emitting cell 110 itself. Therefore, the light emitting unit 110 can provide better contrast in the subsequent light emitting stage.
In the write phase T3, the second driving signal S2 provides a logic high level, so that the corresponding first compensation switch SW3, third compensation switch SW5 and data switch SW7 are turned on; the first driving signal S1, the third driving signal S3, and the fourth driving signal S4 provide logic low levels to turn off the corresponding first reset switch SW1, second reset switch SW2, second compensation switch SW4, and fourth compensation switch SW 6.
As shown in fig. 3C, the data switch SW7 receives the data voltage Vdata through the fourth power source terminal PW4, and the data voltage Vdata is transmitted to the third node n 3.
At this time, since the second node n2 is in a floating state and the first compensation capacitor C1 and the second compensation capacitor C2 are connected in series, the second voltage V2 provided by the second node n2 becomes a level shown in the following equation 2:
in the lighting period T4, the third driving signal S3 and the fourth driving signal S4 provide a logic high level to turn on the corresponding second reset switch SW2, the second compensation switch SW4 and the fourth compensation switch SW 6; the first driving signal S1 and the second driving signal S2 provide logic low levels to turn off the corresponding first reset switch SW1, the first compensation switch SW3, the third compensation switch SW5 and the data switch SW 7.
As shown in fig. 3D, the second reset switch SW2 receives the system high voltage OVDD through the first power terminal PW1, and the system high voltage OVDD is transmitted to the second node n 2. The driving current idri flows from the first power source terminal PW1 to the fifth power source terminal PW5 through the second reset switch SW2, the second compensation switch SW4, the driving transistor 120 and the light emitting unit 110.
At this time, since the first node n1 is in a floating state. The first voltage V1 (i.e., the voltage at the control terminal of the driving transistor 120) provided by the first node n1 changes to the level shown in the following equation 3:
in the light emitting period, the first voltage V1 is lower than the second voltage V2, so that the driving transistor 120 is turned on, and the pixel circuit 100 provides a driving current idri to the light emitting unit 110 as shown in the following formula 4:
in equation 4, k represents the product of carrier mobility (carrier mobility), gate unit capacitance (gate unit capacitance), and aspect ratio of the driving transistor 120.
Since equation 4 does not include the threshold voltage parameter (Vth) of the driving transistor 120, the threshold voltage variation of the driving transistor 120 does not affect the magnitude of the driving current idri. Therefore, the brightness of the light emitting unit 110 can be accurately controlled, so that the display device using the pixel circuit 100 can generate uniform brightness, thereby providing a high-quality display screen.
In the light emitting stage of the embodiment in which the switches SW 1-SW 7 of the pixel circuit 100 are all implemented by transistors, the first reset switch SW1 and the first compensation switch SW3 may have leakage.
For example, during the light-emitting period, the first reference voltage Vref1 is lower than the first voltage V1, so the first reset switch SW1, the first node n1 and the first compensation switch SW3 form a leakage current path between the first power source terminal PW1 and the second power source terminal PW 2. The leakage current L1 of the first reset switch SW1 flows from the first reset switch SW1 through the first node n1 and to the first compensation switch SW 3. The leakage current L2 of the first compensation switch SW3 flows from the first compensation switch SW3 to the second power source PW 2.
In some embodiments, the magnitudes of the leakage current L1 and the leakage current L2 are designed to be equal. Therefore, during the light emitting period, even if the first reset switch SW1 and the first compensation switch SW3 have leakage, the voltage level of the control terminal of the driving transistor 120 is balanced with the first voltage V1, so that the operation state of the driving transistor 120 is not affected.
In addition, the fourth compensation switch SW6 receives the system low voltage OVSS through the third power source terminal PW3, so that the third voltage V3 provided by the third node n3 is fixed to the system low voltage OVSS, and thus the third node n3 is not in a floating state. Therefore, the third node n3 does not affect the voltage value of the second node n2 (the second voltage V2), and thus does not affect the magnitude of the driving current idri.
In some embodiments requiring a higher degree of design flexibility, the first driving signal S1, the second driving signal S2, the third driving signal S3 and the fourth driving signal S4 may have different voltage ranges.
In some embodiments, the driving signals according to fig. 2 are provided to the pixel circuit 100 of fig. 1, and the operations of fig. 3A to fig. 3D are implemented. Table one shows the variation of the voltage at the control terminal of the driving transistor 120 of the pixel circuit 100 during a frame period (frame period) with a length of 66.67 microseconds (ms).
As shown in table i, the variation of the voltage level at the control terminal of the driving transistor 120 is very low in the low gray scale, middle gray scale and high gray scale display conditions, which means that the leakage currents L1 and L2 do not affect the operation state of the driving transistor 120. Thus, the pixel circuit 100 is suitable for use in applications where low picture update frequencies are critical for leakage current requirements.
Fig. 4 is a simplified functional block diagram of a display device 200 according to an embodiment of the invention. The display device 200 includes a gate driver 210, a source driver 220, a plurality of pixel circuits 230, a plurality of data lines 240[1] to 240[ n ] and a plurality of gate lines 250[1] to 250[ n ], and the plurality of pixel circuits 230 are arranged in a plurality of pixel rows R [1] to R [ n ], where n is a positive integer.
The gate driver 210 is used for providing a plurality of control signals CT1[1] -CT 1[ n ], CT2[1] -CT 2[ n ], and CT3[1] -CT 3[ n ] to the pixel circuit 230 through the gate lines 250[1] -250 [ n ]. The source driver 220 is used to provide a data voltage (e.g., the data voltage Vdata of FIG. 1) to the pixel circuit 230 through the data lines 240[1] -240 [ n ].
The above-mentioned element numbers and the indices 1 to n in the signal numbers are only for convenience of referring to the respective elements and signals, and are not intended to limit the number of the elements and signals to a specific number. For example, control signal CT1[1] is provided to the first row R [1] of pixel matrix 230, control signal CT1[2] is provided to the second row R [2] of pixel matrix 230, and so on.
In some embodiments, the pixel circuit 230 is implemented by the pixel circuit 100 of fig. 1. The pixel circuits 230 in the pixel row R [ i ] use the control signals CT1[ i-1], CT1[ i ], CT2[ i ] and CT3[ i ] as the corresponding first driving signal S1, second driving signal S2, third driving signal S3 and fourth driving signal S4, respectively, wherein i is a positive integer less than or equal to n. Similarly, the pixel circuits 230 in the pixel row R [ i +1] respectively use the control signals CT1[ i ], CT1[ i +1], CT2[ i +1] and CT3[ i +1] as the corresponding first driving signal S1, second driving signal S2, third driving signal S3, fourth driving signal S4, and so on.
That is, the first compensation switch SW3 of the pixel circuit 230 in the pixel row R [ i ] and the first reset switch SW1 of the pixel circuit 230 in the pixel row R [ i +1] receive the same control signal CT1[ i ].
The pixel circuits 230 in the pixel row R [1] use the control signals CT1[1], CT2[1] and CT3[1] as the corresponding second, third and fourth driving signals S2, S3 and S4, respectively, and use the control signal CT1[0] provided by another gate line (not shown) as the corresponding first driving signal S1.
As can be seen from the above, the front and rear rows of the pixel matrix 230 can share a corresponding one of the control signals CT1[1] CT1[ n ]. Thus, the circuit architecture of the gate driver 210 can be simplified.
Certain terms are used throughout the description and claims to refer to particular components. However, those of ordinary skill in the art will appreciate that the various elements may be referred to by different names. The specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, "coupled" herein includes any direct and indirect connection. Therefore, if a first element is coupled to a second element, the first element may be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or may be indirectly connected to the second element through another element or a connection means.
In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. A pixel circuit, comprising:
a light emitting unit for emitting light according to a driving current;
a driving transistor including a control terminal, wherein the driving transistor is used for providing the driving current to the light emitting unit;
a reset circuit including a first reset switch and a first node for providing a first voltage, wherein the first reset switch is used for selectively connecting the first node and a first power terminal according to a first driving signal, and the first node is coupled to the control terminal of the driving transistor;
a compensation circuit coupled to the first node and the driving transistor for detecting a threshold voltage of the driving transistor, wherein the compensation circuit comprises a first compensation switch coupled between the first node and a second power source terminal; and
a data circuit coupled to the compensation circuit for providing a data voltage to the compensation circuit;
when the light-emitting unit emits light, the first reset switch and the first compensation switch are turned off, and the first reset switch, the first node and the first compensation switch form a leakage current path between the first power terminal and the second power terminal to balance the first voltage, and the first power terminal and the second power terminal are used for providing different voltages.
2. The pixel circuit according to claim 1, wherein the first compensation switch comprises a first terminal, a second terminal and a control terminal, the control terminal of the first compensation switch is configured to receive a second driving signal, the first terminal of the first compensation switch is coupled to the first node, the second terminal of the first compensation switch receives a predetermined voltage through the second power source terminal,
wherein the compensation circuit further comprises:
a second node coupled to the reset circuit for receiving a second voltage;
a second compensation switch including a first terminal, a second terminal and a control terminal, wherein the control terminal of the second compensation switch is used for receiving a third driving signal, the first terminal of the second compensation switch is coupled to the second node, and the second terminal of the second compensation switch is coupled to the first terminal of the driving transistor;
a first compensation capacitor having a first end and a second end, wherein the first end of the compensation capacitor is coupled to the second node, and the second end of the compensation capacitor is coupled to the first node;
a third node coupled to the data circuit for receiving a third voltage;
a third compensation switch, including a first terminal, a second terminal and a control terminal, wherein the control terminal of the third compensation switch is used for receiving the second driving signal, the first terminal of the third compensation switch is used for receiving the system low voltage, and the second terminal of the third compensation switch is coupled to the second terminal of the driving transistor;
a fourth compensation switch, including a first terminal, a second terminal and a control terminal, wherein the control terminal of the fourth compensation switch is configured to receive a fourth driving signal, the first terminal of the fourth compensation switch is coupled to the third node, and the second terminal of the fourth compensation switch is configured to receive a system low voltage; and
and the second compensation capacitor is coupled between the second node and the third node.
3. The pixel circuit according to claim 2, wherein the first compensation switch and the third compensation switch are turned off, the second compensation switch and the fourth compensation switch are turned on, and the third voltage is equal to the system low voltage when the light emitting unit emits light.
4. The pixel circuit according to claim 1, wherein the first reset switch comprises a first terminal, a second terminal and a control terminal, the control terminal of the first reset switch is configured to receive the first driving signal, the first terminal of the first reset switch is configured to receive a system high voltage through the first power terminal, the second terminal of the first reset switch is coupled to the first node,
wherein the reset circuit further comprises:
a second reset switch, including a first terminal, a second terminal and a control terminal, wherein the control terminal of the second reset switch is used for receiving a fourth driving signal, the first terminal of the second reset switch is used for receiving the system high voltage through the first power source terminal, and the second terminal of the second reset switch is coupled to the compensation circuit.
5. The pixel circuit of claim 4, wherein when the light emitting unit emits light, the first reset switch is turned off, the second reset switch is turned on, and the system high voltage is higher than a first voltage of the first node.
6. The pixel circuit according to claim 4, wherein:
when the light-emitting unit does not emit light and the first reset switch and the second reset switch are conducted, the first voltage is equal to the system high voltage.
7. The pixel circuit of claim 1, wherein the data circuit further comprises:
a data switch including a first terminal, a second terminal and a control terminal, wherein the control terminal of the data switch is used for receiving a second driving signal, the first terminal of the data switch is used for receiving the data voltage, and the second terminal of the data switch is coupled to the compensation circuit.
8. A display device, comprising:
a gate driver;
a source driver; and
a plurality of pixel circuits coupled to the source driver and the gate driver, each of the pixel circuits comprising:
a light emitting unit for emitting light according to a driving current;
a driving transistor including a control terminal, wherein the driving transistor is used for providing the driving current to the light emitting unit;
a reset circuit including a first reset switch and a first node for receiving a first voltage, wherein the first reset switch is coupled between the first node and a first power source terminal, and the first node is coupled to the control terminal of the driving transistor;
a compensation circuit coupled to the first node and the driving transistor for detecting a threshold voltage of the driving transistor, wherein the compensation circuit comprises a first compensation switch coupled between the first node and a second power source terminal; and
a data circuit coupled to the compensation circuit for providing a data voltage to the compensation circuit;
when the light-emitting unit emits light, the first reset switch and the first compensation switch are turned off, and the first reset switch, the first node and the first compensation switch form a leakage current path between the first power terminal and the second power terminal to balance the first voltage, and the first power terminal and the second power terminal are used for providing different voltages.
9. The display device of claim 8, wherein the plurality of pixel circuits includes a first pixel circuit in an ith column and a second pixel circuit in an (i + 1) th column, and a control terminal of the first compensation switch of the first pixel circuit and a control terminal of the first reset switch of the second pixel circuit are configured to receive the same control signal.
10. The display apparatus according to claim 8, wherein the first reset switch comprises a first terminal, a second terminal and a control terminal, the control terminal of the first reset switch is used for receiving a first driving signal, the first terminal of the first reset switch is used for receiving a system high voltage through the first power terminal, the second terminal of the first reset switch is coupled to the first node,
wherein the reset circuit further comprises:
a second reset switch, including a first terminal, a second terminal and a control terminal, wherein the control terminal of the second reset switch is used for receiving another driving signal different from the first driving signal, the first terminal of the second reset switch is used for receiving the system high voltage through the first power terminal, and the second terminal of the second reset switch is coupled to the compensation circuit;
when the light-emitting unit emits light, the first reset switch is turned off, the second reset switch is turned on, and the system high voltage is higher than a first voltage of the first node;
when the light-emitting unit does not emit light and the first reset switch and the second reset switch are conducted, the first voltage is equal to the system high voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| TW108136191A TWI717855B (en) | 2019-10-05 | 2019-10-05 | Pixel circuit and display device |
| TW108136191 | 2019-10-05 |
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| CN111326103A true CN111326103A (en) | 2020-06-23 |
| CN111326103B CN111326103B (en) | 2021-08-20 |
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| WO2023272540A1 (en) * | 2021-06-30 | 2023-01-05 | 京东方科技集团股份有限公司 | Pixel circuit and driving method therefor, display substrate, and display apparatus |
| TWI796723B (en) * | 2021-07-06 | 2023-03-21 | 友達光電股份有限公司 | Display device |
| TWI786853B (en) * | 2021-09-28 | 2022-12-11 | 友達光電股份有限公司 | Display panel and operation method thereof |
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| TW202115703A (en) | 2021-04-16 |
| TWI717855B (en) | 2021-02-01 |
| CN111326103B (en) | 2021-08-20 |
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