TWI479468B - Pixel and display device utilizing the same - Google Patents

Description

Pixel structure and display device

The present invention relates to a pixel structure, and more particularly to a pixel structure of a display device.

According to the backplane process technology, the pixel structure of the Active Matrix Organic Light Emitting Display (AMOLED) can be divided into a P-type and an N-type drive type. The P-type drive type is commonly used in the backplane technology of Low Temperature Poly-Silicon (LTPS). The N-type drive type is widely used in the amorphous-type (a-si) and Indium Gallium Zinc Oxide (IGZO) backsheet technology.

Fig. 7A is a schematic diagram of a pixel of a conventional P-type driving type. The driving transistor PTFT2 is of a P type, and its gate-source voltage is a voltage difference between the data voltage Dm and the operating voltage PVDD. The organic light emitting diode 710 is a general organic light emitting diode (normal OLED). Fig. 7B is a schematic diagram of a pixel of a conventional N-type driving type. The driving transistor NTFT2 is N-type, and its gate-source voltage is a voltage difference between the data voltage Dm and the operating voltage PVEE. The organic light emitting diode 720 is an inverted OLED.

However, reverse phase organic light emitting diodes are less likely to be fabricated. To solve this problem, the prior art provides another pixel structure. As shown in FIG. 8, the organic light-emitting diode 810 is a general organic light-emitting diode, and the driving transistor NTFT2 is N-type. The anode of the organic light emitting diode 810 is coupled to the source of the driving transistor NTFT2. When the voltage across the organic light-emitting diode 810 increases due to aging of the device, the increased voltage across the gate will affect the gate-source voltage of the transistor NTFT2, thereby reducing the drive current generated by the transistor NTFT2, resulting in an imprint.

Furthermore, the metal film provided with the operating voltage PVEE is vapor-deposited on the glass substrate, and the voltage drop generated by the organic light-emitting diode 810 is reflected in the source voltage of the driving transistor NTFT2, thereby affecting the gate of the transistor NTFT2. - The source voltage makes the brightness of the picture uneven.

The present invention provides a pixel structure including a first transistor, a light emitting element, a second transistor, a switching unit, a coupling unit, and a compensation unit. The first transistor has a first gate, a first terminal and a second terminal, and transmits a data signal to a first node during data writing. The second transistor has a second gate, a third end, and a fourth end. The second gate is coupled to a second node. The third end is coupled to a third node. The fourth end is coupled to a fourth node. The switching unit is connected in series with the light emitting element and the second transistor between a first operating voltage and a second operating voltage. The coupling unit is coupled between the first node and the second node. The compensation unit is coupled between the second and third nodes. During a compensation, the voltage of the second node is equal to the voltage of the third node. During a reset, the voltage at the third node is equal to a fixed voltage. The reset period is earlier than the data write period and is between the compensation period and the data write period.

The invention further provides a display device comprising a scan driver, a data driver and at least one pixel. The scan driver provides at least one scan signal. The data driver provides at least one data signal. The pixel includes a first transistor, A light emitting element, a second transistor, a switching unit, a coupling unit and a compensation unit. The first transistor has a first gate, a first end and a second end, and transmits a data signal to a first node according to the scan signal during a data writing. The second transistor has a second gate, a third end, and a fourth end. The second gate is coupled to a second node. The third end is coupled to a third node. The fourth end is coupled to a fourth node. The switching unit is connected in series with the light emitting element and the second transistor between a first operating voltage and a second operating voltage. The coupling unit is coupled between the first node and the second node. The compensation unit is coupled between the second and third nodes. During a compensation, the voltage of the second node is equal to the voltage of the third node. During a reset, the voltage at the third node is equal to a fixed voltage. The reset period is earlier than the data write period and is between the compensation period and the data write period.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

100‧‧‧ display device

110‧‧‧Scan Drive

120‧‧‧Data Drive

210, 510‧‧‧ Switching unit

220, 520‧‧‧compensation unit

230, 530‧‧‧ coupling unit

240, 540‧‧‧Lighting elements

310‧‧‧Initial period

250, 260, 550‧‧‧ setting unit

320‧‧‧Compensation period

330‧‧‧Reset period

340‧‧‧data writing period

350‧‧‧Lighting period

P ₁₁ ~P _mn ‧‧‧ pixels

C1, C2‧‧‧ capacitor

N, G, S, D‧‧‧ nodes

REF‧‧‧reference voltage

SN ₁ ~ SN _n , Sn‧‧ ‧ scan signals

DATA ₁ ~DATA _m , Dm‧‧‧ data signal

241, 541, 710, 720, 810‧‧‧ Organic Light Emitting Diodes

TN1~TN6, TP1~TP5, PTFT2, NTFT1, NTFT2‧‧‧O crystal

ELVDD, ELVSS, PVDD, PVEE‧‧‧ operating voltage

ENB, COM, RST‧‧‧ control signals

V _N , V _S , V _D , V _G , Vgs‧‧‧ voltage

Figure 1 is a schematic view of a display device of the present invention.

Figure 2 is a schematic view showing the structure of the pixel of the present invention.

Fig. 3 is a timing chart of control of the pixels of the present invention.

Figure 4 shows the voltages (VN, VS, VD, VG) of nodes N, S, D, G and the gate-to-source voltage (Vgs) of transistor TN2.

Fig. 5 is a schematic view showing another structure of the pixel of the present invention.

Fig. 6 is a control timing chart of the pixel structure of Fig. 5.

Fig. 7A is a schematic diagram of a pixel of a conventional P-type driving type.

Figures 7B and 8 are schematic diagrams of a conventional N-type drive pattern.

Figure 1 is a schematic view of a display device of the present invention. As shown, the display device 100 includes a scan driver 110, a data driver 120, and pixels P ₁₁ ~P _mn . Scan driver 110 provides scan signals SN ₁ ~ SN _n . The data driver 120 provides the data signals DATA ₁ ~ DATA _m . Each of the pixels P ₁₁ to P _mn receives a corresponding scan signal and data signal.

Taking pixel P _ij as an example, pixel P _ij receives data signal DATA _i according to scan signal SN _j and presents corresponding brightness according to data signal DATA _i . The invention does not limit the size of m, n, i, j. In a possible embodiment, m and n are any positive integers exceeding two. In addition, i and j are also arbitrary positive integers, and 1 < i < m, 1 < j < n.

Figure 2 is a schematic view showing the structure of the pixel of the present invention. As shown, the pixel P _ij includes transistors TN1, TN2, a switching unit 210, a compensation unit 220, a coupling unit 230, and a light-emitting element 240. The transistor TN1 supplies the data signal DATA _i to the node N in accordance with the scan signal SN _j . In this embodiment, the gate of the transistor TN1 receives the scan signal SN _j , the drain of which receives the data signal DATA _i , and the source of which is coupled to the node N.

The switching unit 210 is connected in series with the light emitting element 240 and the transistor TN2 between the operating voltages ELVDD and ELVSS. In the present embodiment, the operating voltage ELVDD is greater than ELVSS. The switching unit 210 transmits the operating voltage ELVDD to the node D according to the control signal ENB, wherein the node D is coupled to the drain of the transistor TN2.

In the present embodiment, the transistor TN2 is coupled between the switching unit 210 and the light emitting element 240. The present invention is not limited to the internal architecture of the switch unit 210. In a possible embodiment, the switch unit 210 is a transistor TN4. Gate of transistor TN4 The control signal ENB is received, the drain of which receives the operating voltage ELVDD, and the source of which is coupled to the node D.

The compensation unit 220 is coupled between the nodes G and D, and couples the gate and the drain of the transistor TN2 according to a control signal COM. In this embodiment, the nodes G and D are respectively coupled to the gate and the drain of the transistor TN2. The present invention does not limit the internal architecture of the compensation unit 220. In a possible embodiment, the compensation unit 220 is a transistor TN3. The gate of the transistor TN3 receives the control signal COM, the drain of which is coupled to the node D, and the source of which is coupled to the node G.

The coupling unit 230 is coupled between the nodes N and G for coupling the levels of the nodes G and S to an appropriate level according to the level of the node N. The present invention does not limit the internal architecture of the coupling unit 230. In a possible embodiment, the coupling unit 230 includes capacitors C1 and C2. The capacitor C1 is coupled between the nodes N and G for coupling the voltage of the node G to an appropriate level according to the voltage of the node N. The capacitor C2 is coupled between the nodes N and S for coupling the voltage of the node S to an appropriate level according to the voltage of the node N. In this embodiment, the node S is coupled to the source of the transistor TN2.

The light emitting element 240 is coupled to the node S and receives the operating voltage ELVSS. The invention does not limit the type of the light-emitting element 240. Any element that can emit light according to a driving current can be used as the light-emitting element 240. In this embodiment, the light-emitting element 240 is an organic light-emitting diode (OLED) 241. The anode of the organic light emitting diode 241 is coupled to the node S, and its cathode receives the operating voltage ELVSS.

During a compensation period, the voltage of node G is equal to the voltage of node D. During a reset, the voltage at node D is equal to a fixed voltage. In a possible embodiment, the fixed voltage is equal to the operating voltage ELVDD. During a data write, transistor TN1 transmits data signal DATA _i to node N. In this embodiment, the reset period is earlier than the data write period and is between the compensation period and the data write period. The mode of operation of the pixel P _ij will be explained later.

In other embodiments, the pixels P _ij further include setting units 250 and 260. The setting unit 250 can make the voltage of the node N equal to a reference voltage REF according to the control signal RST or COM. In a possible embodiment, the reference voltage REF is a low voltage level. In another possible embodiment, the reference voltage REF is equal to the scan signal SN _j . The present invention does not limit the circuit architecture of the setting unit 250. In this embodiment, the setting unit 250 is a transistor TN5. The gate of the transistor TN5 receives the control signal RST, the drain of which receives the reference voltage REF, and the source of which is coupled to the node N.

Similarly, the setting unit 260 also makes the voltage of the node S equal to the reference voltage REF or the scan signal SN _j according to the control signal RST or COM. The circuit architecture of the setting unit 260 is also not limited by the present invention. In this embodiment, the setting unit 260 is a transistor TN6. The gate of transistor TN6 receives control signal RST or COM, its drain reference voltage REF or scan signal SN _j , and its source is coupled to node S.

In the above embodiments, the transistors TN1 to TN6 are all N-type, but are not intended to limit the present invention. In other embodiments, the transistors in the pixel P _ij are all P-type, or may be partially P-type and partially N-type. In addition, in other embodiments, in order to reduce the component cost, the setting unit 250 or 260 may be omitted, or the setting units 250 and 260 may be omitted at the same time.

Fig. 3 is a control timing chart of the pixels of Fig. 2. Fig. 4 is a graph showing the voltages (V _N , V _S , V _D , V _G ) of the nodes N, S, D, and G of Fig. 2 and the gate-source voltage (Vgs) of the transistor TN2.

During the initial period 310, the scan signal SN _j and the control signal COM are at a low level. Therefore, the transistors TN1 and TN3 are not turned on. Since the control signal RST is at a high level, the transistor TN5 is turned on, and the voltage of the node N is equal to the reference voltage REF. At this time, the capacitor C1 couples the node G to a low potential. In a possible embodiment, the voltage of the node G is V _G = Vx + f2 * (REF - V _N ), where Vx is the voltage of the node G during the previous illumination period; f2 = C1/C1 + Cg_paras, where C1 is The capacitance of the capacitor C1, Cg_paras is the gate-related bypass capacitor of the transistor TN2, which contains other stray capacitances in series or parallel, such as the parasitic capacitance between the gate-source Cgs of the transistor TN2, the transistor TN2 gate - drain parasitic capacitance Cgd between the electrodes, the transistor base capacitance of Cox TN2, the node _N V period before a light emitting voltage N.

Since the node G is at a low voltage, the transistor TN2 is not conducted. At this time, the transistor TN6 is turned on, and therefore, the voltage of the node S is equal to the reference voltage REF. Since the control signal ENB is at a high level, the transistor TN4 is turned on. At this time, the voltage of the node D is equal to the operating voltage EVLDD.

During the compensation period 320, since the control signal RST is at a high level, the transistors TN5 and TN6 write the reference voltage REF to the nodes N and S, respectively. At this time, since the control signal COM is at a high level, the transistor TN3 is turned on. The node G is connected to the node D through the transistor TN3. Since the control signal ENB is at a low level, the transistor TN4 is not turned on. At this time, the charge of the node D charges the node G. The levels of nodes G and D will be REF+Vt, where REF is the reference voltage and Vt is the threshold voltage of transistor TN2. During this period, the threshold voltage Vt of the transistor TN2 can be detected and stored in the capacitor C1.

During the reset period 330, the scan signal SN _j , the control signals COM and RST are both low level, and therefore, the transistors TN1, TN3, TN5, and TN6 are not turned on, and the voltage V _N of the node _N , the voltage V _{S of the} node _S , The voltage V _{G of the} node G remains unchanged. At this time, since the transistor TN2 is not turned on, the organic light-emitting diode 241 (i.e., the light-emitting element 240) does not emit light. Since the control signal ENB is at a high level, the transistor TN4 is turned on, so the voltage V _{D of the} node D is equal to the operating voltage ELVDD.

During the data write period 340, the scan signal SN _j is at a high level, and therefore, the transistor TN1 transmits the data signal DATAi to the node N. Due to the coupling effect of the capacitor C1, the voltage of the node G is V _G = REF + Vt + f2 * (DATA _{i -} REF). In addition, through the coupling effect of C2, the voltage V _{S of the} node S is coupled to a level associated with the data signal DATA _i . In a possible embodiment, the voltage V _{S of the} node S is equal to REF+(DATA _i -REF)*f1, where f1=C2/C2+Cs_paras, C2 is the capacitance of the capacitor C2, and Cs_paras is the source correlation of the transistor TN2. The bypass capacitor includes the equivalent capacitance of the organic light-emitting diode 241 and other parallel stray capacitances, such as the gate-source parasitic capacitance of the transistor TN2 and the parasitic capacitance between the gate and the drain.

During the data writing period 340, the transistor TN2 needs to be in an on state, and the organic light emitting diode 241 cannot be turned on. Therefore, the voltage V _S needs to be smaller than ELVSS+Voled, where Volde is the conduction of the organic light emitting diode 241. Voltage. In addition, the gate-source voltage Vgs of the transistor TN2 needs to be greater than the threshold voltage Vt. The voltage V _{S is} as shown in the equation (1), and the voltage Vgs is as shown in the equation (2): V _S = REF + f1 * (DATA _{i -} REF) ≦ ELVSS + Volde (1)

Vgs=V _G -V _S ≧Vt=f2*(DATA _i -REF)+REF+Vt-REF-f1*(DATA _i -REF)≧Vt=(f2-f1)(DATA _i -REF)+Vt≧ Vt...............(2)

From equation (1), the following equation can be obtained: f1≦(ELVSS+Volde-REF)/(DATA _i -REF)......(3)

From equation (2), the following equation can be obtained: (f2-f1)(DATA _i -REF)≧0........................(4)

At this time, the transistor TN2 is turned on, and the charge of the node D charges the node S, but since the amount of charge of the node D is small and is a fixed level, the voltage V _{S of the} node S is only slightly changed, and the threshold voltage is Vt has nothing to do.

During the illumination period 350, the control signal ENB is at a high level, causing the transistor TN4 to be turned on. At this time, the voltage V _{D of the} node D is equal to the operating voltage ELVDD, and the transistor T2 can be operated in the saturation region. In addition, in the light-emitting period 350, since the scan signal SN _j , the control signals COM and RST are both low, the transistors TN1, TN3, TN5, and TN6 are not turned on. At this time, the node N is in a floating state. The voltage of node S is V _S =Voled+ELVSS. The voltage at node G is coupled by capacitor C2 to a level associated with Voled, which is: V _G = REF + f2 * (DATA _{i -} REF) + Vt + f3 * [Voled + ELVSS - [REF + f1 * ( DATA _i -REF)]=REF[1-f2-f3+f1*f3]+DATA _i *[f2-f1*f3]+f3*Voled+Vt+f3*ELVSS...(5)

The gate-source voltage Vgs of the transistor TN2 is as follows: VgS = V _G - V _S = REF [1-f2 - f3 + f1 * f3] + DATA _i * [f2 - f1 * f3] + (f3-1) * (Voled+ELVSS)+Vt..................(6)

The driving current I generated by the transistor TN2 is as follows: I = Kp * (Vgs - Vt) ² ................................. (8)

Where Kp = 1/2uCox*W/L, where u is the carrier mobility, Cox is the capacitance per unit area of the transistor T2, and W/L is the channel width to length ratio of the transistor T2.

After introducing equation (7) into equation (8), the following equation can be obtained: I=Kp*{REF[1-f2-f3+f1*f3]+DATA _i *[f2-f1*f3]+(f3- 1)*(Voled+ELVSS)+Vt-Vt} ² .......................................(9)

Assuming that the capacitances of capacitors C1 and C2 are much larger than the parasitic capacitance of each node of the circuit, the following equation can be obtained: I=Kp*{[DATA _i -REF]*[1-f1]} ² ..................( 10)

As can be seen from equation (10), during the light-emitting period 350, the drive current I generated by the transistor TN2 is independent of the threshold voltage Vt of the transistor TN2. Since the light-emitting element 240 emits light according to the driving current I, the brightness of the light-emitting element 240 is not affected when the transistors TN2 in different pixels have different threshold voltages. In addition, the drive current I generated by the transistor TN2 is also not affected by the variation of the operating voltage ELVDD.

In the present embodiment, the voltage V _{D of the} node D is independent of the threshold voltage Vt, whether during the reset period 330, the data writing period 340, or the light emitting period 350. Therefore, when the charge of the node D charges the node S, or the voltage of the node D is coupled to the node G, the change of the voltage Vgs is independent of the threshold voltage Vt, and therefore, no additional error is caused.

In addition, in the present embodiment, the organic light-emitting diodes 241 do not emit light during the start period 310, the compensation period 320, the reset period 330, and the data writing period 340. Only in the light-emitting period 350, the organic light-emitting diode 241 emits light, and therefore, the pixel of the present invention has a high contrast display quality.

In addition, the capacitance values of the capacitors C1 and C2 can be increased to bring f3 closer to 1, and the influence of the voltage Voled in the equation (9) can be minimized. In the present embodiment, during the initial period 310, the transistor TN2 is not conducted, and therefore, a large current does not flow into the organic light-emitting diode 241 via the transistor TN2, so that the organic light-emitting diode 241 emits light. During this period, if the organic light-emitting diode 241 emits light, the dark state of the pixel will be made dark, and the contrast will be greatly reduced.

In addition, the length of the compensation period 320 can be adjusted according to requirements, and is not limited to the writing time of a single material, so that the high-resolution panel can be more easily realized. Moreover, in the reset period 330, the voltage of the node D is a fixed voltage, so that the voltage offset of the node G after the compensation period can be reduced, and the compensation error can be reduced, so that the pixel exhibits better brightness.

Fig. 5 is a schematic view showing another structure of the pixel of the present invention. As shown, the pixel P _ij includes a transistor TP1, TP2, a switching unit 510, a compensation unit 520, a coupling unit 530, a light-emitting element 540, and a setting unit 550. The gate of the transistor TP1 receives the scan signal SN _j , the source of which receives the data signal DATA _i , and the drain of which is coupled to the node N.

The switch unit 510 is coupled between the transistor TP2 and the light emitting element 540 and operates according to the control signal ENB. As shown, the switch unit 510 includes a transistor TP4. The gate of the transistor TP4 receives the control signal ENB, the drain of which is coupled to the light-emitting element 540, the source of which is coupled to the node D, wherein the node D is coupled to the drain of the transistor TP2. The source of the transistor TP2 is coupled to the node S and receives the operating voltage PVDD.

The coupling unit 530 has only the capacitor C1 and is coupled between the nodes N and G, wherein the node G is the gate of the transistor TP2. The light emitting element 540 includes an organic light emitting diode 541. The anode of the organic light emitting diode 541 is coupled to the anode of the transistor TP4 The cathode receives its operating voltage PVEE. In this embodiment, the operating voltage PVEE is less than PVDD.

The setting unit 550 sets the level of the node N to be equal to the reference voltage REF according to the control signal RST. In a possible embodiment, the reference voltage REF is a low voltage or equal to the scan signal SN _j . In another possible embodiment, the setting unit 550 sets the level of the node N to be equal to the reference voltage REF according to the control signal COM. In the embodiment, the setting unit 550 includes a transistor TP5. The gate of the transistor TP5 receives the control signal RST, the source thereof receives the reference voltage REF, and the drain thereof is coupled to the node N.

In this embodiment, the transistors TP1 TP TP5 are all P-type transistors. Additionally, in other embodiments, the setting unit 550 can be omitted. Fig. 6 is a control timing chart of the pixel structure of Fig. 5. Since the operation principle of Fig. 6 is similar to that of Fig. 3, it will not be described again.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

P _ij ‧ ‧ pixels

SN _j ‧‧‧ scan signal

DATA _i ‧‧‧ data signal

TN1~TN6‧‧‧O crystal

210‧‧‧Switch unit

220‧‧‧Compensation unit

230‧‧‧Coupling unit

240‧‧‧Lighting elements

241‧‧‧Organic Luminescent Diodes

250, 260‧‧‧ setting unit

N, G, S, D‧‧‧ nodes

ELVDD, ELVSS‧‧‧ operating voltage

ENB, COM, RST‧‧‧ control signals

REF‧‧‧reference voltage

C1, C2‧‧‧ capacitor

Claims (10)

A pixel structure includes: a first transistor having a first gate, a first end, and a second end, and transmitting a data signal to a first node during a data writing; a second transistor having a second gate, a third end, and a fourth end, the second gate is coupled to a second node, and the third end is coupled to a third node, The fourth end is coupled to a fourth node; a switch unit is connected in series with the light emitting element and the second transistor between a first operating voltage and a second operating voltage; and a compensation unit coupled to the first And between the third node; wherein during a compensation period, the voltage of the second node is equal to the voltage of the third node, and during a reset period, the voltage of the third node is equal to a fixed voltage, and the reset period Located between the compensation period and the data writing period. The pixel structure of claim 1, further comprising: a first setting unit, configured to make the voltage of the first node equal to a reference voltage. The pixel structure of claim 1, further comprising: a coupling unit, comprising a first capacitor, the first capacitor being coupled between the first and second nodes. The pixel structure of claim 3, wherein the coupling unit further comprises a second capacitor coupled between the first and fourth nodes. For example, the pixel structure described in claim 1 of the patent scope includes: a second setting unit is configured to make the voltage of the fourth node equal to the reference voltage. The pixel structure of claim 1, wherein: the first gate receives a scan signal, the first end receives the data signal, and the second end is coupled to the first node; the compensation unit is Is a third transistor, the third transistor has a third gate, a fifth end, and a sixth end, the third gate receives a first control signal, and the fifth end is coupled to the third a node, the sixth end is coupled to the second node; the switch unit is a fourth transistor, the fourth transistor has a fourth gate, a seventh end, and an eighth end, the fourth gate Receiving a second control signal, the seventh end receiving the first operating voltage, the eighth end is coupled to the third node; the first setting unit is a fifth transistor, and the fifth transistor has a a fifth gate, a ninth terminal, and a tenth terminal, the fifth gate receives a third control signal or the first control signal, the ninth terminal receives the reference voltage, and the tenth end is coupled to the a first node; the second setting unit is a sixth transistor, and the sixth transistor has a sixth gate The eighth gate receives the third control signal or the first control signal, the eleventh end receives the reference voltage, and the twelfth end is coupled to the The fourth node. The pixel structure of claim 6, wherein the fourth transistor is turned on during the initial period, and the first, second, and third transistors are not turned on; during the compensation, the second And the third transistor is turned on, and the first and fourth transistors are not turned on; during the resetting, the fourth transistor is turned on, and the first, The second and third transistors are non-conductive; during the writing of the data, the first and second transistors are turned on, and the third and fourth transistors are not turned on; during a light-emitting period, the second and fourth The transistor is turned on and the first and third transistors are not turned on. The pixel structure of claim 1, wherein the second transistor is non-conductive during the resetting. The pixel structure of claim 1, wherein the light-emitting element does not emit light during the resetting. A display device comprising: a scan driver for providing at least one scan signal; a data driver for providing at least one data signal; and at least one pixel, the pixel comprising: a first transistor having a first gate, a first end and a second end, and according to the scan signal, transmitting the data signal to a first node during a data writing; a light emitting element; a second transistor having a second gate a third end and a fourth end, the second end is coupled to a second node, the third end is coupled to a third node, the fourth end is coupled to a fourth node; a switch unit, and The light-emitting element and the second transistor are connected in series between a first operating voltage and a second operating voltage; and a compensation unit coupled between the second and third nodes; During a compensation period, the voltage of the second node is equal to the voltage of the third node. During a reset period, the voltage of the third node is equal to a fixed voltage, and the reset period is located during the compensation period and the data is written. Between the periods.