CN111320133B - Chip separation method and wafer - Google Patents
Chip separation method and wafer Download PDFInfo
- Publication number
- CN111320133B CN111320133B CN202010122897.0A CN202010122897A CN111320133B CN 111320133 B CN111320133 B CN 111320133B CN 202010122897 A CN202010122897 A CN 202010122897A CN 111320133 B CN111320133 B CN 111320133B
- Authority
- CN
- China
- Prior art keywords
- phase medium
- chip
- solid phase
- array substrate
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00865—Multistep processes for the separation of wafers into individual elements
- B81C1/00904—Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
- B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
- B01L3/50—Containers for the purpose of retaining a material to be analysed, e.g. test tubes
- B01L3/502—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures
- B01L3/5027—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip
Landscapes
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Engineering & Computer Science (AREA)
- Dispersion Chemistry (AREA)
- Analytical Chemistry (AREA)
- General Health & Medical Sciences (AREA)
- Hematology (AREA)
- Clinical Laboratory Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention relates to a chip separation method and a wafer, wherein the chip separation method comprises the following steps: providing an array substrate, wherein the array substrate comprises a bottom plate and a plurality of chip units with pore canals, and the plurality of chip units are distributed on the bottom plate at intervals; depositing a solid phase medium with a preset thickness on the array substrate, and filling the solid phase medium in the pore channel; bonding a cover plate on the array substrate, wherein the cover plate covers the chip unit to form a wafer; cutting the wafer and forming a plurality of cutting bodies, wherein each cutting body comprises a chip unit; and removing the solid phase medium on the cutting body to form the chip with the pore channel. According to the chip separation method and the wafer provided by the embodiment of the invention, the chip separation method can meet the cutting and forming requirements of the chip, meanwhile, debris can be prevented from entering the pore channel of the chip, and the performance of the chip is ensured.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a chip separation method and a wafer.
Background
The chip such as the micro-fluidic chip is widely applied in the fields of life science, medicine, food, environmental sanitation inspection and the like due to the characteristics of small volume, low cost, convenient carrying, high analysis speed, less samples required by analysis and the like.
The silicon-based micro-fluidic chip is produced by a production process similar to an integrated circuit, large-scale batch production of the micro-fluidic chip is easily realized by utilizing a mature integrated circuit production process, the production efficiency is high, but corresponding disadvantages exist, and the silicon-based micro-fluidic chip mainly shows that chips are easily generated on a wafer by a cutting blade at a high rotating speed when the chips produced in batch are scribed, cooling liquid is driven by the cutting blade to enter a cutting part for cooling and remove the chips generated during cutting in the cutting process, and the inevitable cooling liquid can take the chips to enter the pore channel of the micro-fluidic chip to influence the performance of the chip because the pore channel of the chip is in an open state.
Therefore, a new method for separating chips and a new wafer are needed.
Disclosure of Invention
The embodiment of the invention provides a chip separation method and a wafer, wherein the chip separation method can meet the requirement of chip separation forming, and meanwhile, can prevent chips from entering a pore channel of a chip, and ensures the performance of the chip.
In one aspect, an embodiment of the present invention provides a chip separation method, including:
providing an array substrate, wherein the array substrate comprises a bottom plate and a plurality of chip units with pore canals, and the plurality of chip units are distributed on the bottom plate at intervals; depositing a solid phase medium with a preset thickness on the array substrate, and filling the solid phase medium in the pore channel; bonding a cover plate on the array substrate, wherein the cover plate covers the chip unit to form a wafer; cutting the wafer and forming a plurality of cutting bodies, wherein each cutting body comprises a chip unit; and removing the solid phase medium on the cutting body to form the chip with the pore channel.
According to an aspect of the embodiment of the present invention, the step of removing the solid medium on the cutting body to form the chip having the pore specifically includes: providing an etching solution for a solid phase medium; and placing the cutting body in corrosive liquid for a preset time, and acting the corrosive liquid on the solid phase medium to separate the solid phase medium from the pore channel so as to form the chip with the pore channel.
According to an aspect of the embodiment of the present invention, the step of removing the solid medium on the cutting body to form the chip with the pore channel further includes: heating the etching liquid and/or vibrating the cutting body relative to the etching liquid.
According to one aspect of an embodiment of the present invention, the bottom plate is made of a silicon wafer, the cover plate is made of a silicon wafer, the solid phase medium is gold, and the corrosive liquid includes iodine and potassium iodide; or the solid phase medium is aluminum, and the corrosive liquid comprises a mixed solution of phosphoric acid, nitric acid and acetic acid.
According to one aspect of an embodiment of the present invention, the base plate is made of a silicon wafer, the cover plate is made of a glass plate, the solid phase medium is silicon nitride, and the etching solution includes phosphoric acid; or the solid phase medium is silicon oxide, and the etching solution comprises mixed solution of hydrofluoric acid and ammonium fluoride.
According to an aspect of the embodiments of the present invention, before the step of bonding a cover plate on the array substrate, the cover plate covering the chip units to form the wafer, the chip separation method further includes: and removing at least part of the solid-phase medium by adopting chemical mechanical polishing so that the surface of the bottom plate provided with the chip unit is at least partially exposed to the outer side of the solid-phase medium and forms a bonding region.
According to an aspect of the embodiments of the present invention, before the step of bonding a cover plate on the array substrate, the cover plate covering the chip units to form the wafer, the chip separation method further includes: removing at least part of the solid phase medium by chemical mechanical polishing to make the thickness of the solid phase medium at the outer edge of the surface of the bottom plate provided with the chip unit be
According to one aspect of an embodiment of the invention, the melting point of the solid phase medium is greater than 400 ℃.
In another aspect, an embodiment of the invention provides a wafer, including: the array substrate comprises a bottom plate and a plurality of chip units with pore canals, wherein the chip units are distributed on the bottom plate at intervals; solid phase medium deposited on the array substrate and filling the pore channels; and the cover plate is bonded with the array substrate and covers the chip unit.
According to another aspect of an embodiment of the invention, the solid phase medium is gold, aluminum, silicon oxide or silicon nitride.
According to the chip separation method and the wafer provided by the embodiment of the invention, the solid-phase medium with the preset thickness is directly deposited on the array substrate, and the solid-phase medium is filled in the pore channels of the chip unit, so that when the wafer formed by bonding the array substrate and the cover plate is cut into a plurality of cutting bodies, the solid-phase medium can prevent chips generated in the cutting process of the wafer from entering the pore channels of the chip unit, and the solid-phase medium deposited in each cutting body is removed after the cutting is finished, so that the molding requirement of the chip with the pore channels can be met, and the molded chip has better performance.
Drawings
Features, advantages and technical effects of exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a schematic flow chart of a chip separation method according to an embodiment of the present invention;
FIG. 2 is an exploded view of a wafer according to an embodiment of the present invention;
FIG. 3 is a flow chart of a chip detachment method according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of the array substrate and the solid phase medium after the solid phase medium is removed in the chip separation method according to the embodiment of the invention;
FIG. 5 is a flow chart illustrating a chip detachment method according to another embodiment of the present invention;
fig. 6 is a flow chart illustrating a chip detachment method according to still another embodiment of the present invention.
Wherein:
10-an array substrate;
11-a base plate; 111-a carrying surface; 112-outer peripheral surface; 113-a bottom surface; 12-a chip unit;
20-solid phase medium;
30-a cover plate;
x-thickness direction.
In the drawings, like parts are provided with like reference numerals. The figures are not drawn to scale.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present invention; also, the dimensions of some of the structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The terms of orientation appearing in the following description are directions shown in the drawings, and do not limit the method of separating chips and the specific structure of a wafer according to the present invention. In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as either a fixed connection, a removable connection, or an integral connection; can be directly connected or indirectly connected. The specific meaning of the above terms in the present invention can be understood as appropriate to those of ordinary skill in the art.
For a better understanding of the present invention, a separation method for chips and a wafer according to an embodiment of the present invention will be described in detail below with reference to fig. 1 to 6.
Referring to fig. 1 and fig. 2 together, fig. 1 is a schematic flow chart illustrating a chip separation method according to an embodiment of the invention, and fig. 2 is an exploded view illustrating a wafer according to an embodiment of the invention.
The embodiment of the invention provides a chip separation method, which comprises the following steps:
s100, providing an array substrate 10, wherein the array substrate 10 comprises a bottom plate 11 and a plurality of chip units 12 with pore channels, and the plurality of chip units 12 are distributed on the bottom plate 11 at intervals.
S200, depositing the solid-phase medium 20 with a preset thickness on the array substrate 10, and filling the solid-phase medium 20 in the pore channel.
And S300, bonding a cover plate 30 on the array substrate 10, wherein the cover plate 30 covers the chip unit 12 to form a wafer.
S400, cutting the wafer and forming a plurality of cutting bodies, wherein each cutting body comprises a chip unit 12;
and S500, removing the solid phase medium 20 on the cutting body to form the chip with the pore channel.
The chip separation method provided by the embodiment of the invention can meet the cutting and forming requirements of the chip, and meanwhile, can prevent chips from entering the pore channel of the chip, thereby ensuring the performance of the chip.
Alternatively, in step S100, the array substrate 10 may be provided in advance, or may be prefabricated in situ. Alternatively, the bottom plate 11 may be a circular plate, the bottom plate 11 has a bottom surface 113, a bearing surface 111 and an outer circumferential surface 112 surrounding the bottom surface 113, which are oppositely arranged in the thickness direction X of the bottom plate 11, and the plurality of chip units 12 are located on the side of the bearing surface 111. Alternatively, a plurality of chip units 12 may be arranged in rows and columns on the bottom plate 11, and two adjacent chip units 12 are spaced from each other to form a cutting area.
Alternatively, in step S200, the solid-phase medium 20 deposited on the array substrate 10 with a predetermined thickness may specifically be deposited on the side of the carrying surface 111 where the plurality of chip units 12 are located, and the deposited thickness may be set according to the form of the solid-phase medium 20 and the size requirement of the array substrate 10, as long as the solid-phase medium 20 can be filled in the pore channels of each chip unit 12.
In some alternative embodiments, the solid phase medium 20 can cover the carrying surface 111 of the array substrate 10 away from the bottom surface 113 thereof, so as to facilitate the deposition of the solid phase medium 20, and further ensure the filling requirement of the channels.
Alternatively, in step S300, the structural shape of the cover plate 30 may be matched with the structural shape of the base plate 11, and may be a circular plate, and the cover plate 30 and the base plate 11 are stacked on each other in the thickness direction X of the base plate 11 and are connected to each other by bonding to cover the chip units 12.
In some optional examples, in step S400, a plurality of dice may be formed by cutting a spacing region (i.e., a cutting region) between two adjacent chip units 12 such that the chip units 12 are separated from each other. Since the channels of each chip unit 12 are filled with the solid-phase medium 20, when the wafer is diced, the solid-phase medium 20 can prevent debris generated during the dicing process of the wafer from entering the channels of the chip unit 12.
In step S500, after the dicing is completed, the deposited solid medium 20 in each of the diced bodies is removed, so that the molding requirement of the chip with the hole can be met, and the molded chip has better performance. And only the solid phase medium 20 is formed in a deposition mode, so that the operation process is simple and the working hours are saved.
In some optional embodiments, the above embodiments provide a chip separation method, wherein the melting point of the solid medium 20 is greater than or equal to 400 ℃. Adopt above-mentioned numerical range through the melting point of injecing solid phase medium 20, can satisfy the filling effect to the pore promptly, avoid in the piece gets into the pore, simultaneously, can also avoid apron 30 and array base member 10 to lead to the emergence of solid phase medium 20 phase transition problem because of the intensification when the bonding, and then avoid leading to the problem emergence in the pore because of the phase transition.
Referring to fig. 3, fig. 3 is a flow chart illustrating a chip separation method according to another embodiment of the invention.
In some optional embodiments, the chip separation method provided in each of the above embodiments specifically includes, in step S500:
s510, providing an etching solution for the solid phase medium 20;
s520, placing the cutting body in corrosive liquid for a preset time, and acting the corrosive liquid on the solid phase medium 20 to separate the solid phase medium 20 from the pore channel so as to form the chip with the pore channel.
The method of separating the solid-phase medium 20 from the pore channel by utilizing the action of the corrosive liquid and the solid-phase medium 20 has simple operation and can ensure the reliability of the separation effect of the solid-phase medium 20 and the pore channel.
Optionally, the components of the etching solution may be specifically set according to the material of the solid phase medium 20, as long as the reaction with the solid phase medium 20 can be ensured, so that the solid phase medium 20 can be separated from the pore channel.
In some alternative embodiments, the bottom plate 11 may be made of a silicon wafer, and the cover plate 30 may also be made of a silicon wafer, in this case, the solid phase medium 20 may be a metal medium, in some alternative examples, the solid phase medium 20 may be gold, and in step S300, when the array substrate 10 is bonded to the cover plate 30, the gold may be bonded to silicon by forming a gold-silicon eutectic. In step S500, the etching solution corresponding to gold may be a mixed solution of iodine and potassium iodide, as long as the etching solution reacts with the solid phase medium 20 on the cutting body and is separated from the pore channels.
It is understood that the solid medium 20 is not limited to gold, and in some other examples, the solid medium 20 may be aluminum, and in this case, the etching solution may include a mixed solution of phosphoric acid, nitric acid, and acetic acid, with phosphoric acid as a main component. Optionally, the etching solution contains phosphoric acid, nitric acid and acetic acid in a ratio of 16: 1: 3, the corrosion liquid adopts the component proportion, so that the separation effect of aluminum can be further optimized, and the performance of a formed chip is ensured.
It should be understood that when the solid phase medium 20 is a metal medium, the metal medium is not limited to gold and aluminum, but may be other metal media, as long as the requirement of filling the pore channels can be met, and the melting point of the solid phase medium 20 itself is greater than the bonding temperature between the cover plate 30 and the array substrate 10, which is not listed here.
It is understood that the solid medium 20 is not limited to be a metal medium, in some other examples, the solid medium 20 may also be a non-metal medium, in some alternative examples, the solid medium 20 may be silicon oxide, and in this case, the corresponding etching solution may be a mixed solution of hydrofluoric acid and ammonium fluoride.
Of course, in some examples, when the solid phase medium 20 is a non-metal medium, the solid phase medium 20 may also be silicon nitride, and in this case, the etching solution may be a phosphoric acid solution, and may be an 85% phosphoric acid solution, which may also meet the requirement of the solid phase medium 20 for filling the pore channels and the requirement of the solid phase medium 20 for separating the pore channels after wafer dicing.
In some optional embodiments, the step S500 of the method for separating a chip provided in each of the above embodiments may further include a step of heating the etching solution to increase the temperature of the etching solution, thereby increasing the reaction rate of the etching solution and the solid medium 20.
The required temperature of the etching solution can be limited according to the material of the solid phase medium 20 and the components of the etching solution, in some optional examples, taking the solid phase medium 20 as silicon nitride and taking phosphoric acid solution as the etching solution as an example, the etching solution can be heated to any value between 130 ℃ and 150 ℃, including two end values of 130 ℃ and 150 ℃, and the separation rate of the solid phase medium 20 and the pore channel is increased by 1.5 times or more by heating the etching solution.
As an optional implementation manner, in the chip separation method provided in each of the above embodiments, the step S500 further includes a step of vibrating the cutting body in the etching solution, and the separation rate between the solid-phase medium 20 and the pore canal can be further increased by vibrating the cutting body in the etching solution. In some alternative embodiments, the cutting body may be vibrated by ultrasonic waves or the like, so as to meet the requirement of increasing the separation rate of the solid phase medium 20 from the pore channels.
Referring to fig. 4 and 5, fig. 4 is a schematic view illustrating the array substrate 10 and the solid phase medium 20 after the solid phase medium 20 is removed in the chip separation method according to the embodiment of the invention, and fig. 5 is a schematic flow chart illustrating the chip separation method according to another embodiment of the invention.
As an optional implementation manner, in the chip separation method provided in each of the above embodiments, before step S300, the chip separation method further includes step S600:
at least part of the solid medium 20 is removed so that the surface of the base plate 11 on which the chip unit 12 is arranged is at least partially exposed to the outside of the solid medium 20 and forms a bonding region. By exposing at least part of the surface of the bottom plate 11 where the chip units 12 are arranged to the outside of the solid-phase medium 20 and forming the bonding region, the solid-phase medium 20 can be effectively prevented from affecting the bonding when step S300 is executed, and the stability of the bonding connection between the cover plate 30 and the array substrate 10 can be ensured.
For example, when the solid phase medium 20 is aluminum, silicon oxide or silicon nitride, at least a portion of the solid phase medium 20 may be removed to expose at least a portion of the surface of the bottom plate 11 where the chip unit 12 is disposed to the outside of the solid phase medium 20 and form a bonding region to ensure the bonding requirement between the cover plate 30 and the array substrate 10.
In some alternative embodiments, chemical mechanical polishing may be used to remove at least a portion of the solid medium 20, so that the surface of the base plate 11 on which the chip unit 12 is disposed is at least partially exposed to the outside of the solid medium 20 and forms the bonding region. By adopting the chemical mechanical polishing mode, the thickness of the solid phase medium 20 to be removed and the position of the solid phase medium to be removed can be accurately controlled.
Referring to fig. 6, fig. 6 is a flowchart illustrating a chip separation method according to still another embodiment of the present invention, and of course, in some other examples, before step S300, the chip separation method provided in the above embodiment may further include step S700:
removing at least part of the solid phase medium 20 to make the thickness of the solid phase medium 20 at the outer edge of the surface of the bottom plate 11 where the chip unit 12 is arranged correspond to the thickness of the solid phase medium 20
(Eimei) & lten & gt
Any number between (angstroms), including
Two end values, optionally
Any value in between. Because the solid-phase medium 20 made of a part of materials can be bonded with the cover plate 30, for example, gold, before the step S300, it is not necessary to expose at least a part of the surface of the bottom plate 11 on which the chip unit 12 is disposed to the outside of the solid-phase medium 20, and it is only necessary to grind the solid-phase medium to change the thickness of the solid-phase medium, so that the flatness of the solid-phase medium 20 formed after deposition can be changed, which is more beneficial to the implementation of the step S300, and the bonding requirement between the cover plate 30 and the array substrate 10 can be ensured, and at the same time, the bonding difficulty can be effectively reduced. At the same time, the thickness of the solid phase medium 20 is limited to
Any value between the two can ensure the thickness required when the cover plate is bonded, and further ensure the bonding requirement with the cover plateIn the process, the thickness of the solid phase medium is moderate, and material waste is avoided.
Also, in some alternative embodiments, chemical mechanical polishing may be used to remove at least a portion of the solid phase medium 20, so that the thickness of the solid phase medium 20 at the outer edge of the surface of the bottom plate 11 where the chip unit 12 is disposed is equal to the thickness of the solid phase medium 20
Any value in between. By adopting the chemical mechanical polishing mode, the thickness of the solid phase medium 20 to be removed and the position of the solid phase medium to be removed can be accurately controlled.
Therefore, according to the chip separation method provided by the embodiment of the invention, the solid-phase medium 20 with the predetermined thickness is directly deposited on the array substrate 10, and the solid-phase medium 20 is filled in the pore channels, so that when the wafer formed by bonding the array substrate 10 and the cover plate 30 is respectively cut into a plurality of cut bodies, the solid-phase medium 20 can prevent chips generated in the process of cutting the wafer from entering the pore channels of the chip unit 12, and after the cutting is completed, the deposited solid-phase medium 20 in each cut body is removed, so that the molding requirement of the chip with the pore channels can be met, and the molded chip can have better performance.
As an alternative implementation manner, the embodiment of the invention further provides a novel wafer, which includes an array substrate 10, a solid medium 20, and a cover plate 30, where the array substrate 10 includes a bottom plate 11 and a plurality of chip units 12 having vias, and the plurality of chip units 12 are distributed on the bottom plate 11 at intervals. The solid medium 20 is deposited on the array substrate 10 and fills the channels, and the cover plate 30 is bonded to the array substrate 10 and covers the chip unit 12.
Optionally, the structural form of the array substrate 10 and the cover plate 30 is the same as that described above in the separation method of the chip, and thus, the description thereof is not repeated here.
In some alternative embodiments, the solid medium 20 can cover the carrying surface 111 on the side of the bottom surface 113 of the array substrate 10 away from the bottom plate 11, so as to facilitate the deposition of the solid medium 20 and ensure the filling requirement of the channels of each chip unit 12.
In some optional examples, the solid phase medium 20 may be a metal medium, such as gold or aluminum, and in some other examples, the solid phase medium may also be a non-metal medium, such as silicon oxide or silicon nitride, and the above four solid phase media 20 are only used to illustrate several optional embodiments, but not limited thereto, as long as the requirement of filling the via can be met, and the influence on the bonding connection between the array substrate 10 and the cover plate 30 can be avoided, and it can be ensured that the solid phase medium can be removed by a corresponding etching solution after being diced.
Therefore, in the wafer provided by the embodiment of the present invention, the solid-phase medium 20 is deposited in the pore channels of the chip unit 12, so that the wafer is diced and separated, and in the process of forming the chip, the solid-phase medium 20 can effectively prevent the chips generated by cutting from entering the pore channels, thereby ensuring the function of separating the formed chip.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. A method for separating chips, comprising:
providing an array substrate, wherein the array substrate comprises a bottom plate and a plurality of chip units with pore canals, and the chip units are distributed on the bottom plate at intervals;
depositing a solid phase medium with a preset thickness on the array substrate, and filling the solid phase medium in the pore channels;
removing at least part of the solid phase medium, so that the surface of the bottom plate, on which the chip unit is arranged, is at least partially exposed to the outer side of the solid phase medium and a bonding region is formed;
bonding a cover plate on the array substrate, wherein the cover plate covers the chip units to form a wafer;
cutting the wafer and forming a plurality of cutting bodies, wherein each cutting body comprises the chip unit;
and removing the solid phase medium on the cutting body to form the chip with the pore channel.
2. The method for separating chips according to claim 1, wherein the step of removing the solid phase medium on the cutting body to form the chip with the pore channel specifically comprises:
providing the corrosive liquid for the solid phase medium;
and placing the cutting body in the corrosive liquid for a preset time, and acting the corrosive liquid on the solid phase medium to separate the solid phase medium from the pore channel so as to form the chip with the pore channel.
3. The method for separating chips according to claim 2, wherein the step of removing the solid phase medium on the cutting body to form the chip with the pore channel further comprises:
heating the corrosive liquid and/or vibrating the cutting body relative to the corrosive liquid.
4. The method for separating chips according to claim 2, wherein the base plate is made of a silicon wafer;
the cover plate is made of a silicon wafer, the solid phase medium is gold, the corrosive liquid comprises iodine and potassium iodide, or the solid phase medium is aluminum, and the corrosive liquid comprises a mixed solution of phosphoric acid, nitric acid and acetic acid.
5. The method for separating chips according to claim 2, wherein the base plate is made of a silicon wafer, and the cover plate is made of a glass sheet;
the solid phase medium is silicon nitride, and the corrosive liquid comprises phosphoric acid; or, the solid phase medium is silicon oxide, and the etching solution comprises a mixed solution of hydrofluoric acid and ammonium fluoride.
6. The method for separating chips according to any one of claims 1 to 5, wherein a cover plate is bonded to the array substrate, the cover plate covering the chip units to form a wafer, and the method for separating chips further comprises:
and removing at least part of the solid-phase medium by adopting chemical mechanical polishing so that the surface of the bottom plate, on which the chip unit is arranged, is at least partially exposed to the outer side of the solid-phase medium and a bonding region is formed.
7. The method for separating chips according to any one of claims 1 to 5, wherein a cover plate is bonded to the array substrate, the cover plate covering the chip units to form a wafer, and the method for separating chips further comprises:
removing at least part of the solid phase medium by adopting chemical mechanical polishing so as to enable the thickness of the outer edge of the surface of the bottom plate, which is provided with the chip unit, corresponding to the solid phase medium to be equal to
8. The method for separating chips according to any one of claims 1 to 5, wherein the melting point of the solid phase medium is more than 400 ℃.
9. A wafer formed in a method of separating chips as claimed in any one of claims 1 to 8, comprising:
the array substrate comprises a bottom plate and a plurality of chip units with pore canals, wherein the chip units are distributed on the bottom plate at intervals, and an interval area between every two adjacent chip units is a cutting area;
solid phase medium deposited on the array substrate and filling the pore channels;
and the cover plate is bonded with the array substrate and covers the chip unit.
10. The wafer of claim 9, wherein the solid phase medium is gold, aluminum, silicon oxide, or silicon nitride.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010122897.0A CN111320133B (en) | 2020-02-27 | 2020-02-27 | Chip separation method and wafer |
| PCT/CN2021/078527 WO2021170145A1 (en) | 2020-02-27 | 2021-03-01 | Chip separation method and wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010122897.0A CN111320133B (en) | 2020-02-27 | 2020-02-27 | Chip separation method and wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111320133A CN111320133A (en) | 2020-06-23 |
| CN111320133B true CN111320133B (en) | 2022-03-25 |
Family
ID=71163428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010122897.0A Active CN111320133B (en) | 2020-02-27 | 2020-02-27 | Chip separation method and wafer |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111320133B (en) |
| WO (1) | WO2021170145A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111320133B (en) * | 2020-02-27 | 2022-03-25 | 西人马联合测控（泉州）科技有限公司 | Chip separation method and wafer |
| CN115261451A (en) * | 2022-07-26 | 2022-11-01 | 深圳太古语科技有限公司 | Method for sequencing chip surface chemical treatment and packaging bonding |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11235656A (en) * | 1995-10-25 | 1999-08-31 | Nec Corp | Grinding pad |
| CN101458260A (en) * | 2007-09-28 | 2009-06-17 | 原子能委员会 | Method of manufacturing a microfluid component comprising at least one microchannel filled with nanostructures |
| CN105502280A (en) * | 2014-09-24 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | MEMS device forming method |
| CN109334028A (en) * | 2018-11-28 | 2019-02-15 | 常州工程职业技术学院 | A kind of micro-fluidic chip paster structure and paster technique |
| CN210015846U (en) * | 2019-06-28 | 2020-02-04 | 长鑫存储技术有限公司 | Wafer and semiconductor device |
| CN210110749U (en) * | 2019-06-28 | 2020-02-21 | 长鑫存储技术有限公司 | Wafer and semiconductor device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100763907B1 (en) * | 2005-12-26 | 2007-10-05 | 삼성전자주식회사 | A method of fabricating a microfluidic device and a microfluidic device fabricated by the same |
| US9610543B2 (en) * | 2014-01-31 | 2017-04-04 | Infineon Technologies Ag | Method for simultaneous structuring and chip singulation |
| CN104192791A (en) * | 2014-09-15 | 2014-12-10 | 华东光电集成器件研究所 | Cutting method for MEMS (Micro-electromechanical Systems) wafer |
| CN106391151B (en) * | 2016-08-31 | 2018-11-09 | 清华大学 | It is suitable for the multilayer micro-fluid chip production method of mass production |
| CN107293462A (en) * | 2017-07-12 | 2017-10-24 | 山西省化工研究所（有限公司） | A kind of method that microchannel plate is prepared with polymer carrier |
| CN107731726B (en) * | 2017-11-14 | 2019-12-13 | 山东芯诺电子科技股份有限公司 | Method for cutting back of glass passivated wafer |
| CN109920732B (en) * | 2017-12-12 | 2021-02-12 | 中芯国际集成电路制造(上海)有限公司 | Cutting method of semiconductor packaging device and packaging method of semiconductor device |
| JP2019130552A (en) * | 2018-01-30 | 2019-08-08 | 株式会社ディスコ | Laser processing method |
| CN111320133B (en) * | 2020-02-27 | 2022-03-25 | 西人马联合测控（泉州）科技有限公司 | Chip separation method and wafer |
-
2020
- 2020-02-27 CN CN202010122897.0A patent/CN111320133B/en active Active
-
2021
- 2021-03-01 WO PCT/CN2021/078527 patent/WO2021170145A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11235656A (en) * | 1995-10-25 | 1999-08-31 | Nec Corp | Grinding pad |
| CN101458260A (en) * | 2007-09-28 | 2009-06-17 | 原子能委员会 | Method of manufacturing a microfluid component comprising at least one microchannel filled with nanostructures |
| CN105502280A (en) * | 2014-09-24 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | MEMS device forming method |
| CN109334028A (en) * | 2018-11-28 | 2019-02-15 | 常州工程职业技术学院 | A kind of micro-fluidic chip paster structure and paster technique |
| CN210015846U (en) * | 2019-06-28 | 2020-02-04 | 长鑫存储技术有限公司 | Wafer and semiconductor device |
| CN210110749U (en) * | 2019-06-28 | 2020-02-21 | 长鑫存储技术有限公司 | Wafer and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111320133A (en) | 2020-06-23 |
| WO2021170145A1 (en) | 2021-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111320133B (en) | Chip separation method and wafer | |
| JP4977198B2 (en) | System-in-package platform for electronic microfluidic devices | |
| CN100449789C (en) | Method of manufacturing a micro-electrical-mechanical system | |
| KR101094450B1 (en) | Dicing method using a plasma etching | |
| US9887152B2 (en) | Method for manufacturing semiconductor devices having a metallisation layer | |
| EP0325704A2 (en) | Process for the simultaneous manufacture of a plurality of semiconductor devices from a single wafer | |
| US20100044873A1 (en) | Semiconductor device and method of manufacturing the same | |
| EP1193214A1 (en) | Integrated chemical microreactor, thermally insulated from detection electrodes, and manufacturing method therefor | |
| TW201342494A (en) | Composite wafer for fabrication of semiconductor devices | |
| CN101026366A (en) | Piezoelectric thin film device | |
| CN101752273B (en) | Method of manufacturing semiconductor device | |
| CN110739390A (en) | Temperature compensation type surface acoustic wave filter device and manufacturing method thereof | |
| US7682935B2 (en) | Process of manufacture of ultra thin semiconductor wafers with bonded conductive hard carrier | |
| JP2014039995A (en) | Methods for fabricating mems structures by etching sacrificial features embedded in glass | |
| EP1962333A1 (en) | Semiconductor device manufacturing method | |
| CN111446158B (en) | Metal deposition process after wafer back cutting | |
| CN101026367A (en) | Piezoelectric thin film device | |
| JP2001523046A (en) | Method for thinning a semiconductor wafer with circuits and wafer made by the method | |
| US20060113649A1 (en) | Light transmissive cover, device provided with same and methods for manufacturing them | |
| US8518802B2 (en) | Process for fabricating integrated-circuit chips | |
| KR20110028265A (en) | Method of forming an electronic device including removing a differential etch layer | |
| WO2019122162A1 (en) | Method of producing a thin film functional layer | |
| CN109103080A (en) | Electroded reversed table top ultra thin wafer of one kind and preparation method thereof | |
| CN112466807A (en) | Process method for thinning ultrathin wafer and evaporating metal on back | |
| JP5046875B2 (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |