CN111313873A - Comparator with a comparator circuit - Google Patents
Comparator with a comparator circuit Download PDFInfo
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- CN111313873A CN111313873A CN201911420269.4A CN201911420269A CN111313873A CN 111313873 A CN111313873 A CN 111313873A CN 201911420269 A CN201911420269 A CN 201911420269A CN 111313873 A CN111313873 A CN 111313873A
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- 238000006880 cross-coupling reaction Methods 0.000 claims abstract description 8
- 238000010586 diagram Methods 0.000 description 12
- 238000010295 mobile communication Methods 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 2
- 238000011069 regeneration method Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 208000024172 Cardiovascular disease Diseases 0.000 description 1
- 206010028980 Neoplasm Diseases 0.000 description 1
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- 206010012601 diabetes mellitus Diseases 0.000 description 1
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- 235000006694 eating habits Nutrition 0.000 description 1
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- 230000003907 kidney function Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000012544 monitoring process Methods 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 210000001635 urinary tract Anatomy 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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Abstract
The comparator includes: a first transistor and a second transistor for receiving a first differential input signal and a second differential input signal, respectively; a third transistor coupled to the first transistor and a first output voltage; a fourth transistor coupled to the second transistor and a second output voltage, wherein the third transistor and the fourth transistor are cross-coupled to each other; a fifth transistor coupled to the first transistor and a first node voltage; and a sixth transistor coupled to the second transistor and a second node voltage, wherein the fifth transistor and the sixth transistor are cross-coupled to each other, the first output voltage and the second output voltage are positively fed back through the cross-coupling of the third transistor and the fourth transistor, and the first node voltage and the second node voltage are positively fed back through the cross-coupling of the fifth transistor and the sixth transistor.
Description
Technical Field
The invention relates to a comparator.
Background
Modern people have physiological problems such as disordered daily life and rest, poor eating habits, busy work and exercise carelessness, so that the probability of cardiovascular diseases, diabetes, renal functions and urinary tract problems is increased, and the probability of relative cancer is increased.
The monitoring of physiological information and screening at any time for early treatment is one of the elements pursued in future preventive medicine, and the biosensor has its relative advantages in this point of view to meet clinical needs.
Therefore, besides the requirement of accuracy, the way to obtain results quickly and the development of testing instruments are also one of the targets for the bio-detection.
Disclosure of Invention
According to an embodiment of the present invention, a comparator is provided, including: a first transistor and a second transistor for receiving a first differential input signal and a second differential input signal, respectively; a third transistor coupled to the first transistor and a first output voltage; a fourth transistor coupled to the second transistor and a second output voltage, wherein the third transistor and the fourth transistor are cross-coupled to each other; a fifth transistor coupled to the first transistor and a first node voltage; a sixth transistor coupled to the second transistor and a second node voltage, wherein the fifth transistor and the sixth transistor are cross-coupled to each other; and an impedance circuit coupled to the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the first output voltage, the second output voltage, the first node voltage, and the second node voltage. The first output voltage and the second output voltage are positively fed back through the cross coupling of the third transistor and the fourth transistor. The first node voltage and the second node voltage are positively fed back through the cross coupling of the fifth transistor and the sixth transistor.
In order to better understand the above and other aspects of the present invention, the following detailed description is given with reference to the accompanying drawings.
Drawings
Fig. 1 shows a circuit architecture diagram of a comparator according to an exemplary embodiment of the present invention.
Fig. 2A and 2B are schematic diagrams illustrating an operation of a comparator according to an exemplary embodiment of the invention.
Fig. 3 shows a gain diagram of a comparator according to an exemplary embodiment of the invention.
Fig. 4 shows a signal waveform diagram of a comparator according to an exemplary embodiment of the invention and a signal waveform diagram of a conventional comparator.
Wherein the reference numerals
100: comparator with a comparator circuit
Mb, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12: transistor with a metal gate electrode
Vin and Vip: differential input signal
CK、
Frequency signal
X, Y: output voltage
W, Z: node voltage
VCC, VDD: operating voltage
Vz, Vw, Vx, Vy: voltage of
Detailed Description
The technical terms in the specification refer to the common terms in the technical field, and if the specification explains or defines a part of the terms, the explanation of the part of the terms is based on the explanation or definition in the specification. Various embodiments of the present invention each have one or more technical features. In the present invention, the present invention provides a method for implementing a mobile communication system, which is capable of providing a mobile communication system with a plurality of mobile communication devices.
Fig. 1 shows a circuit architecture diagram of a comparator 100 according to an exemplary embodiment of the invention. The comparator 100 can be applied in an Oversampling Analog-to-digital converter (Oversampling Analog-to-digital converter) of a biosensor. If the biosensor has 2 probes, the two probes are respectively contacted to a reference end (for example, a hand) and a measured end (for example, when the biosensor is used for sensing heartbeat, the measured end probe is contacted to the heart of the subject).
As shown in fig. 1, the comparator 100 includes: transistors Mb, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12.
The transistor Mb is used to provide a bias current (the transistor Mb may also be referred to as a bias source). The transistors M1 and M2 receive differential input signals Vin and Vip, respectively, and may also be referred to as input stages. The transistors M3-M6 are used to provide signal amplification function. The transistors M7-M10 act as impedance circuits. Transistors M11 and M12 are output offset (offset) cancellation stages.
The transistor Mb has: a source coupled to ground; a drain coupled to the sources of transistors M1 and M2; and a gate receiving a clock signal CK.
The transistor M1 has: a source coupled to the drain of transistor Mb; a drain coupled to the sources of transistors M3 and M5; and a gate receiving the differential input signal Vip.
The transistor M2 has: a source coupled to the drain of transistor Mb; a drain coupled to the sources of transistors M4 and M6; and a gate receiving the differential input signal Vin.
The transistor M3 has: a source coupled to the drain of the transistor M1; a drain coupled to the output voltage X and the gate of the transistor M4; and a gate coupled to the output voltage Y.
The transistor M4 has: a source coupled to the drain of the transistor M2; a drain coupled to the output voltage Y and the gate of the transistor M3; and a gate coupled to the output voltage X.
The transistor M5 has: a source coupled to the drain of the transistor M1; a drain coupled to the node voltage W and the gate of the transistor M6; and a gate coupled to the node voltage Z.
The transistor M6 has: a source coupled to the drain of the transistor M2; a drain coupled to the node voltage Z and the gate of the transistor M5; and a gate coupled to the node voltage W.
The transistor M7 has: a source coupled to the output voltage X; a drain coupled to the operating voltage VDD; and a gate coupled to the node voltage W.
The transistor M8 has: a source coupled to the output voltage Y; a drain coupled to the operating voltage VDD; and a gate coupled to the node voltage Z.
The transistor M9 has: a source coupled to the node voltage W; a drain coupled to the operating voltage VCC; and a gate coupled to the node voltage W.
The transistor M10 has: a source coupled to the node voltage Z; a drain coupled to the operating voltage VCC; and a gate coupled to the node voltage Z.
The transistor M11 has: a source coupled to the node voltage Z; a drain coupled to the node voltage W; and a gate for receiving the frequency signal
(which is an inverted signal of the frequency signal CK).
The transistor M12 has: a source coupled to the output voltage Y; a drain coupled to the output voltage X; and a gate for receiving the frequency signal
(which is an inverted signal of the frequency signal CK).
Fig. 2A and 2B are schematic diagrams illustrating an operation of a comparator according to an exemplary embodiment of the invention. Fig. 2A is a schematic diagram illustrating the operation of the comparator according to an exemplary embodiment of the invention when the clock signal CK is logic 1. FIG. 2B is a schematic diagram illustrating the operation of the comparator according to an exemplary embodiment of the invention when the clock signal CK is logic 0.
As shown in fig. 2A, when the clock signal CK is logic 1, the transistor Mb is turned on, and the transistors M11 and M12 are turned off, so that the transistors M1 to M10 of the comparator 100 can perform dynamic comparator output operations, and details thereof are not repeated herein.
As shown in fig. 2B, when the clock signal CK is logic 0, the transistor Mb is turned off, and the transistors M11 and M12 are turned on. Since the transistors M11 and M12 are turned on, the output voltage X is the output voltage Y, and the node voltage W is the node voltage Z VCC. The comparator 100 is in a clear state at this time to cancel the output offset.
Fig. 3 shows a gain diagram of a comparator according to an exemplary embodiment of the invention. In an exemplary embodiment of the invention, the transistors M3, M5, M7 and M9 can be regarded as an inverter, and the transistors M4, M6, M8 and M10 can be regarded as another inverter, the gains of the two inverters are (a0, τ 0), so the gains for the output voltage X and the output voltage Y are G1, wherein the formula is as follows:
that is, when the clock signal CK is 1, the output voltage X and the output voltage Y are positively fed back by the cross-coupling of the transistors M3 and M4.
In addition, in the exemplary embodiment of the invention, when the clock signal CK is equal to 1, the node voltage W and the node voltage Z can be further positively fed back through the cross-coupling of the transistors M5 and M6. That is, in the exemplary embodiment of the present invention, the node voltages W and Z may be applied to (1); and (2) performing positive feedback on the output voltage X and the output voltage Y. This can reduce the regeneration time (regeneration time) caused by the transistors M7-M10. The output voltages X and Y are accelerated, making the post-stage output (not shown) react faster, increasing the operating frequency and increasing the overall circuit bandwidth. In detail, since the impedances of the transistors M9 and M10 are larger, the voltages of the node voltages W and Z are smaller than the voltages of the output voltages X and Y, the first feedback is provided by the transistors M3 and M4, and the second feedback is provided by the transistors M5 and M6 (but the voltage gain of the second feedback is smaller). Thus, by performing the first and second feedbacks simultaneously, the first feedback of the node voltages W and Z increases the response speed of M9 and M10 to the larger impedance in the second feedback, which in turn affects the output voltages X and Y and the operating bandwidth of the overall circuit.
As shown in fig. 3, the gain amplification G of the comparator according to the embodiment of the present invention is G1G 2, wherein G1 gm3 ro7 gm4 ro8, wherein gm3 and gm4 represent transconductance values of the transistors M3 and M4, respectively, ro7 and ro8 represent equivalent resistance values of the transistors M7 and M8, respectively, G2 gm5 ro9 gm6 ro10, wherein gm5 and gm6 represent transconductance values of the transistors M5 and M6, respectively, and ro9 and ro10 represent equivalent resistance values of the transistors M9 and M10, respectively. Therefore, the comparator of the embodiment of the invention can effectively improve the gain and accelerate the comparator to output the comparison result.
Fig. 4 shows a signal waveform diagram of a comparator according to an exemplary embodiment of the invention and a signal waveform diagram of a conventional comparator. In fig. 4, Vw, Vz, Vx, and Vy represent the node voltage W, the node voltage Z, the output voltage X, and the output voltage Y, respectively. As shown in fig. 4, comparing the conventional output voltage X with the output voltage X of the embodiment of the present invention, it can be seen that the output voltage X of the embodiment of the present invention has a faster response.
In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.
Claims (6)
1. A comparator, comprising:
a first transistor and a second transistor for receiving a first differential input signal and a second differential input signal, respectively;
a third transistor coupled to the first transistor and a first output voltage;
a fourth transistor coupled to the second transistor and a second output voltage, wherein the third transistor and the fourth transistor are cross-coupled to each other;
a fifth transistor coupled to the first transistor and a first node voltage;
a sixth transistor coupled to the second transistor and a second node voltage, wherein the fifth transistor and the sixth transistor are cross-coupled to each other; and
an impedance circuit coupled to the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the first output voltage, the second output voltage, the first node voltage, and the second node voltage;
wherein the first output voltage and the second output voltage are positively fed back through the cross coupling of the third transistor and the fourth transistor; and
the first node voltage and the second node voltage are positively fed back through the cross coupling of the fifth transistor and the sixth transistor.
2. The comparator as claimed in claim 1, further comprising a bias source coupled to the first transistor and the second transistor for providing a bias current, the bias source being controlled by a clock signal.
3. The comparator of claim 2, wherein the impedance circuit comprises:
a seventh transistor coupled to the first output voltage, a first operating voltage and the first node voltage;
an eighth transistor coupled to the second output voltage, the first operating voltage and the second node voltage;
a ninth transistor coupled to the first node voltage and a second operating voltage; and
a tenth transistor coupled to the second node voltage and the second operating voltage.
4. The comparator of claim 3, further comprising:
an eleventh transistor coupled to the second node voltage, the first node voltage and an inverted clock signal; and
a twelfth transistor coupled to the second output voltage, the first output voltage and the inverted clock signal.
5. The comparator as claimed in claim 4, wherein when the clock signal is logic 1, the bias voltage source is turned on, the eleventh transistor and the twelfth transistor are turned off, and the first transistor to the tenth transistor of the comparator perform dynamic comparator output.
6. The comparator as claimed in claim 5, wherein when the clock signal is logic 0, the bias source is turned off, the eleventh transistor and the twelfth transistor are turned on, the first output voltage is equal to the second output voltage, the first node voltage is equal to the second node voltage, and the comparator is in a clear state to offset an output offset.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108119417 | 2019-06-05 | ||
| TW108119417A TWI678886B (en) | 2019-06-05 | 2019-06-05 | Comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111313873A true CN111313873A (en) | 2020-06-19 |
| CN111313873B CN111313873B (en) | 2023-03-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911420269.4A Active CN111313873B (en) | 2019-06-05 | 2019-12-31 | Comparator with a comparator circuit |
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| Country | Link |
|---|---|
| CN (1) | CN111313873B (en) |
| TW (1) | TWI678886B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1088004A (en) * | 1992-11-16 | 1994-06-15 | Rca汤姆森许可公司 | Differential comparator circuit |
| US20010043088A1 (en) * | 1999-04-14 | 2001-11-22 | Vaishali Nikhade | Offset comparator and method for forming same |
| CN101252348A (en) * | 2007-02-20 | 2008-08-27 | 尔必达存储器株式会社 | Voltage controlled oscillator |
| CN106803753A (en) * | 2015-11-25 | 2017-06-06 | 德克萨斯仪器股份有限公司 | Ultra low power reduces the clocked comparator of coupling |
| CN107888171A (en) * | 2017-11-16 | 2018-04-06 | 上海北京大学微电子研究院 | A kind of high speed is low to recalcitrate noise dynamic comparer and circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7208980B2 (en) * | 2005-01-21 | 2007-04-24 | Broadcom Corporation | Comparator with offset compensation |
| US7570082B2 (en) * | 2006-08-15 | 2009-08-04 | International Business Machines Corporation | Voltage comparator apparatus and method having improved kickback and jitter characteristics |
| GB2529686A (en) * | 2014-08-29 | 2016-03-02 | Ibm | High-speed comparator for analog-to-digital converter |
| US10491205B2 (en) * | 2017-12-15 | 2019-11-26 | Qualcomm Incorporated | Comparator for globally distributed regulators |
-
2019
- 2019-06-05 TW TW108119417A patent/TWI678886B/en active
- 2019-12-31 CN CN201911420269.4A patent/CN111313873B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1088004A (en) * | 1992-11-16 | 1994-06-15 | Rca汤姆森许可公司 | Differential comparator circuit |
| US20010043088A1 (en) * | 1999-04-14 | 2001-11-22 | Vaishali Nikhade | Offset comparator and method for forming same |
| CN101252348A (en) * | 2007-02-20 | 2008-08-27 | 尔必达存储器株式会社 | Voltage controlled oscillator |
| CN106803753A (en) * | 2015-11-25 | 2017-06-06 | 德克萨斯仪器股份有限公司 | Ultra low power reduces the clocked comparator of coupling |
| CN107888171A (en) * | 2017-11-16 | 2018-04-06 | 上海北京大学微电子研究院 | A kind of high speed is low to recalcitrate noise dynamic comparer and circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111313873B (en) | 2023-03-21 |
| TW202046639A (en) | 2020-12-16 |
| TWI678886B (en) | 2019-12-01 |
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