CN111313873B - Comparator with a comparator circuit - Google Patents

Abstract

The comparator includes: a first transistor and a second transistor for receiving a first differential input signal and a second differential input signal respectively; a third transistor coupled to the first transistor and a first output voltage a fourth transistor coupled to the second transistor and a second output voltage, wherein the third transistor and the fourth transistor are cross-coupled to each other; a fifth transistor coupled to the first transistor and a first transistor a node voltage; a sixth transistor coupled to the second transistor and a second node voltage, wherein the fifth transistor and the sixth transistor are cross-coupled to each other through the intersection of the third transistor and the fourth transistor The coupling performs positive feedback on the first output voltage and the second output voltage, and the positive feedback on the first node voltage and the second node voltage is performed through the cross-coupling of the fifth transistor and the sixth transistor.

Description

Comparators

technical field

The present invention relates to a comparator.

Background technique

Modern urban people's life disorder, poor eating habits, busy work and lack of exercise lead to increased chances of cardiovascular disease, diabetes, kidney function, urinary tract problems, and relatively increased chances of suffering from cancer and other physiological problems.

Monitoring physiological information and screening at any time for early treatment is one of the elements pursued by preventive medicine in the future. From this point of view, biosensors have their relative advantages to meet clinical needs.

Therefore, in addition to the pursuit of accuracy in biological testing requirements, the method of quickly obtaining results and the development of testing instruments have also become one of the goals.

Contents of the invention

According to an embodiment of the present invention, a comparator is proposed, including: a first transistor and a second transistor, respectively used to receive a first differential input signal and a second differential input signal; a third transistor, coupled to to the first transistor and a first output voltage; a fourth transistor coupled to the second transistor and a second output voltage, wherein the third transistor and the fourth transistor are cross-coupled to each other; a fifth transistor , coupled to the first transistor and a first node voltage; a sixth transistor, coupled to the second transistor and a second node voltage, wherein the fifth transistor and the sixth transistor are cross-coupled to each other; and an impedance circuit, coupled to the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the first output voltage, the second output voltage, the first node voltage and the second node voltage . The first output voltage and the second output voltage are positively fed back through the cross-coupling of the third transistor and the fourth transistor. The first node voltage and the second node voltage are positively fed back through the cross-coupling of the fifth transistor and the sixth transistor.

In order to have a better understanding of the above and other aspects of the present invention, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 shows a circuit structure diagram of a comparator according to an exemplary embodiment of the invention.

FIG. 2A and FIG. 2B respectively show schematic diagrams of operations of a comparator according to an exemplary embodiment of the present invention.

FIG. 3 shows a gain diagram of a comparator according to an exemplary embodiment of the invention.

FIG. 4 shows a waveform diagram of a signal waveform of a comparator according to an exemplary embodiment of the present invention and a waveform diagram of a signal waveform of a conventional comparator.

Among them, reference signs

100: Comparator

Mb, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12: Transistors

Vin and Vip: differential input signal

频率信号CK,

frequency signal

X, Y: output voltage

W, Z: node voltage

VCC, VDD: operating voltage

Vz, Vw, Vx, Vy: Voltage

Detailed ways

The technical terms in this specification refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanation or definition of this part of the terms shall prevail. Each embodiment of the present invention has one or more technical features respectively. On the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 1 shows a circuit structure diagram of a comparator 100 according to an exemplary embodiment of the invention. The comparator 100 can be applied in an oversampling analog-to-digital converter of a biosensor. If the biosensor has two probes, which are respectively contacted to the reference end (such as a hand) and the tested end of the subject (for example, when the biosensor is used to sense heartbeat, the probe at the tested end touches the subject's heart).

As shown in FIG. 1 , the comparator 100 includes: transistors Mb, M1 , M2 , M3 , M4 , M5 , M6 , M7 , M8 , M9 , M10 , M11 and M12 .

The transistor Mb is used to provide a bias current (the transistor Mb can also be called a bias source). The transistors M1 and M2 respectively receive differential input signals Vin and Vip, and can also be referred to as an input stage. Transistors M3-M6 are used to provide signal amplification. Transistors M7-M10 act as an impedance circuit. The transistors M11 and M12 are output offset cancellation stages.

The transistor Mb has: a source coupled to the ground; a drain coupled to the sources of the transistors M1 and M2; and a gate receiving a clock signal CK.

The transistor M1 has: a source coupled to the drain of the transistor Mb; a drain coupled to the sources of the transistors M3 and M5; and a gate receiving the differential input signal Vip.

The transistor M2 has: a source coupled to the drain of the transistor Mb; a drain coupled to the sources of the transistors M4 and M6; and a gate receiving the differential input signal Vin.

The transistor M3 has: a source coupled to the drain of the transistor M1; a drain coupled to the output voltage X and the gate of the transistor M4; and a gate coupled to the output voltage Y.

The transistor M4 has: a source coupled to the drain of the transistor M2; a drain coupled to the output voltage Y and the gate of the transistor M3; and a gate coupled to the output voltage X.

The transistor M5 has: a source coupled to the drain of the transistor M1; a drain coupled to the node voltage W and the gate of the transistor M6; and a gate coupled to the node voltage Z.

The transistor M6 has: a source coupled to the drain of the transistor M2; a drain coupled to the node voltage Z and the gate of the transistor M5; and a gate coupled to the node voltage W.

The transistor M7 has: a source coupled to the output voltage X; a drain coupled to the operating voltage VDD; and a gate coupled to the node voltage W.

The transistor M8 has: a source coupled to the output voltage Y; a drain coupled to the operating voltage VDD; and a gate coupled to the node voltage Z.

The transistor M9 has: a source coupled to the node voltage W; a drain coupled to the operating voltage VCC; and a gate coupled to the node voltage W.

The transistor M10 has: a source coupled to the node voltage Z; a drain coupled to the operating voltage VCC; and a gate coupled to the node voltage Z.

(其为频率信号CK的反相信号)。The transistor M11 has: a source, coupled to the node voltage Z; a drain, coupled to the node voltage W; and a gate, receiving the frequency signal

(It is the inversion signal of the frequency signal CK).

(其为频率信号CK的反相信号)。The transistor M12 has: a source, coupled to the output voltage Y; a drain, coupled to the output voltage X; and a gate, receiving the frequency signal

(It is the inversion signal of the frequency signal CK).

FIG. 2A and FIG. 2B respectively show schematic diagrams of operations of a comparator according to an exemplary embodiment of the present invention. FIG. 2A is a schematic diagram showing the operation of the comparator according to an exemplary embodiment of the present invention when the clock signal CK is logic 1. Referring to FIG. FIG. 2B is a schematic diagram showing the operation of the comparator according to an exemplary embodiment of the present invention when the clock signal CK is logic 0. Referring to FIG.

As shown in FIG. 2A, when the frequency signal CK is logic 1, the transistor Mb is turned on, and the transistors M11 and M12 are turned off. At this time, the transistors M1-M10 of the comparator 100 can perform a dynamic comparator output action. The details It is not repeated here.

As shown in FIG. 2B , when the clock signal CK is logic 0, the transistor Mb is turned off, and the transistors M11 and M12 are turned on. Since the transistors M11 and M12 are turned on, the output voltage X=the output voltage Y=the node voltage W=the node voltage Z=VCC. At this time, the comparator 100 is in a clear state to offset the output offset.

FIG. 3 shows a gain diagram of a comparator according to an exemplary embodiment of the invention. In an exemplary embodiment of the present invention, the transistors M3, M5, M7 and M9 can be regarded as an inverter, and the transistors M4, M6, M8 and M10 can be regarded as another inverter, and the two inverters The gain of is (A0, τ0), therefore, the gain of output voltage X and output voltage Y is G1, where the formula is as follows:

That is, when the frequency signal CK=1, the output voltage X and the output voltage Y are positively fed back through the cross-coupling of the transistors M3 and M4.

In addition, in the exemplary embodiment of the present invention, when the frequency signal CK=1, the node voltage W and the node voltage Z can be positively fed back through the cross-coupling of the transistors M5 and M6. That is to say, in the exemplary embodiment of the present invention, positive feedback can be performed on (1) the node voltage W and the node voltage Z; and (2) the output voltage X and the output voltage Y at the same time. In this way, the regeneration time caused by the transistors M7-M10 can be reduced. Speeding up the output voltages X and Y makes the post-stage output (not shown) respond faster, increases the operating frequency, and increases the overall circuit bandwidth. In detail, due to the large impedance of transistors M9 and M10, the voltages of node voltages W and Z are smaller than the voltages of output voltages X and Y, the first feedback is provided by transistors M3 and M4, and the second feedback is provided by transistors M5 and M6. Secondary feedback (but the voltage gain of the second feedback is relatively small). In this way, the first and second feedbacks are performed at the same time, and the first feedback of the node voltage W and Z improves the response speed of M9 and M10, which use larger impedances in the second feedback, and then affects the output voltage X and Y and the operating bandwidth of the overall circuit.

As shown in Figure 3, the gain amplification G of the comparator in the embodiment of the present invention is G=G1*G2, wherein G1=gm3*ro7=gm4*ro8, wherein gm3 and gm4 represent the transconductance values of transistors M3 and M4 respectively , and ro7 and ro8 respectively represent the equivalent resistance values of transistors M7 and M8, G2=gm5*ro9=gm6*ro10, wherein, gm5 and gm6 represent the transconductance values of transistors M5 and M6 respectively, and ro9 and ro10 represent transistors The equivalent resistance value of M9 and M10. Therefore, the comparator in the embodiment of the present invention can effectively increase the gain and speed up the comparator to output the comparison result.

FIG. 4 shows a waveform diagram of a signal waveform of a comparator according to an exemplary embodiment of the present invention and a waveform diagram of a signal waveform of a conventional comparator. In FIG. 4 , Vw, Vz, Vx, and Vy represent node voltage W, node voltage Z, output voltage X, and output voltage Y, respectively. As shown in FIG. 4 , comparing the conventional output voltage X with the output voltage X of the embodiment of the present invention, it can be seen that the output voltage X of the embodiment of the present invention has a faster response.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (4)

1. A comparator, comprising:

a first transistor and a second transistor for receiving a first differential input signal and a second differential input signal, respectively;

a third transistor coupled to the first transistor and a first output voltage;

a fourth transistor coupled to the second transistor and a second output voltage, wherein the third transistor and the fourth transistor are cross-coupled to each other;

a fifth transistor coupled to the first transistor and a first node voltage;

a sixth transistor coupled to the second transistor and a second node voltage, wherein the fifth transistor and the sixth transistor are cross-coupled to each other; and

an impedance circuit coupled to the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the first output voltage, the second output voltage, the first node voltage, and the second node voltage;

wherein the first output voltage and the second output voltage are positively fed back by cross-coupling the third transistor and the fourth transistor; and

positive feedback is carried out on the first node voltage and the second node voltage through the cross coupling of the fifth transistor and the sixth transistor;

the impedance circuit includes:

a seventh transistor coupled to the first output voltage, a first operating voltage and the first node voltage;

an eighth transistor coupled to the second output voltage, the first operating voltage and the second node voltage;

a ninth transistor coupled to the first node voltage and a second operating voltage; and

a tenth transistor coupled to the second node voltage and the second operating voltage;

the comparator further comprises:

an eleventh transistor coupled to the second node voltage, the first node voltage and an inverted clock signal; and

a twelfth transistor coupled to the second output voltage, the first output voltage and the inverted clock signal.

2. The comparator as claimed in claim 1, further comprising a bias source coupled to the first transistor and the second transistor for providing a bias current, the bias source being controlled by a clock signal.

3. The comparator as claimed in claim 2, wherein when the clock signal is logic 1, the bias voltage source is turned on, the eleventh transistor and the twelfth transistor are turned off, and the first transistor to the tenth transistor of the comparator perform dynamic comparator output.

4. The comparator as claimed in claim 3, wherein when the clock signal is logic 0, the bias source is turned off, the eleventh transistor and the twelfth transistor are turned on, the first output voltage is equal to the second output voltage, the first node voltage is equal to the second node voltage, and the comparator is in a clear state to offset an output offset.

Images