CN111312806B - Preparation method and product of single-layer atomic channel fin field effect transistor - Google Patents

Preparation method and product of single-layer atomic channel fin field effect transistor Download PDF

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CN111312806B
CN111312806B CN202010142634.6A CN202010142634A CN111312806B CN 111312806 B CN111312806 B CN 111312806B CN 202010142634 A CN202010142634 A CN 202010142634A CN 111312806 B CN111312806 B CN 111312806B
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layer
substrate
constant material
field effect
dielectric
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CN111312806A (en
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韩拯
陈茂林
孙东明
孙兴丹
王汉文
刘航
董宝娟
刘松
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Institute of Metal Research of CAS
Hunan University
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Hunan University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a fin field effect transistor with a channel material with a monoatomic layer thickness and a preparation method thereof. The fin field effect transistor is characterized in that a vertical step or a vertical array structure is etched on a substrate, a dielectric layer is deposited on the side wall and uniformly coated, then a single-layer transition metal chalcogenide is synthesized at the step, a vertical channel material with the thickness of a monoatomic layer is obtained by adopting an anisotropic etching process, and finally, the fin field effect transistor with the channel material with the thickness of the monoatomic layer is obtained by combining a selective wet etching process and a micro-nano processing process. The fin width of the resulting transistor is only 0.6 nm; based on different thicknesses of the top layer of the substrate, a fin field effect transistor with the height of hundreds of nanometers can be obtained; by preparing the step array, a high-density fin array type FinFET can be obtained and used for constructing a logic device with high integration and low power consumption.

Description

Preparation method and product of single-layer atomic channel fin field effect transistor
Technical Field
The invention belongs to the field of application research of nano artificial composites, micro-nano devices, logic devices and the like, and particularly provides a method for preparing a fin field effect transistor of a channel material with a single atomic layer thickness.
Background
Moore's law states that the number of transistors per unit area in an integrated circuit is multiplied by year, which requires that the size of the transistors be continuously reduced. When the channel width reaches below 10 nanometers, the quantum confinement effect of the traditional planar field effect transistor is remarkable, and further reduction of the size of the traditional planar field effect transistor is hindered. One solution is to use a three-dimensional structure to construct a fin field effect transistor composed of a gate and a dielectric-clad channel material. The contact area between the grid and the channel material is larger, the thickness of the channel material is thinner, the regulation and control capability of the grid is enhanced, and the reduction of the power consumption of the device is facilitated while the size of the device is reduced.
At present, a fin field effect transistor is generally prepared by a top-down method, and a channel material with a fish fin structure is obtained by etching a block body. However, limited by the precision of the photolithography process, the currently realized fin width limit is about 3 nm. Because of the great challenge of further improving the precision of the lithography technology, the goal of further reducing the fin width by relying on the method has great challenge, and the method is not beneficial to the further development of the semiconductor industry.
In recent years, new structured field effect transistors based on two-dimensional layered material systems have been well developed. For example, a single carbon nanotube is used as a gate to regulate a single-layer molybdenum disulfide planar transistor, and the method reduces the gate length of the field effect transistor to the order of 1 nanometer, but the size reduction is only limited to the size reduction of the gate material. Similarly, a field effect transistor using graphene as a source electrode and a drain electrode and using a carbon nanotube as an ultra-narrow channel material has been reported, and the transistor has a greatly reduced size, and the height of the channel carbon nanotube is also reduced correspondingly, which is not beneficial to overcoming a short channel effect. It has also been reported that a few layers of semiconductor molybdenum disulfide or carbon nanotube films are used as channel materials to construct novel fin field effect transistors, and the thickness dimension of the channel materials is in the order of several nanometers. European union patent WO2019053362a1 describes a method of growing different types of monoatomic layer two-dimensional materials on a metal template, and subsequently etching the top material and the metal template to obtain a vertically independent monoatomic layer two-dimensional material for use as a channel material of a fin field effect transistor. However, the patent has obvious limitations, which are firstly strictly limited by the metal substrate, and the vertical step side cannot be obtained by adopting a metal deposition process, and meanwhile, in the process of growing the material at high temperature, the small-sized patterned metal substrate is easy to deform, so that the material grown subsequently cannot be strictly vertical to the substrate; in addition, the variety of materials grown on the metal substrate is limited, and many two-dimensional materials cannot obtain high-quality single-layer single crystals on the metal substrate; in addition, the single-layer two-dimensional material synthesized in the patent is completely exposed and is easily damaged or doped in the subsequent process, so that the intrinsic characteristics of the single-layer two-dimensional material are influenced; finally, this patent does not teach and demonstrate high density finfet arrays, which are difficult to apply in commercial finfet solutions. In principle, the standing two-dimensional layered van der waals material is adopted as the channel material, so that the thickness of the fin field effect transistor is expected to be reduced to the thickness limit of a single atomic layer, and the channel material height equivalent to that of a silicon-based fin gate device can be achieved. However, how to realize vertically independent two-dimensional nanosheets in experiments remains extremely challenging.
Disclosure of Invention
The invention aims to provide a method for preparing a fin field effect transistor of a channel material with a single atomic layer thickness, and the method is proved to have universality by successfully preparing various channel material systems. Meanwhile, the stable and controllable high-density fin field effect transistor array is realized based on the method.
The technical scheme of the invention is as follows:
a method for manufacturing a fin field effect transistor with a channel material with a single atomic layer thickness is characterized in that: etching on a substrate to obtain a vertical step structure or a vertical step array substrate structure, synthesizing a sandwich structure of a high dielectric constant material, a monoatomic layer thickness channel material and the high dielectric constant material on the side wall of the step or the step array, packaging the sandwich structure, a source electrode and a drain electrode, and finally preparing a grid electrode, thereby obtaining the fin field effect transistor with the limited channel width.
The preparation method of the transistor comprises the following specific steps:
(1) etching on a substrate to obtain a vertical step structure or a vertical step array structure;
(2) depositing a high-dielectric-constant material film on the surface of the substrate, then removing the high-dielectric-constant material film in the planar area, and reserving the high-dielectric-constant material film on the side wall of the step in the vertical direction;
(3) depositing a monoatomic layer of a transition metal chalcogenide on a substrate;
(4) defining source and drain electrode regions, fixing the step position of the developed substrate obliquely upwards, and plating metal electrodes on the substrate;
(5) depositing a high dielectric constant material again on the basis of the step (4), then removing the high dielectric constant material and the monoatomic layer transition metal chalcogenide in the planar area, and reserving a sandwich structure of the high dielectric constant material, the monoatomic layer thickness channel material and the high dielectric constant material in the step side wall area;
(6) etching the vertical step side wall or the vertical step array structure, and keeping the original side wall sandwich structure while removing the upper step;
(7) on the basis of the step (6), further depositing a high dielectric constant material film for packaging the top layer of the sandwich structure and simultaneously packaging the source electrode and the drain electrode;
(8) defining a gate electrode area, and depositing a gate electrode.
The invention can isolate different types of single atomic layer layered two-dimensional materials in a vertical mode by utilizing a universal template growth method. Based on the bottom-up preparation process, the vertical self-supporting atomic layer two-dimensional material can be further coated by an insulating dielectric layer and a metal gate electrode to form a fin field effect transistor structure of a channel material with the single atom thickness and the width of a 0.6 nanometer fin. Fin field effect transistors based on a series of monoatomic layer layered two-dimensional materials have been shown to have similar electrical performance. The realization of the physical limit of the fin width in the fin field effect transistor structure opens up new possibility for the application of future nano electronic devices with high integration level and high on-off ratio.
As a preferred technical scheme:
in the step (1), exposure and development are carried out on the surface of the substrate by utilizing an electron beam exposure technology or a photoetching technology to obtain a single separation pattern or a high-density array pattern, then a 200-nanometer metal protective layer (which can be metal nickel, aluminum, copper or gold) is deposited, the material of the top layer of the substrate in a region without metal protection is removed by utilizing inductively coupled plasma etching, a lower insulating layer is kept from being damaged, and finally, based on the type of the metal protective layer, the metal protective layer is dissolved by using corresponding etching solution to obtain a vertical step structure or a vertical step array structure. The vertical step structure can be further evolved into an array structure, and the array height and the array interval are adjustable. Based on the different thicknesses of the substrate top layer material, a finfet of several hundred nanometers in height can be obtained. By preparing the step array, the high-density array type FinFET can be obtained and used for constructing a logic device with high integration and low power consumption.
The initial substrate can be selected from a variety of substrates, either SOI type three-layer substrates or two-layer substrates, where the top layer can be a semiconductor, metal or insulator and the underlying material is an insulator. Most preferably an SOI substrate in which the top silicon has a different chemical stability from the underlying silicon oxide, allowing for high selectivity etching, while being compatible with commercial semiconductor processes.
In the step (2), depositing a high-dielectric-constant material film on the surface of the substrate by using an atomic layer deposition method, then removing the high-dielectric-constant material film in the planar area by using a reactive ion etching technology, and reserving the high-dielectric-constant material film on the side wall of the step in the vertical direction;
in step (5), the high dielectric constant material and the monoatomic layer transition metal chalcogenide are removed in the planar region by using a reactive ion etching technique.
According to the invention, the deposition of uniform and continuous compact films with different thicknesses on a three-dimensional structure can be realized through atomic layer deposition; by utilizing the anisotropic etching characteristic of the reactive ion etching, the material of the plane area can be removed, and the material of the vertical side wall area is reserved.
In the step (3), according to the type requirement of the monoatomic layer transition metal chalcogenide, based on a chemical vapor deposition method, a precursor is spin-coated or spray-coated on a substrate in advance, and then material synthesis is performed under a corresponding atmosphere and temperature, so that deposition and cladding are realized, and different types of monoatomic layer transition metal chalcogenide are deposited on the vertical step or the vertical step array.
The invention carries out chemical vapor deposition on a substrate with a vertical structure, and a precursor solution is required to be spin-coated or sprayed on the substrate in advance, wherein the precursor solution is a compound (such as Na) containing transition metal2MoO4Or Na2WO4) In an aqueous solution having a concentration in the range of 0.0001 to 0.1 mol per liter.
In the step (4), the source electrode pattern and the drain electrode pattern are exposed in the vertical step area by using an electron beam exposure or photoetching process, developed by using a developing solution, and metal electrodes are rotatably evaporated by using an electron beam evaporation process.
In the step (6), based on the type of the step of the top material of the substrate, a corresponding solution is selected to perform selective wet etching on the side wall of the step, and the original side wall sandwich structure is retained while the step is removed.
In the step (7), the single-layer transition metal chalcogenide clamped by the high-dielectric-constant material is encapsulated by the high-dielectric-constant material again, so that the purposes of avoiding the electric leakage of the top area and encapsulating the source electrode and the drain electrode are achieved.
In step (8), there are two schemes for preparing the gate electrode, scheme one: patterning by using an electron beam exposure or photoetching process, and then directly depositing a metal material with the thickness higher than that of the step by adopting electron beam evaporation to obtain a metal grid;
scheme II: depositing a carbon nano tube film with dominant metallicity on a substrate, then patterning by using an electron beam exposure or photoetching process, and finally etching the carbon nano tube film by using an oxygen plasma cleaning machine to obtain the carbon nano tube film grid.
The invention also provides a fin field effect transistor with a channel material with the thickness of the monoatomic layer, which is prepared by the method and is characterized in that: the fin field effect transistor takes a high dielectric constant material as a dielectric layer, a supporting layer and a packaging layer, takes a single-layer transition metal chalcogenide as a channel material, and takes a metal or metallic carbon nanotube as a grid.
The high dielectric constant material is one or more of hafnium oxide, silicon oxide, aluminum oxide, yttrium oxide and boron nitride. The most preferred is hafnium oxide, which is used as a dielectric layer or a packaging layer material, has better chemical stability, higher dielectric constant and good film formation, and can realize packaging and insulating functions even if deposited at 1-2 nm.
The single-layer transition metal chalcogenide compound is molybdenum disulfide, tungsten disulfide, molybdenum diselenide, tungsten ditelluride, molybdenum ditelluride or other two-dimensional transition metal chalcogenide compounds with an X-M-X sandwich structure, wherein X represents a chalcogenide element, and M represents a transition group metal; among the most preferred transition metal chalcogenides is molybdenum disulfide, which has superior chemical stability, higher mobility and on-off ratio than other materials, and thus has the most potential for use in industrial semiconductor devices.
The invention provides a universal method for obtaining different single-layer transition metal chalcogenide compounds by a template growth method, which is obviously improved compared with the prior art, is not limited by the type and the appearance of a growth substrate of a material any more, and can ensure the stability of the substrate in the growth process only by depositing a high dielectric constant material film on the substrate by adopting an atomic layer deposition technology before growing the material; secondly, before the material is etched, the material is packaged by using the high-dielectric-constant material again, so that the material is prevented from being doped and damaged in the subsequent process; finally, the FinFET with the channel material with the intrinsic monoatomic layer thickness and the fin width of only 0.6 nanometer is obtained. The method reduces the fin width of the fin field effect transistor to the limit of 0.6 nanometer atom thickness, and discloses the development direction of a new generation of nanometer electronic devices with low energy consumption and high integration level.
The method of the invention has the advantages that:
1. the template growth method is not limited by the type of the substrate and is more compatible with the commercial semiconductor process;
2. the template growth method is not limited by the morphology of the substrate, and the height of the channel can be effectively controlled by selecting the thickness of the top layer material of the substrate;
3. the template growth method is not limited by the material variety, can realize the synthesis of various transition metal chalcogenide compounds, and enriches the selectivity of the channel material variety;
4. the preparation of the vertical step structure and the etching removal of the plane area are realized by utilizing the selectivity and the anisotropic etching performance of the etching process;
5. utilizing atomic layer deposition to obtain a uniform and compact dielectric layer film which is used as a dielectric layer, a packaging layer and a supporting layer of the fin field effect transistor;
6. preparing a single atomic layer thickness limit fin type field effect transistor with a fin width;
7. preparing a single-layer atomic channel fin field effect array with adjustable density;
8. the fin field effect transistor prepared by the method has strong grid electrode regulation and control capability and good ohmic contact.
Drawings
Fig. 1 shows a comparison of typical dimensions of a single atomic layer of transition metal chalcogenide with etched silicon fins and carbon nanotubes (silicon, single layer of transition metal chalcogenide, carbon nanotubes in order from left to right).
Fig. 2 is a schematic diagram of a single-atom fin-wide finfet.
FIG. 3 is a first schematic diagram of a transistor fabrication process; (a) the structure of the SOI substrate, (b) the structure of the top layer material after patterning and etching, (c) the structure of the substrate after dielectric layer deposition, and (d) the structure of the substrate after dielectric layer planarization and etching.
Fig. 4 is a scanning electron micrograph of silicon steps after etching of the top layer material.
Fig. 5 is a scanning electron micrograph of an array of silicon steps.
FIG. 6 is a second schematic diagram of a transistor fabrication process; (a) a schematic structural diagram of a single-layer transition metal chalcogenide compound growing in a step structure area, (b) a schematic structural diagram of depositing a source electrode and a drain electrode, and (c) a schematic structural diagram of depositing a dielectric layer.
Fig. 7 is a scanning electron microscope image of a single layer of transition metal chalcogenide grown in a step structure region.
FIG. 8 is a third schematic diagram of a transistor fabrication process; (a) a schematic structural diagram after planarization and etching of the dielectric layer and the monoatomic layer transition metal chalcogenide, (b) a schematic structural diagram after removing top silicon by wet etching, (c) a schematic structural diagram after depositing the dielectric layer, and (d) a schematic structural diagram after depositing the gate electrode.
Fig. 9 is a scanning electron micrograph of a typical vertical dielectric layer sandwiched monoatomic layer of a transition metal chalcogenide.
Fig. 10 is a scanning electron micrograph of a typical metal gated single atomic layer thickness channel material finfet.
Fig. 11 is a scanning electron micrograph of a typical finfet with a carbon nanotube film as the monatomic layer thickness channel material of the gate.
FIG. 12 is a cross-sectional schematic view of a typical monolayer atomic channel.
Fig. 13 is a scanning electron micrograph image of a high density fin array.
Fig. 14 is a cross-sectional schematic view of a high density fin array.
Figure 15 is an I-V plot (inset shows the field effect plot for the same device) for a finfet with a channel material of single atomic layer thickness of molybdenum disulfide at different gate voltages.
Reference numerals: 1. the semiconductor device comprises a source electrode, a drain electrode, a dielectric layer, a sandwich structure, a single-atom-layer transition metal chalcogenide, a single-atom-layer channel, a dielectric layer, a silicon oxide layer, a single-layer transition metal chalcogenide layer, a grid electrode and a semiconductor layer, wherein the single-atom-layer transition metal chalcogenide layer is sandwiched between the source electrode and the dielectric layer, the.
Detailed Description
The following examples further illustrate the invention but are not intended to limit the invention thereto.
Example 1
(1) An LOR-7A (3K rpm, heating 190 ℃, 5 minutes) and PMMA950K a7(5K rpm, heating 190 ℃, 5 minutes) are respectively spin-coated on the surface of a top 300 nm silicon SOI substrate (the schematic structural diagram is shown in fig. 3 a), then exposed by an electron beam exposure technique, and respectively developed by a developing solution 1(IPA/DI Water 1/3) for 1 minute, a developing solution 2(CD-26) for 35 seconds, and dried by nitrogen. Then, depositing metal nickel with the thickness of 200 nanometers by electron beam evaporation to serve as a protective layer, removing SOI top-layer silicon material without metal protection by using inductively coupled plasma etching, and finally dissolving the metal nickel by using hydrochloric acid to obtain a vertical step pattern, wherein the structural schematic diagram is shown in FIG. 3b, and the physical enlarged diagram is shown in FIG. 4;
(2) an atomic layer deposition process was used to deposit a uniform and dense 10 nm hafnium oxide film on the substrate surface at 150 c at 0.1 nm per cycle, as shown in fig. 3 c. Then, utilizing a reactive ion etching technology, taking trifluoromethane and oxygen as etching gases, removing hafnium oxide in the plane area, and reserving hafnium oxide on the side wall of the step in the vertical direction, as shown in fig. 3 d;
(3) performing oxygen plasma cleaning (200W for 2 min) on the SOI substrate based on template chemical vapor deposition method to improve the hydrophilicity of the substrate, and spin-coating or spray-coating 0.01 mol Na on the SOI substrate2MoO4Precursor solution (20.6 mg Na)2MoO4Dissolved in 10 ml of deionized water), the substrate was placed in the center of the heat source of a cvd furnace, a crucible loaded with 80 mg of sulfur powder was placed 10 cm in front of the substrate, and 300 seem of argon was introduced into the furnace and allowed to stand for 10 minutes before heating to maintain an inert atmosphere. The furnace was then heated to 850 ℃ over 45 minutes and held at this temperature for 40 minutes (continued flow of 280sccm of argon) to ensure that the precursor was in a molten liquid state. Finally, the sulfur powder was introduced into the heating zone and the reaction was completed within 2 minutes. After growth, the furnace is self-heatingThen cooled to room temperature. The deposition of the monoatomic layer of molybdenum disulfide on the vertical step structure is realized (as shown in FIG. 6 a), and the physical enlargement is shown in FIG. 7;
(4) defining the source electrode area and the drain electrode area by using an electron beam exposure technology, wherein the specific parameters are as in step (1), fixing the step position of the substrate after development in an inclined and upward manner, and performing electron beam evaporation to realize close fit and good contact between the metal electrode and the step structure on the premise of ensuring the thickness of the thinner metal electrode, wherein the structural schematic diagram of the deposited source electrode and the deposited drain electrode is shown in FIG. 6 b;
(5) on the basis of the step (4), depositing hafnium oxide again, as shown in fig. 6c, and removing the hafnium oxide and the monoatomic layer transition metal chalcogenide in the planar region by using a reactive ion etching technique, leaving a sandwich structure of hafnium oxide, monoatomic layer thickness channel material and hafnium oxide in the sidewall region (as shown in fig. 8 a);
(6) performing selective wet etching on the silicon sidewall by using tetramethylammonium hydroxide, and removing the silicon step while retaining the original sidewall sandwich structure, as shown in fig. 8 b;
(7) on the basis of the step (6), further depositing a hafnium oxide film for encapsulating the top layer of the sandwich structure and simultaneously encapsulating the source electrode and the drain electrode (as shown in fig. 8 c), wherein the enlarged view of the object is shown in fig. 9;
(8) patterning by electron beam exposure or lithography, and depositing a metal material with a thickness higher than that of the step by electron beam deposition to obtain a metal gate, as shown in FIG. 8d, FIG. 10, and FIG. 12,
(9) good ohmic contact can be obtained by performing an electrical transport test on the device, as shown in fig. 15.
Example 2
The difference from example 1 is that: the SOI substrate in the step (1) can be replaced by other substrates, such as a substrate with a similar SOI type three-layer structure, and can also be a substrate with a two-layer structure, wherein the top layer can be a semiconductor, a metal or an insulator, and the lower layer is made of an insulator.
A single atomic layer thickness channel material fin field effect transistor can be obtained.
Example 3
The difference from example 1 is that: and (2) the thicknesses of the SOI top layer silicon in the step (1) are different.
FinFET with channel material of single atom layer thickness with different heights (up to micron level) can be obtained.
Example 4
The difference from example 1 is that: the electron beam exposure process in the steps (1), (4) and (8) can be replaced by an ultraviolet lithography process, LOR-3A (3K rpm, heating at 190 ℃ for 5 minutes) and S-1813(4K rpm, heating at 120 ℃ for 2 minutes) are spin-coated on a substrate, then exposure is carried out by using an ultraviolet lithography technology, development is carried out for 35 seconds by using a shadow solution (CD-26) respectively, and drying is carried out by using nitrogen.
A single atomic layer thickness channel material fin field effect transistor can be obtained.
Example 5
The difference from example 1 is that: the metal nickel protective layer in the step (1) can be replaced by metal aluminum, copper or gold as the protective layer, the same protective effect can be realized, and the corresponding etching liquid is also changed correspondingly.
A single atomic layer thickness channel material fin field effect transistor can be obtained.
Example 6
The difference from example 1 is that: the hafnium oxide dielectric layer material in the steps (2), (4) and (6) can be replaced by high-dielectric-constant materials such as silicon oxide, aluminum oxide, yttrium oxide and boron nitride, and the thickness of the dielectric layer can be 1-20 nm.
Fin field effect transistors of different kinds of dielectric layer materials can be obtained.
Example 7
The difference from example 1 is that: the channel material synthesized in the step (3) is other monoatomic layer two-dimensional materials, such as tungsten disulfide, molybdenum diselenide, tungsten ditelluride, molybdenum ditelluride and other two-dimensional transition metal chalcogenide compounds with an X-M-X sandwich structure, wherein X represents a chalcogen element, and M represents a transition group metal.
For example, in the synthesis of tungsten disulfide, 0.03 mol of Na is pre-spin-coated or spray-coated on the SOI substrate2WO4Precursor solution (88.2 mg Na)2WO4Dissolved in 10 ml of deionized water), a mixed gas of 270sccm argon and 30sccm hydrogen is used as a sulfur vapor carrier gas, and other growth conditions are the same as those for synthesizing molybdenum disulfide.
Different types of single atomic layer thickness channel materials of the FinFET can be obtained.
Example 8
The difference from example 1 is that: the growth temperature of the synthesized channel material in the step (3) can be 200-.
A single atomic layer thickness channel material fin field effect transistor can be obtained.
Example 9
The difference from example 1 is that: step (8) is to deposit a carbon nanotube film with dominant metallicity on the substrate, then to pattern the carbon nanotube film by using electron beam exposure or photolithography, and finally to etch the carbon nanotube film by using an oxygen plasma cleaning machine, thereby obtaining a real object enlarged view of the carbon nanotube film gate as shown in fig. 11.
A single atomic layer thickness channel material fin field effect transistor can be obtained.
Example 10
The difference from example 1 is that: the exposed pattern in step (1) is changed into a pattern array with different density, a vertical step array can be obtained after etching the protective metal, the enlarged view of the step array is shown in fig. 5, and the subsequent process is the same as that in embodiment 1. An enlarged view of the high density fin array is shown in fig. 13, and a schematic cross-sectional view of the channel region is shown in fig. 14.
A finfet array with a channel material of monoatomic layer thickness can be obtained.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims (11)

1. A preparation method of a fin field effect transistor with a single-layer atomic channel is characterized by comprising the following specific steps:
(1) etching on a substrate to obtain a vertical step structure or a vertical step array structure;
(2) depositing a high-dielectric-constant material film on the surface of the substrate, then removing the high-dielectric-constant material film in the planar area, and reserving the high-dielectric-constant material film on the side wall of the step in the vertical direction;
(3) depositing a monoatomic layer thickness channel material on a substrate;
(4) defining source and drain electrode regions, fixing the step position of the developed substrate obliquely upwards, and depositing a metal electrode on the substrate;
(5) depositing a high dielectric constant material again on the basis of the step (4), then removing the high dielectric constant material and the monatomic layer thickness channel material in the planar area, and reserving a sandwich structure of the high dielectric constant material, the monatomic layer thickness channel material and the high dielectric constant material in the step side wall area;
(6) etching the vertical step structure or the vertical step array structure, and keeping the original side wall sandwich structure while removing the steps;
(7) on the basis of the step (6), further depositing a high dielectric constant material film for packaging the top layer of the sandwich structure and simultaneously packaging the source electrode and the drain electrode;
(8) defining a gate electrode area, and depositing a gate electrode.
2. A method of manufacturing a transistor according to claim 1, characterized by: the monatomic layer thickness channel material is a monatomic layer transition metal chalcogenide.
3. A method of manufacturing a transistor according to claim 1, characterized by:
in the step (1), exposure and development are carried out on the surface of the substrate by utilizing an electron beam exposure technology or a photoetching technology to obtain a single separation pattern or an array pattern, then a metal protective layer is deposited, materials of the top layer of the substrate in an area without the metal protective layer are removed by utilizing inductively coupled plasma etching, a lower insulating layer is kept from being damaged, and finally, based on the type of the protective layer, corresponding etching liquid is selected to dissolve the metal protective layer to obtain a vertical step structure or a vertical step array structure.
4. A method of manufacturing a transistor according to claim 2, characterized by:
in the step (2), depositing a high-dielectric-constant material film on the surface of the substrate by using an atomic layer deposition method, then removing the high-dielectric-constant material film in the planar area by using a reactive ion etching technology, and reserving the high-dielectric-constant material film on the side wall of the step in the vertical direction;
in step (5), the high dielectric constant material and the monoatomic layer transition metal chalcogenide are removed in the planar region by using a reactive ion etching technique.
5. A method of manufacturing a transistor according to claim 2, characterized by:
in the step (3), according to the type of the monoatomic layer transition metal chalcogenide, based on a chemical vapor deposition method, a corresponding precursor is spin-coated or spray-coated on the substrate in advance, and then material synthesis is performed at a corresponding atmosphere and temperature, so that the monoatomic layer transition metal chalcogenide coated on the vertical step or the vertical step array is deposited.
6. A method of manufacturing a transistor according to claim 1, characterized by:
in the step (4), the source and drain electrode patterns are obtained by exposure and development in the vertical step region by using an electron beam exposure process or a photolithography process, and the metal electrode is deposited by using an electron beam evaporation technique.
7. A method of manufacturing a transistor according to claim 1, characterized by:
in the step (6), based on the type of the step material, a corresponding solution is selected to perform selective wet etching on the step side wall, and the original side wall sandwich structure is retained while the step is removed.
8. A method of manufacturing a transistor according to claim 1, characterized by:
in step (8), there are two schemes for preparing the gate electrode, scheme one: patterning by using an electron beam exposure or photoetching process, and then directly depositing a metal material with the thickness higher than that of the step by adopting electron beam evaporation to obtain a metal grid;
scheme II: depositing a carbon nano tube film with dominant metallicity on a substrate, then patterning by using an electron beam exposure or photoetching process, and finally etching the carbon nano tube film by using an oxygen plasma cleaning machine to obtain the carbon nano tube film grid.
9. A fin field effect transistor with a channel material with a monoatomic layer thickness manufactured by the method of any one of claims 1 to 8, wherein the structure of the fin field effect transistor is as follows: the sandwich structure is surrounded by the grid, a single-layer transition metal chalcogenide is arranged in the sandwich structure, a high-dielectric-constant material is arranged outside the sandwich structure, the high-dielectric-constant material has the functions of a dielectric layer, a supporting layer and a packaging layer, the single-layer transition metal chalcogenide is used as a channel material, and metal or carbon nano tubes are used as the grid.
10. The finfet of claim 9, wherein the channel material has a monoatomic layer thickness, and wherein: the high dielectric constant material is one or more of hafnium oxide, aluminum oxide and yttrium oxide.
11. The finfet of claim 9, wherein the channel material has a monoatomic layer thickness, and wherein: the single-layer transition metal chalcogenide compound is molybdenum disulfide, tungsten disulfide, molybdenum diselenide, tungsten ditelluride, molybdenum ditelluride or other two-dimensional transition metal chalcogenide compounds with an X-M-X sandwich structure, wherein X represents a chalcogenide element, and M represents a transition group metal.
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