CN106549020A - TFT structure and manufacture method based on the carbon-based plate of flexible multi-layered Graphene quantum - Google Patents
TFT structure and manufacture method based on the carbon-based plate of flexible multi-layered Graphene quantum Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Abstract
The invention discloses the TFT structure and manufacture method based on the carbon-based plate of flexible multi-layered Graphene quantum, the TFT structure includes multi-layer graphene quantum carbon base plate, first source electrode, first drain electrode, first grid insulating barrier and first grid, the multi-layer graphene quantum carbon base plate includes the first channel region, and positioned at the multi-layer graphene quantum carbon base plate the corresponding depressed area being separated from each other the first drain region and the first source region, first channel region is located between first drain region and the first source region, first source electrode is filled in first source region, first drain electrode is filled in the first drain region, the first grid insulating barrier is arranged on first channel region, the first grid is arranged on the first grid insulating barrier.The present invention can make carrier mobility higher, can prepare flexibility TFT with large area low cost, realize manufacture flexible electronic device.
Description
【Technical field】
The present invention relates to the TFT structure and manufacture method based on the carbon-based plate of flexible multi-layered Graphene quantum.
【Background technology】
Existing flexible TFT technology includes amorphous silicon hydride TFT, LTPS TFT and metal-oxide TFT.Non-crystalline silicon itself
Mobility it is very low, another is also very sensitive for illumination, and device electrical characteristics occur under applied voltage and illumination condition sternly
Deteriorate again, cause amorphous silicon film transistor technology not adapt to the demand of novel flexible Display Technique.LTPSTFT improves and moves
Shifting rate, possesses higher aperture opening ratio and resolution than the liquid crystal display of amorphous silicon technology using the liquid crystal display of polycrystalline silicon technology
Rate, faster response speed, higher integrated level.But the preparation technology of low temperature polycrystalline silicon is relative complex, technological temperature is high, greatly
Area uniformity has problems.OTFT is less demanding to preparation process condition, and technological temperature is generally not more than 200
DEG C, with flexible electronic technical compatibility, it is a kind of environmentally friendly novel crystal Manifold technology.But organic tft is from large area at present
Commercialization also have larger distance, subject matter be device for the steam and temperature in air has very high sensitivity,
The stability of device needs further to be improved.Oxide thin film transistor possesses good electric property, with higher migration
Rate and current on/off ratio, meet at present jumbo, and the display of high-resolution is required, particularly AMOLED driving application side
Face, with certain prospect.But its carrier mobility needs further to be improved.
Not yet disclosed Chinese invention application 201610701057.3 describes the carbon-based substrate of flexible multi-layered Graphene quantum
Manufacture method, quote it is as follows：
To solve the above problems, the present invention provides a kind of preparation side of the carbon-based two-dimensional semiconductor material of multi-layer graphene quantum
Method, forms the controllable carbon-based two-dimensional semiconductor material of flexible multi-layered Graphene quantum of band gap, and can large area, low cost,
In high volume, reel-to-reel is continuously produced.
The present invention provides a kind of preparation method of multi-layer graphene quantum carbon-based semiconductors material, comprises the steps：S1.
Sinterable polymer is carried out with Kapton (PI films) as raw material, at the first temperature, H, O, N atom is removed, crystallite is formed
The carbon presoma of state；S2. adjust to second temperature, the carbon presoma carries out graphitization, form multi-layer graphene quantum
Carbon-based two-dimensional semiconductor material；Wherein, the doping of nano metal material at least in step S2, is carried out, with described many
Quantum dot is formed in layer graphene.
Preferably, the first temperature is divided into three sections, and the temperature for removing H atom is 900 DEG C -1100 DEG C, removes the temperature of O atom
For 1800 DEG C -2200 DEG C, the temperature for removing N atoms is 2700 DEG C -3300 DEG C.
Further preferably, the first temperature is divided into three sections, and the temperature for removing H atom is 1000 DEG C, removes the temperature of O atom
For 2000 DEG C, the temperature for removing N atoms is 3000 DEG C.
Preferably, second temperature is 2000 DEG C -3500 DEG C.
Further preferably, second temperature is divided into two sections, and first stage temperature is 2000 DEG C -2500 DEG C, second stage temperature
For 2500 DEG C -3500 DEG C.
Preferably, the nano metal material of doping includes calcium (Ca), antimony (Sb), niobium (Nb), yttrium (Y), molybdenum (Mo), silicon
(Si), at least one in arsenic (As), indium (In), hafnium (Hf), gallium (Ga) or at least two alloy；The grain of nano metal material
Footpath is between 2-5nm.
Further preferably, the nano metal material of doping is InAs, forms the multi-layer graphene with InAs quantum dots
The carbon-based two-dimensional semiconductor material of quantum.
The present invention also provides a kind of multi-layer graphene quantum carbon-based two-dimensional semiconductor material, using preparation side as above
Method is prepared.
Beneficial effects of the present invention include：It is carbonized by PI films and graphitization, is prepared with hexaplanar net molecular structure
And the Flexible graphene morphosiss of ordered arrangement, the structural curvature is big, dispersion and the degree of deviation are very little in face.By nanometer gold
The doping of category material, forms quantum dot, realizes the unlatching and regulation and control of band gap.The preparation method can also meet large area, low cost,
In high volume, reel-to-reel is continuously produced.
The carbon-based two-dimensional semiconductor material of multi-layer graphene quantum prepared by the method, can be applied to prepare high-performance
The materials such as field-effect transistor, quantum calculation chip semiconductor.
Hereinafter embodiments of the present invention are elaborated.It is emphasized that what the description below was merely exemplary,
Rather than in order to limit the scope of the present invention and its application.
In one embodiment, the preparation method of the carbon-based two-dimensional semiconductor material of a kind of multi-layer graphene quantum, including such as
Lower step：S1. with PI films as raw material, sinterable polymer is carried out at the first temperature, remove H, O, N atom, form crystallite state
Carbon presoma；S2. adjust to second temperature, the carbon presoma carries out graphitization, form multi-layer graphene quantum carbon-based
Two-dimensional semiconductor material；Wherein, the doping of nano metal material at least in step S2, is carried out, with the multilamellar stone
Quantum dot is formed in black alkene.
In a preferred embodiment, the novel transparent polyamides that PI films are prepared in using prior art CN103289402A
Imines thin film.The PI films carry out mutual hydridization by aromatic diamine and many anhydride of aromatic series, and import the prepared polyamides of methyl
Imines, then carry out cyclodehydration, polycondensation, imidizate and obtain.The thin film alignment is excellent, and the characteristic for having birefringence high,
Carbonization, graphitization when towards thickness swelling diminish, face direction length change amount is also little, thus tend to sexual disorder reduce, line
Orientation is improved, and intensity also improves, and is not likely to produce rupture, can arbitrarily heat, pressurize and without breakage.
PI film Jing sinterable polymers are carbonized, and remove H, O, N atom, make macromolecule heat treatment close to the temperature of single crystals graphite
Degree, C atoms are rearranged, and are formed the big heteroaromatic compounds crystallite state in continuum, are ultimately formed with excellent artificial different
The crystallite state carbon presoma of source graphite-structure, the carbon precursor realize flatness of the response.Carbon precursor Jing graphitizations, carbon knot
Structure is recombinated, and the carbon atom Jing high temperature at crystallite state edge accelerates aggravation motion, crystallite state to be bonded mutually generation macromole, starts hexagonal
Mesh configuration combines and carries out crystallization orientation, and hexagonal carbon stratum reticulare face forms and is grown into, and is changed into two axles from an axle, generates bent
Folding rate is big, dispersion and the degree of deviation are very little in face, it is possible to the Flexible graphene morphosiss of bending.
In a preferred embodiment, sinterable polymer carbonization, the temperature for removing H atom are 900 DEG C -1100 DEG C, and O is former for removing
The temperature of son is 1800 DEG C -2200 DEG C, and the temperature for removing N atoms is 2700 DEG C -3300 DEG C.
In an additional preferred embodiment, sinterable polymer carbonization, the temperature for removing H atom are 1000 DEG C, remove O atom
Temperature be 2000 DEG C, remove N atoms temperature be 3000 DEG C.
In a preferred embodiment, graphited temperature is carried out for 2000 DEG C -3500 DEG C.
In an additional preferred embodiment, carry out graphitization in two stages, first stage reaction temperature is 2000 DEG C -2500
DEG C, second stage reaction temperature is 2500 DEG C -3500 DEG C.
In a further preferred embodiment, graphitization is 1.4 × 10-8-1.8×10-8Mm Hg, more optimizedly exist
1.6×10-8Carry out under mm Hg.
The crystal structure summit G peaks that PI films are constituted Jing after carbonization and graphitization are located at 1582.6cm-1Right side；Secondary peak is
2D two peak structure, positioned at 2719.8cm-1；D peaks 1363cm on the right side of G peaks-1Very little, fault of construction are few.Multi-layer graphene form is
Two dimensional Crystallization, wherein, atom follows the regular orderly plane hexagonal lattice form for being configured of hexagonal configuration, respectively
Carbon atom is that 3 carbon atoms are joined together, and has an electronics to be the shape for moving freely in chemical bond in 4 outer-shell electrons
State, free electron can be moved along crystal lattice, therefore, Graphene has very high conductivity in face direction.
During being carbonized and be graphited, while dopen Nano metal material, forms quantum dot, two-dimentional multilamellar stone is prepared
Black alkene quantum is carbon-based, realizes the unlatching and regulation and control of Graphene band gap.Nano transition metal is with Graphene with covalently bonded, electricity
When sub- cloud is overlapped, with conjugated system (delocalized pi-bond), shared electron logarithm between two atoms, electronics cross a nanometer potential barrier, shape
Into Fermi electron sea, electronics passes through quantum potential barrier into another SQW from a SQW, forms quantum tunneling effect, knot
Structure effect, quantum confined effect.
In a preferred embodiment, during the nano metal material of doping includes Ca, Sb, Nb, Y, Mo, Si, As, In, Hf, Ga
It is at least one or at least two alloy.
In an additional preferred embodiment, the nano metal material of doping is InAs, formation with InAs quantum dots
The carbon-based two-dimensional semiconductor material of multi-layer graphene quantum.
Embodiment 1
In noble gases, the carbonization of PI film Jing sinterable polymers, respectively at 1000 DEG C, 2000 DEG C and 3000 DEG C, removing H,
O, N atom, C atomic rearrangements form carbon presoma；Carbon presoma carries out graphite at 2800 DEG C under inert gas shielding
Change, start traverse net construction, generate high-purity single crystal graphene construction, two-dimentional carbon-coating is hexagonal closs packing, with plane net
Shape molecular ordered arrangement.In carbonization and graphitizing process, adulterate InAs nano metal materials, forms quantum dot, and multilamellar is obtained
The carbon-based two-dimensional semiconductor material of Graphene quantum, quantum dot density are 1 × 1010～3 × 1010cm-2, band gap width is 1.3-
1.4ev。
Embodiment 2
Difference with embodiment 1 is, the mixture of the nano metal material of doping for InAs and Sb, the quantum dot of formation
Density is 1.2 × 1012cm-2.By quantum tunneling effect, regulate and control and Sb elements are added in InAs, form InSbxAs1-xQuantum
Point, during adjustment content x, controllable band gap width.
Comparative example 1
Difference with embodiment one or embodiment two is：PI film Jing sinterable polymers are carbonized, respectively at 500 DEG C, 600 DEG C
With 800 DEG C of removings for carrying out H, O, N atom, it is impossible to form the carbon-based two-dimensional semiconductor material of multi-layer graphene quantum.
【The content of the invention】
In order to overcome the deficiencies in the prior art, the invention provides based on the carbon-based plate of flexible multi-layered Graphene quantum
TFT structure and manufacture method, so that carrier mobility is higher, can prepare flexibility TFT with large area low cost, realize that manufacture is soft
Property electronic device.
A kind of TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum, including multi-layer graphene quantum carbon base plate,
First source electrode, the first drain electrode, first grid insulating barrier and first grid, the multi-layer graphene quantum carbon base plate include the first ditch
Road region and the first drain region of the corresponding depressed area being separated from each other positioned at the multi-layer graphene quantum carbon base plate
With the first source region, first channel region is located between first drain region and the first source region, and described the
One source electrode is filled in first source region, and first drain electrode is filled in the first drain region, the first grid insulation
Layer is arranged on first channel region, and the first grid is arranged on the first grid insulating barrier.
Preferably, also including the second source electrode, the second drain electrode, second grid insulating barrier and second grid, the Multi-layer graphite
Alkene quantum carbon base plate also include the second channel region and positioned at the multi-layer graphene quantum carbon base plate be separated from each other it is right
Answer the second drain region, the second source region and the area of isolation of depressed area；
Second channel region is located between second drain region and the second source region, and second source electrode is filled out
Fill in second source region, second drain electrode is filled in the second drain region, and the second grid insulating barrier is arranged on
On second channel region, the second grid is arranged on the second grid insulating barrier；
The area of isolation both sides form the first TFT structure and the second TFT structure respectively, and first TFT structure includes
First source electrode, the first drain electrode, first grid insulating barrier, first grid and the first channel region, the second TFT structure bag
Include the second source electrode, the second drain electrode, second grid insulating barrier, second grid and the second channel region；
The inwall of the area of isolation is provided with area of isolation insulating barrier.
Preferably, include the gap between area of isolation insulating barrier in the area of isolation.
Preferably, first source electrode also includes extending first source region and being located at the multi-layer graphene amount
Part in the carbon-based plate surface of son, first drain electrode also include extending first drain region and being located at the multilamellar stone
Part in the carbon-based plate surface of black alkene quantum.
Preferably, first source electrode also includes extending first source region and being located at first channel region
Part on surface, first drain electrode also include extending first drain region and being located at the first channel region table
Part on face, the first grid insulating barrier part are located on first channel region, and a part is located at described first
In the first drain electrode on channel region, a part is located on the first source electrode on first channel region.
Preferably, second source electrode also includes extending second source region and being located at the multi-layer graphene amount
Part in the carbon-based plate surface of son, second drain electrode also include extending second drain region and being located at the multilamellar stone
Part in the carbon-based plate surface of black alkene quantum.
Preferably, second source electrode also includes extending second source region and being located at second channel region
Part on surface, second drain electrode also include extending second drain region and being located at the second channel region table
Part on face, the second grid insulating barrier part are located on second channel region, and a part is located at described second
In the second drain electrode on channel region, a part is located on the second source electrode on second channel region.
Present invention also offers a kind of manufacture of the described TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum
Method, comprises the steps：
S1, on the multi-layer graphene quantum carbon base plate etching formed the first drain region of depression for being separated from each other and
First source region；
S2, the first conductive layer is formed on the multi-layer graphene quantum carbon base plate, etch first conductive layer and formed
First drain electrode and the first source electrode；
S3, form insulating barrier on the multi-layer graphene quantum carbon base plate, the first drain electrode and the first source electrode, etching is described
Insulating barrier forms the first grid insulating barrier；
S4, form the first grid on the first grid insulating barrier.
Preferably, in step S1：
On the multi-layer graphene quantum carbon base plate also etching formed the second drain region of the depression being separated from each other, the
Two source regions and area of isolation；Wherein, between second drain region and the second source region it is the second channel region；
In step S2：
Etch first conductive layer and also form the second drain electrode and the second source electrode；Wherein, second source electrode is filled in institute
The second source region is stated, second drain electrode is filled in the second drain region；
In step S3：
Etch the insulating barrier and also form second grid insulating barrier and area of isolation insulating barrier, wherein, the second grid
Insulating barrier is arranged on second channel region, and the area of isolation insulating barrier is located on the inwall of the area of isolation；
In step S4, also include：The second grid is formed on the second grid insulating barrier.
Preferably, include the gap between area of isolation insulating barrier in the area of isolation.
Preferably, first source electrode also includes extending first source region and being located at the multi-layer graphene amount
Part in the carbon-based plate surface of son, first drain electrode also include extending first drain region and being located at the multilamellar stone
Part in the carbon-based plate surface of black alkene quantum.
Preferably, first source electrode also includes extending first source region and being located at first channel region
On part, first drain electrode also includes extending first drain region the portion on first channel region
Point, the first grid insulating barrier part is located on first channel region, and a part is located at first channel region
On first drain electrode on, a part be located at first channel region on the first source electrode on.
Preferably, second source electrode also includes extending second source region and being located at the multi-layer graphene amount
Part in the carbon-based plate surface of son, second drain electrode also include extending second drain region and being located at the multilamellar stone
Part in the carbon-based plate surface of black alkene quantum.
Preferably, second source electrode also includes extending second source region and being located at second channel region
On part, second drain electrode also includes extending second drain region the portion on second channel region
Point, the second grid insulating barrier part is located on second channel region, and a part is located at second channel region
On second drain electrode on, a part be located at second channel region on the second source electrode on.
In certain embodiments, shown according to the XRD diffraction spectra of the multi-layer graphene quantum carbon-based material, the Multi-layer graphite
(there is C- axles (002) crystal face and (004) crystal face be height-oriented in alkene quantum carbon-based material for the graphite thing phase constituent of highly crystalline
Diffraction maximum), with hexagonal (P63/mmc) crystalline texture.(002) direction be interplanar distance between horizontal lattice plane be 0.336nm, unit
Cell parameter is a=b=0.246nm, and c=0.671nm, density d=2.26kg/m3, cell parameter compare kish
(0.334nm) bigger, density quite, belongs to highly crystalline film with kish (2.20-2.28kg/m3)
In certain embodiments, shown according to the x-ray photoelectron power spectrum of the multi-layer graphene quantum carbon-based material, XPS
Analysis shows its be mainly C peaks, also there is a small amount of O peaks, Si peaks, C and Na peaks.The combination of C1s peaks can be 284.6ev, and O1s peaks are combined
Can be 532.3ev；C/O spectral strengths ratio is more than 9.As a result show the Graphene quantum carbon-based material carbon-to-oxygen ratio be 9.5, have
Excellent electric conductivity.
In certain embodiments, Hall effect test can obtain the electrical conductivity of the multi-layer graphene quantum carbon-based material and be
1.2x106S/m, hall mobility reach 830cm2/Vs。
The invention has the beneficial effects as follows：
The present invention can make carrier mobility higher, can prepare flexibility TFT with large area low cost, realize that manufacture is flexible
Electronic device.
【Description of the drawings】
Fig. 1 is the TFT structure schematic diagram based on the carbon-based plate of flexible multi-layered Graphene quantum of an embodiment of the present invention
Fig. 2 is the structural representation of the TFT structure manufacture process based on the carbon-based plate of flexible multi-layered Graphene quantum of Fig. 1
Fig. 3 is the structural representation of the TFT structure manufacture process based on the carbon-based plate of flexible multi-layered Graphene quantum of Fig. 1
Fig. 4 is the structural representation of the TFT structure manufacture process based on the carbon-based plate of flexible multi-layered Graphene quantum of Fig. 1
Fig. 5 is the TFT structure schematic diagram based on the carbon-based plate of flexible multi-layered Graphene quantum of an embodiment of the present invention
【Specific embodiment】
Preferred embodiment to inventing below is described in further detail.
As shown in Fig. 1 to 5, a kind of TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum of embodiment, including
The carbon-based substrate 1 of multi-layer graphene quantum, the first source electrode 10, first drain 9, first grid insulating barrier 13 and first grid 15, with
And second source electrode 8, second drain 7, second grid insulating barrier 11 and second grid 14, the multi-layer graphene quantum carbon base plate bag
Include the first channel region 51, the second channel region 31, and being separated from each other positioned at the multi-layer graphene quantum carbon base plate 1
Correspond to the first drain region 5, the first source region 6, the second drain region 3, the second source region 4 and the isolation area of depressed area
Domain 2, first channel region 51 are located between first drain region 5 and the first source region 6, first source electrode 10
First source region 6 is filled in, first drain electrode 9 is filled in the first drain region 5, the first grid insulating barrier 13
It is arranged on first channel region 51, the first grid 15 is arranged on the first grid insulating barrier 13, described
Two channel regions 31 are located between second drain region 3 and the second source region 4, and second source electrode 8 is filled in described
Second source region 4, second drain electrode 7 are filled in the second drain region 3, and the second grid insulating barrier 11 is arranged on described
On second channel region 13, the second grid 14 is arranged on the second grid insulating barrier 11.
2 both sides of the area of isolation form the first TFT structure and the second TFT structure respectively, and first TFT structure includes
The drain electrode 9, first grid insulating barrier 13 of first source electrode 10, first, first grid 15 and the first channel region 51, described second
TFT structure includes second the 8, second drain electrode 7, second grid insulating barrier 11 of source electrode, second grid 14 and the second channel region 31, institute
The inwall for stating area of isolation 2 is provided with area of isolation insulating barrier 12.
The typical thickness of the carbon-based substrate of flexible multi-layered Graphene quantum 1 is 10-100 microns, by multi-layer graphene quantum carbon
Basic unit's formation stacked on top of one another.The carbon-based substrate 1 of multi-layer graphene quantum is separated into many Graphene islands, Graphene by area of isolation 2
Island is made up of three regions, is channel region corresponding with grid respectively, the source region and drain region outside channel region.
In a preferred embodiment, between including between area of isolation insulating barrier 12 in the area of isolation 2
Gap 21.
In a preferred embodiment, first source electrode 10 also includes extending first source region 6 position
In the part 101 on 1 surface of multi-layer graphene quantum carbon base plate, the part on 51 surface of the first channel region
103rd, the part 102 and above the first source region 6, first drain electrode 9 also include extending first drain electrode
Region 5 and be located at 1 surface of multi-layer graphene quantum carbon base plate on part 93, positioned at 51 surface of the first channel region
On part 91, and the part 92 above the first drain region, 13 part of the first grid insulating barrier is located at institute
State on the surface of the first channel region 51, a part is located on the first drain electrode part 91 on first channel region, one
Divide in the first source electrode portion 103 on first channel region 51.
Similarly, second source electrode 8 also includes extending second source region 4 and being located at the multi-layer graphene
Part on 1 surface of quantum carbon base plate, the part on 31 surface of the second channel region and be located at the second source area
Part above domain 4, second drain electrode 7 also include extending second drain region 3 and being located at the multi-layer graphene
Part on 1 surface of quantum carbon base plate, the part on 31 surface of the second channel region and be located at the second drain region
Part above domain, 14 part of the second grid insulating barrier are located on the surface of second channel region 31, a part
On the second drain electrode part on second channel region 31, a part is located at second on second channel region 31
In source electrode portion.
A kind of manufacture method of the TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum, comprises the steps：
S1, as shown in Fig. 2 on multi-layer graphene quantum carbon base plate 1 etching formed be separated from each other depression first leakage
Polar region domain 5, the first source region 6, the second drain region 3, the second source region 4 and area of isolation 2.For example can using etc. from
Daughter is etched, and in one embodiment, the depth of source region and drain region is 1-1000nm, preferably 50nm, isolation area
2 depth of domain is 10-10000nm, preferably 100nm.
S2, the 10, first drain electrode of the first source electrode of formation the 9, second source electrode 8 and the second drain electrode 7.As shown in figure 3, magnetic can be adopted
Control sputtering method drains on the surface of multi-layer graphene quantum carbon base plate 1 and the first drain region 5, the first source region 6, second
Form conductive film in region 3, the second source region 4, conductive can select metal such as Al, Mo, Cr, Ag, Au etc. or
Person's alloy, it is also possible to select transparent conductive material, it is also possible to from composite conducting material etc..Then, carved using wet method or dry method
Etching technique etches to form first the 10, first drain electrode of source electrode the 9, second source electrode 8 and the second drain electrode 7 to conductive film.
S3, formation first grid insulating barrier 13 and second grid insulating barrier 11.As shown in figure 4, in multi-layer graphene quantum
Form exhausted in the surface of carbon base plate 1 and first source electrode the 8, second drain electrode 7 of the 9, second source electrode of the 10, first drain electrode and area of isolation 2
Edge layer, forming method have ald, sputter coating, chemical vapor deposition, thermal evaporation, spin coating etc., and insulating layer material can be with
From organic layer such as PMMA, PVA etc., inorganic layer such as SiO2、SiNx、Al2O3、HfO、Ta2O3, TiO etc., it would however also be possible to employ it is organic/
Inorganic composite layers.It is preferred that forming monolayer Al using ALD2O3Layer, thickness are preferably 5nm-300nm.Can be using dry etching to exhausted
Edge layer perform etching to be formed first grid insulating barrier 13, second grid insulating barrier 11, and area of isolation 2 inner wall insulation layer
12。
S4, formation first grid 15 and second grid 14, both can form the coplanar knot of top-gated in approximately the same plane
Structure.As shown in figure 5, can using magnetron sputtering method formed conductive film, conductive can select metal such as Al, Mo, Cr,
Ag, Au etc. or alloy, it is also possible to select transparent conductive material, it is also possible to from composite conducting material etc..Using wet method or dry
Method etching technics performs etching to form first grid 15 and second grid 14 to conductive film.
S5, passivation layer are formed, to protect conductive layer.Insulating barrier forming method for passivation has ald, sputtering
Plated film, chemical vapor deposition, thermal evaporation, spin coating etc., insulating layer material can be from organic layer such as PMMA, PVA etc., inorganic layers
SiO2、SiNx、Al2O3、HfO、Ta2O3, TiO etc., it would however also be possible to employ organic/inorganic composite layer.It is preferred that forming monolayer using ALD
Al2O3Layer, thickness are preferably 5nm-300nm.
Above content is with reference to specific preferred implementation further description made for the present invention, it is impossible to assert
The present invention be embodied as be confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of without departing from present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the present invention by
The scope of patent protection that the claims submitted to determine.
Claims (14)
1. a kind of TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum, is characterized in that, including multi-layer graphene quantum
Carbon base plate, the first source electrode, the first drain electrode, first grid insulating barrier and first grid, the multi-layer graphene quantum carbon base plate bag
Include the first of the first channel region and the corresponding depressed area being separated from each other positioned at the multi-layer graphene quantum carbon base plate
Drain region and the first source region, first channel region be located at first drain region and the first source region it
Between, first source electrode is filled in first source region, and described first drains is filled in the first drain region, and described first
Gate insulator is arranged on first channel region, and the first grid is arranged on the first grid insulating barrier.
2. the TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum as claimed in claim 1, is characterized in that,
Also include the second source electrode, the second drain electrode, second grid insulating barrier and second grid, the multi-layer graphene quantum carbon base plate
Also include the second channel region and the corresponding depressed area that is separated from each other positioned at the multi-layer graphene quantum carbon base plate
Second drain region, the second source region and area of isolation；
Second channel region is located between second drain region and the second source region, and second source electrode is filled in
Second source region, second drain electrode are filled in the second drain region, and the second grid insulating barrier is arranged on described
On second channel region, the second grid is arranged on the second grid insulating barrier；
The area of isolation both sides form the first TFT structure and the second TFT structure respectively, and first TFT structure includes described
First source electrode, the first drain electrode, first grid insulating barrier, first grid and the first channel region, second TFT structure include
Two source electrodes, the second drain electrode, second grid insulating barrier, second grid and the second channel region；
The inwall of the area of isolation is provided with area of isolation insulating barrier.
3. the TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum as claimed in claim 1, is characterized in that,
Include the gap between area of isolation insulating barrier in the area of isolation.
4. the TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum as claimed in claim 1, is characterized in that,
First source electrode also includes extending first source region and being located at the multi-layer graphene quantum carbon base plate table
Part on face, first drain electrode also include extending first drain region and being located at the multi-layer graphene quantum carbon
Part on substrate surface.
5. the TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum as claimed in claim 1, is characterized in that,
First source electrode also includes the portion extended first source region and be located on the first channel region surface
Point, first drain electrode also includes the portion extended first drain region and be located on the first channel region surface
Point, the first grid insulating barrier part is located on first channel region, and a part is located at first channel region
On first drain electrode on, a part be located at first channel region on the first source electrode on.
6. the TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum as claimed in claim 2, is characterized in that,
Second source electrode also includes extending second source region and being located at the multi-layer graphene quantum carbon base plate table
Part on face, second drain electrode also include extending second drain region and being located at the multi-layer graphene quantum carbon
Part on substrate surface.
7. the TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum as claimed in claim 2, is characterized in that,
Second source electrode also includes the portion extended second source region and be located on the second channel region surface
Point, second drain electrode also includes the portion extended second drain region and be located on the second channel region surface
Point, the second grid insulating barrier part is located on second channel region, and a part is located at second channel region
On second drain electrode on, a part be located at second channel region on the second source electrode on.
8. a kind of manufacture method of the TFT structure based on the carbon-based plate of flexible multi-layered Graphene quantum as claimed in claim 1,
It is characterized in that, comprise the steps：
S1, on the multi-layer graphene quantum carbon base plate, etching forms first drain region and first of depression being separated from each other
Source region；
S2, the first conductive layer is formed on the multi-layer graphene quantum carbon base plate, etch first conductive layer and form described
First drain electrode and the first source electrode；
S3, form insulating barrier on the multi-layer graphene quantum carbon base plate, the first drain electrode and the first source electrode, etch the insulation
Layer forms the first grid insulating barrier；
S4, form the first grid on the first grid insulating barrier.
9. manufacture method as claimed in claim 8, is characterized in that：
In step S1：
On the multi-layer graphene quantum carbon base plate, also etching forms the second drain region of the depression being separated from each other, the second source
Polar region domain and area of isolation；Wherein, between second drain region and the second source region it is the second channel region；
In step S2：
Etch first conductive layer and also form the second drain electrode and the second source electrode；Wherein, second source electrode is filled in described
Two source regions, second drain electrode are filled in the second drain region；
In step S3：
Etch the insulating barrier and also form second grid insulating barrier and area of isolation insulating barrier, wherein, the second grid insulation
Layer is arranged on second channel region, and the area of isolation insulating barrier is located on the inwall of the area of isolation；
In step S4, also include：The second grid is formed on the second grid insulating barrier.
10. manufacture method as claimed in claim 9, is characterized in that：
Include the gap between area of isolation insulating barrier in the area of isolation.
11. manufacture methods as claimed in claim 8, is characterized in that,
First source electrode also includes extending first source region and being located at the multi-layer graphene quantum carbon base plate table
Part on face, first drain electrode also include extending first drain region and being located at the multi-layer graphene quantum carbon
Part on substrate surface.
12. manufacture methods as claimed in claim 8, is characterized in that,
First source electrode also includes the part extended first source region and be located on first channel region, institute
Stating the first drain electrode also includes extending first drain region the part on first channel region, and described first
A gate insulator part is located on first channel region, and a part is located at the first drain electrode on first channel region
On, a part is located on the first source electrode on first channel region.
13. manufacture methods as claimed in claim 9, is characterized in that,
Second source electrode also includes extending second source region and being located at the multi-layer graphene quantum carbon base plate table
Part on face, second drain electrode also include extending second drain region and being located at the multi-layer graphene quantum carbon
Part on substrate surface.
14. manufacture methods as claimed in claim 9, is characterized in that,
Second source electrode also includes the part extended second source region and be located on second channel region, institute
Stating the second drain electrode also includes extending second drain region the part on second channel region, and described second
A gate insulator part is located on second channel region, and a part is located at the second drain electrode on second channel region
On, a part is located on the second source electrode on second channel region.
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Effective date of registration: 20201020 Address after: 518000 5th floor, danbang science and technology building, Langshan 1st Road, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SHENZHEN DIANBOND TECHNOLOGY Co.,Ltd. Address before: 523808, industrial zone, Songshan Industrial Park, Songshan District, Guangdong, Dongguan Patentee before: Guang Dong Dongbond Technology Co.,Ltd. |
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Effective date of registration: 20220805 Address after: 523000 Songshan Lake Science and Technology Industrial Park, Dongguan City, Guangdong Province Patentee after: GUANG DONG DONGBOND TECHNOLOGY Co.,Ltd. Address before: 5th Floor, Danbang Science and Technology Building, Langshan 1st Road, Nanshan District, Shenzhen, Guangdong 518000 Patentee before: SHENZHEN DIANBOND TECHNOLOGY Co.,Ltd. |
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