CN111312764B

CN111312764B - Display device and method for manufacturing the same

Info

Publication number: CN111312764B
Application number: CN202010101485.9A
Authority: CN
Inventors: 金阳完; 郭源奎
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2014-03-07
Filing date: 2015-02-26
Publication date: 2023-04-11
Anticipated expiration: 2035-02-26
Also published as: CN111312763A; KR20150105596A; KR20210093808A; KR102141209B1; KR102419177B1; KR20200094123A; CN111312764A; KR102281330B1; CN111312763B

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a central region having a display region on a substrate; a peripheral region surrounding the central region; a plurality of pads arranged in one direction in the central region; a plurality of insulation patterns adjacent to the plurality of pads; and a slit between the plurality of insulation patterns in the peripheral region, wherein the slit is formed by removing at least a portion of an insulation material of the plurality of insulation patterns.

Description

Display device and method for manufacturing the same

Cross Reference to Related Applications

This application claims priority and benefit to korean patent application No. 10-2014-0027428, filed 3/7/2014 to the korean intellectual property office, and korean patent application No. 10-2014-0063822, filed 5/27/2014 to the korean intellectual property office, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

One or more embodiments of the present invention relate to a display device and a method of manufacturing the display device.

Background

In the field of display, display devices using a flexible substrate which is light and thin and has excellent impact resistance are being developed. A display device using a flexible substrate can be manufactured by cutting a mother glass so that a plurality of display devices can be manufactured from the mother glass. For example, the substrate for the individual display device may be separated by cutting the display substrate along a cutting line using a press.

However, when the display substrate is cut by physical pressure (e.g., a press), the area around the cut line may have burrs or deformation. As a result of such burrs or deformations, layers on the display substrate may separate or crack, which may cause the lines to break. In addition, when the display substrate is cut, layers on the display substrate around the cutting lines may be separated, and thus reliability of the display device may be degraded.

Therefore, it is attempted to expose the display substrate by removing the layer from the display substrate located around the cutting line. However, when the residual metal film exists in the stepped portion formed by removing the layer located around the cutting line, a short circuit may be generated due to the residual metal film being electrically coupled to the wiring included in the circuit board on which an external circuit is mounted when the circuit board is coupled to the pad formed in the display substrate.

Disclosure of Invention

One or more embodiments of the present invention include a display device using a flexible substrate and a method of manufacturing the display device.

One or more embodiments of the present invention relate to a display device using a flexible substrate and a method of manufacturing the display device.

Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments.

According to one or more embodiments of the present invention, a display device includes: a central region having a display region on a substrate; a peripheral region surrounding the central region; a plurality of pads arranged in one direction in the central region; a plurality of insulation patterns adjacent to the plurality of pads; and a slit between the plurality of insulation patterns in the peripheral region, wherein the slit is formed by removing at least a portion of an insulation material of the plurality of insulation patterns.

The plurality of pads may each include an extension line, and the plurality of insulation patterns may overlap the extension line.

The plurality of insulating patterns may include an inorganic material.

The display device may further include an organic film covering at least one region of the side surfaces and the uppermost surface of the plurality of insulation patterns.

The peripheral region may include a region exposing a top surface of the substrate.

The peripheral region may include a pad peripheral region adjacent to the plurality of pads and include the plurality of insulation patterns and the slits, and the region exposing the top surface of the substrate may be adjacent to the pad peripheral region.

The region exposing the top surface of the substrate may be adjacent to an edge of the substrate.

The edge of the substrate may be defined by a cut line.

At least one inorganic film may be located in a central region of the substrate.

The plurality of insulation patterns may have a shape coupled to the at least one inorganic film.

The plurality of pads may be on the at least one inorganic film.

The at least one inorganic film may include a plurality of layers.

Each of the plurality of insulating patterns may include a plurality of inorganic patterns stacked on one another.

Each of the plurality of insulating patterns may include a first inorganic pattern and a second inorganic pattern on the first inorganic pattern.

The top surface of the first inorganic pattern may be completely covered with the second inorganic pattern.

A top surface of the first inorganic pattern may have an exposed area.

The display device may further include an organic film covering at least side surfaces and a top surface of the second inorganic pattern of the plurality of insulating patterns.

The first inorganic film may be positioned between the plurality of insulating patterns and the substrate.

A groove may be formed in a region where the first inorganic film is removed, such that the groove is formed in a region where the first inorganic film overlaps the slit.

The display device may further include an organic film covering at least side surfaces and a top surface of the plurality of insulating patterns without covering portions of the first inorganic film corresponding to the slits.

The display device may further include in the center region: a buffer film on the substrate; and a plurality of Thin Film Transistors (TFTs) on the buffer film and including an active layer, a gate electrode, a source electrode, and a drain electrode, and at least one insulating film may be adjacent to at least one of the active layer, the gate electrode, the source electrode, and the drain electrode, and the plurality of insulating patterns may be the same material as the at least one insulating film.

The plurality of insulating patterns and the at least one insulating film may be coupled to each other.

The at least one insulating film may include at least one of a buffer film formed on the substrate, a gate insulating layer insulating the gate electrode and the active layer, and an interlayer dielectric film insulating the source electrode and the drain electrode from the gate electrode.

The at least one insulating film may include at least one of a buffer film formed on the substrate, a gate insulating layer insulating the gate electrode and the active layer, and a passivation film formed on the source electrode and the drain electrode.

The display device may further include an organic film covering the plurality of TFTs, wherein the organic film covers at least one region of side surfaces and uppermost surfaces of the plurality of insulating patterns.

The display device may further include: a pixel electrode electrically coupled to at least one of the plurality of TFTs; and a pixel defining film covering a portion of the pixel electrode and defining an emission area, wherein the pixel defining film covers at least one area of side surfaces and uppermost surfaces of the plurality of insulating patterns.

The display device may further include a counter electrode facing the pixel electrode, and an organic emission layer is positioned between the pixel electrode and the counter electrode.

The substrate may comprise a flexible material.

The display device may further include: a dummy insulating pattern spaced apart from the plurality of insulating patterns, wherein the dummy insulating pattern does not correspond to the plurality of pads; and dummy slits between the dummy insulating patterns, wherein a portion of the dummy insulating patterns is removed in the peripheral region to form the dummy slits.

An angle formed by an extension line of the plurality of pads and an edge of the substrate may be less than or greater than 90 ° to make the plurality of pads have an inclined shape, and an angle formed by an extension line of the slit and an edge of the substrate may be less than or greater than 90 ° to make the slit have an inclined shape.

An angle formed by the extension lines of the plurality of pads and the edge of the substrate may be the same as an angle formed by the extension lines of the slits and the edge of the substrate.

The display device may further include a circuit board on which an external circuit is mounted so that an electrical signal is transmitted to the display area, wherein a plurality of wires of the circuit board may be coupled to the plurality of pads.

The plurality of conductive lines of the circuit board may be positioned on the plurality of insulation patterns and may be separated by the slits.

According to some embodiments of the present invention, in a method of manufacturing a display device including a central region having a display region on a substrate and a peripheral region surrounding the central region, the method includes: forming a plurality of pads in one direction in the central region; forming a plurality of insulation patterns corresponding to the plurality of pads in a region of the peripheral region adjacent to the plurality of pads; and forming a gap between the plurality of insulation patterns by removing a portion of the insulation material of the plurality of insulation patterns.

The method may further include forming an inorganic film in a central region of the substrate, and the plurality of insulation patterns may include the inorganic film.

The at least one inorganic film may include a plurality of layers.

The method may further comprise: forming the plurality of insulating patterns spaced apart from each other across the gap by patterning a layer including at least an uppermost layer of the plurality of layers of the inorganic film; and forming the plurality of pads on any one of the plurality of layers of the inorganic film after forming the plurality of insulating patterns.

The method may further include removing a lowermost layer of the plurality of layers including at least the inorganic film in a region corresponding to the gap after forming the plurality of pads.

Drawings

These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a plan view schematically showing a display device according to an embodiment of the present invention;

FIG. 2 is an enlarged plan view of region II of FIG. 1;

FIG. 3 is a cross-sectional view taken along line a-a' of FIG. 2, according to an embodiment of the present invention;

fig. 4 is a plan view schematically showing a display device according to another embodiment of the present invention;

fig. 5 to 14 are sectional views taken along line a-a' of fig. 2 according to other embodiments of the present invention;

fig. 15 and 16 are enlarged plan views of the modified embodiment of fig. 2;

fig. 17 to 25 are sectional views describing a method of manufacturing the display device of fig. 1 based on a line b-b' of fig. 1, according to an embodiment of the present invention;

fig. 26 and 27 are sectional views describing a method of manufacturing the display device of fig. 1 based on a line b-b' of fig. 1, according to another embodiment of the present invention;

fig. 28 to 31 are sectional views describing a method of manufacturing the display device of fig. 1 based on a line b-b' of fig. 1, according to another embodiment of the present invention;

fig. 32 is a plan view schematically showing a display device according to a comparative embodiment;

FIG. 33 is an enlarged plan view of region VII of FIG. 32;

fig. 34 is a plan view schematically showing a display device according to an embodiment of the present invention;

FIG. 35 is an enlarged plan view of region IX of FIG. 34; and

fig. 36 is a sectional view taken along line Q-Q' of fig. 35.

Detailed Description

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, these embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the embodiments are described below only by referring to the drawings to explain aspects of the present specification.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, it can be directly or indirectly formed on the other layer, region or component. That is, for example, intervening layers, regions, or components may be present.

The size of elements in the drawings may be exaggerated for convenience of explanation. In other words, since the sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

In the embodiments described below, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system, and can be understood in the broadest sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

When embodiments may be implemented differently, the particular order of processing may be performed differently than described. For example, two processes described in succession may be executed substantially concurrently or in reverse order from that described.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When an element is referred to as being "at least one of," it modifies that entire column of elements rather than modifying individual elements of that column.

Fig. 1 is a plan view schematically showing a display device 1000 according to an embodiment of the present invention. Fig. 2 is an enlarged plan view of a region II of fig. 1, and fig. 3 is a sectional view taken along line a-a' of fig. 2 according to an embodiment of the present invention.

Referring to fig. 1, a display device 1000 includes a substrate 100 according to some embodiments. The substrate 100 may be formed of any suitable substrate material, for example, the substrate 100 may be formed of glass, metal, or organic material.

In some embodiments, the substrate 100 may be formed of a flexible material such that the substrate 100 may be a flexible substrate that is easily bent, folded, or rolled. For example, substrate 100 may be formed of ultra-thin glass, metal, or plastic. When plastic is used, the substrate 100 may be formed of, for example, polyimide (PI), but the material of the substrate 100 is not limited thereto and may be changed to include any other suitable flexible substrate material.

A plurality of display devices 1000 may be formed on mother glass, and individual display devices 1000 may be obtained by cutting the substrate 100 along the cutting line CL. Fig. 1 shows an individual display device 1000 separated by cutting the substrate 100 along a cutting line CL. Thus, the edge of the substrate 100 is defined by the cutting line CL.

The substrate 100 is divided into a peripheral area PA and a central area CA. The peripheral area PA is an area located around or adjacent to the cutting line CL, and the central area CA is an area located inside the peripheral area PA.

However, the present embodiment is not limited thereto. For example, the cutting line CL may not exist. In other words, one display device 1000 may be formed in one mother glass, in which case the substrate 100 may be one mother glass, and thus may not have the cutting lines CL. At this time, the peripheral area PA is an area adjacent to the edge of the substrate 100, and the central area CA may be an area located inside the peripheral area PA. For ease of illustration, one or more embodiments described below include a cut line CL.

The center area CA includes a display area DA and a non-display area NDA.

The display area DA may include at least one display element, for example, at least one Organic Light Emitting Device (OLED), for displaying an image. In addition, the display area DA may include a plurality of pixels.

The non-display area NDA is positioned around the display area DA. As shown in fig. 1, the non-display area NDA may be formed to surround the display area DA. Although not shown, in some embodiments, the non-display area NDA may be formed adjacent to a plurality of side surfaces of the display area DA. In some embodiments, the non-display area NDA may be formed adjacent to one side surface of the display area.

The non-display area NDA includes at least a pad area PDA.

A driver or a plurality of pads 106a are arranged in the pad area PDA.

In some embodiments, at least one inorganic film may be formed in the central region CA, thereby preventing moisture or impurities from penetrating into the display device 1000 through the substrate 100.

The peripheral area PA is an area located around the cutting line CL and located at the periphery of the substrate 100 along the cutting line CL.

The at least one region of the peripheral region PA includes a region exposing the top surface of the substrate 100 and a pad peripheral region PPA.

First, a region of the peripheral region PA exposing the top surface of the substrate 100 will be described.

As shown in fig. 1, the peripheral area PA may include an area exposing the top surface of the substrate 100 at areas near the upper, left, and right edges of the substrate 100.

When the individual display devices 100 are cut and separated from the mother glass, the region of the peripheral area PA exposing the top surface of the substrate 100 prevents cracks from being diffused through an insulating film (e.g., an inorganic film on the substrate 100).

The width of the region of the peripheral region PA exposing the top surface of the substrate 100 from the cutting line CL to the central region CA may range from about several micrometers to several hundreds of micrometers. For example, the width may range from 40 microns to 500 microns, or from 50 microns to 350 microns.

In some embodiments, the peripheral area PA may not include an area exposing the top surface of the substrate 100. In other words, the peripheral area PA may include only the pad peripheral area PPA described below, and may not expose the top surface of the substrate 100 at an area where the edge of the substrate 100 is attached.

The pad peripheral area PPA of the peripheral area PA will now be described.

The pad peripheral area PPA is an area adjacent to the pad area PDA in the peripheral area.

In some embodiments, the pad peripheral region PPA may be a region overlapping the circuit board 300, assuming that the circuit board 300 (e.g., a Chip On Film (COF)) of fig. 32 mounted with an external circuit is bonded to the pad 106a.

The pad peripheral area PPA is provided at least corresponding to the plurality of pads 106a.

The pad peripheral region PPA includes the insulation pattern IP. The insulation patterns IP are arranged corresponding to the pads 106a and spaced apart from each other across the gap S.

The insulation pattern IP is arranged to overlap with an extension line of the pad 106a. Accordingly, when the wire of the circuit board is coupled to the pad 106a, the wire is disposed on the top surface of the insulation pattern IP, thereby preventing (or substantially preventing) the wire from contacting impurities (e.g., a residual metal film or metal particles) on the substrate 100, thereby preventing (or substantially preventing) a short circuit condition.

In some embodiments, the effect of preventing short circuits may be increased by arranging the extension lines of the pads 106a to be separated by the gap S.

This effect will be described in more detail later with reference to the drawings.

In fig. 2 and 3, the insulation pattern IP located in the pad peripheral region PPA is described in more detail.

Fig. 2 shows a portion of the pad area PDA provided with the pad 106a and a portion of the pad peripheral area PPA adjacent to the pad area PDA. A plurality of pads 106a are formed on the substrate 100.

Here, as described above, in some embodiments, at least one inorganic film may be formed in the central area CA on the substrate 100, and at this time, the inorganic film may be formed in the pad area PDA, or the pad 106a may be formed on the inorganic film of the pad area PDA.

The pads 106a are arranged in one direction while being spaced apart from each other at a predetermined interval. In some embodiments, the pads 106a may be arranged in a width direction (x-axis direction of fig. 2) of each pad 106a.

A plurality of insulation patterns IP are arranged in the pad peripheral region PPA. As described above, in some embodiments, at least one inorganic film may be formed in the central area CA on the substrate 100, and at this time, the plurality of insulation patterns IP may be coupled to the inorganic film of the pad area PDA. However, the present embodiment is not limited thereto, and the insulation pattern IP may be formed separately from the inorganic film formed in the central area CA.

The insulation patterns IP may be arranged in a row in a direction corresponding to the plurality of pads 106a. The insulating pattern IP may be formed of an inorganic material. According to some embodiments described above, when the insulating pattern IP is coupled to the at least one inorganic film formed in the central area CA, the insulating pattern IP protrudes from the pad area PDA toward the pad peripheral area PPA and is respectively disposed at positions corresponding to the plurality of pads 106a. In other words, each insulation pattern IP is located at a position where each pad 106a extends in the length direction (y-axis direction of fig. 2).

The slits S are arranged between adjacent insulation patterns IP, and the insulation patterns IP are spaced apart from each other across the slits S. Here, the slit S may be a narrow and long slit and may have an opening type exposing the top surface of the substrate 100 or an opening type exposing an inorganic film having a top surface lower than that of the insulating pattern IP, according to one or more embodiments to be described later.

Referring to fig. 3, the slit S has an opening type exposing the top surface of the substrate 100. In fig. 3, the insulation patterns IP are spaced apart from each other across the slit S exposing the top surface of the substrate 100.

The insulating pattern IP includes a first inorganic pattern 101P and a second inorganic pattern 102P in order from the substrate 100. The second inorganic pattern 102P has a structure in which a plurality of inorganic pattern layers 103P and 105P are stacked on each other. The insulation pattern IP shown in fig. 3 is only an example, and thus the embodiment is not limited thereto and may include an insulation pattern IP having any structure. For example, the insulation pattern IP may include only one layer, include two layers, or include at least four layers.

Further, as described above, in some embodiments, at least one inorganic film may be formed in the central area CA on the substrate 100, and at this time, the plurality of insulation patterns IP may be coupled to the inorganic film of the pad area PDA. In other words, the first and second

inorganic patterns

101P and 102P sequentially stacked in the insulating pattern IP may be respectively coupled to the inorganic films sequentially formed in the pad area PDA.

In addition, in some embodiments, various inorganic films may be formed in the display area DA of the central area CA. In other words, the plurality of insulation patterns IP may be formed to be coupled to at least one of a buffer film and a gate insulation layer, an interlayer dielectric film, a passivation film, and other various insulation films that may be included in a Thin Film Transistor (TFT) for driving a pixel, which are adjacently formed on the substrate 100.

The first inorganic pattern 101P may be disposed in the central region CA to flatten the top surface of the substrate 100, and may include a pattern of a buffer film functioning as a barrier to prevent (or substantially prevent) moisture or impurities from penetrating through the substrate 100. Further, the second inorganic pattern 102P may be disposed in the central region CA, and may include an inorganic pattern layer 103P of a gate insulating layer for insulating an active layer and a gate electrode of the TFT from each other and an inorganic pattern layer 105P of an interlayer dielectric film for insulating the gate electrode and the source and drain electrodes from each other. Details of which will be described later.

In the embodiment of fig. 3, the insulating pattern IP has a side end surface in which the top surface of the first inorganic pattern 101P is completely covered with the second inorganic pattern 102P. In other words, the side end faces of the first inorganic patterns 101P and the side end faces of the second inorganic patterns 102P may be located on the same line.

However, fig. 3 is only an example and the present embodiment may have various modified examples. For example, the side end faces of the first inorganic patterns 101P and the side end faces of the second inorganic patterns 102P may be located on the same diagonal line. As another embodiment, the side end faces of the first inorganic patterns 101P and the side end faces of the second inorganic patterns 102P may not be located on the same line. In some cases, the width of the first inorganic pattern 101P may be smaller than the width of the second inorganic pattern 102P.

Fig. 4 is a plan view schematically showing a display device 2000 according to another embodiment of the present invention.

The display device 2000 according to the present embodiment includes a peripheral area PA and a central area CA on the substrate 200, wherein the central area CA includes a display area DA and a non-display area NDA, and the peripheral area PA includes at least a pad peripheral area PPA.

For convenience of explanation, differences between the display device 1000 and the display device 2000 will be mainly described.

The pad peripheral region PPA includes an insulation pattern IP and a dummy insulation pattern DIP.

The insulation patterns IP are formed corresponding to the pads 206a and spaced apart from each other across the gap S.

The dummy insulation patterns DIP do not correspond to the pads 206a and are spaced apart from each other across the dummy slits DS.

The insulation pattern IP is arranged to overlap with an extension line of the pad 206 a. Accordingly, when the wire is coupled to the pad 206a, the wire is prevented (or substantially prevented) from contacting impurities or contaminants on the substrate 200, such as a residual metal film or metal particles, thereby preventing or reducing a short circuit condition.

The dummy insulating patterns DIP may cover impurities or particles remaining when various components are formed on the substrate 200, so that defects caused by the impurities may be prevented or substantially prevented. In addition, when the display device 2000 including the substrate 200 is deformed (e.g., bent or folded), the dummy insulating patterns DIP and the dummy slits DS may perform a stress relieving function.

Because other components of the display device 2000 are substantially similar to other components of the display device 1000 described above, some additional details regarding the display device 2000 will not be repeated.

Fig. 5 to 14 are sectional views taken along line a-a' of fig. 2 according to other embodiments of the present invention.

According to the embodiment of fig. 5, the slit S has an opening type exposing at least the top surface of the substrate 100. In the embodiment of fig. 5, the insulation patterns IP are spaced apart from each other across the slit S exposing at least the top surface of the substrate 100.

Meanwhile, as in the embodiment of fig. 3, the insulating pattern IP includes a first inorganic pattern 101P and a second inorganic pattern 102P in order from the substrate 100. As described above, in some embodiments, at least one inorganic film may be formed in the central area CA on the substrate 100, and at this time, the plurality of insulation patterns IP may be coupled to the inorganic film in the pad area PDA. However, the present embodiment is not limited thereto, and the insulating pattern IP may be formed separately from the inorganic film in the central area CA.

The embodiments of forming the first and second

inorganic patterns

101P and 102P have been described above. In other words, the above-described embodiments are applicable to details regarding the connection relationship of the inorganic film in the central area CA.

In addition, the second inorganic pattern 102P may have a structure in which a plurality of inorganic pattern layers 103P and 105P are stacked on each other.

Unlike the embodiment of fig. 3, in the embodiment of fig. 5, the top surface of the first inorganic pattern 101P of the insulating pattern IP is partially exposed. In other words, the side end faces of the first inorganic pattern 101P and the side end faces of the second inorganic pattern 102P are not located on the same line, and the second inorganic pattern 102P covers only a part of the top surface of the first inorganic pattern 101P.

In the embodiment of fig. 5, a residual metal film may remain on an area exposing the top surface of the first inorganic pattern 101P, but a short circuit of the pad unit 106a may be prevented.

Referring to the embodiment of fig. 6, the slit S has an opening type exposing the top surface of the first inorganic film 101. In the embodiment of fig. 6, the insulation patterns IP are spaced apart from each other across the slit S exposing the top surface of the first inorganic film 101.

Meanwhile, the insulating pattern IP includes a second inorganic pattern 102P on the first inorganic film 101. As described above, in some embodiments, at least one inorganic film may be formed in the central area CA on the substrate 100, and at this time, the plurality of insulation patterns IP may be coupled to the inorganic film in the pad area PDA. However, the present embodiment is not limited thereto, and the insulating pattern IP may be formed separately from the inorganic film in the central area CA.

Detailed embodiments of forming the second inorganic pattern 102P have been described above. In other words, the above-described embodiments are applicable to details regarding the coupling relationship of the inorganic film in the central area CA. In addition, the second inorganic pattern 102P may have a structure in which a plurality of inorganic pattern layers 103P and 105P are stacked on each other.

In the embodiment of fig. 6, the first inorganic film 101 is formed in the pad peripheral region PPA and the insulating pattern IP includes only the second inorganic pattern 102P, whereby the operation of patterning the first inorganic film 101 may be omitted, thereby simplifying the process.

Referring to the embodiment of fig. 7, the slit S has an opening type exposing the top surface of the first inorganic film 101. In the embodiment of fig. 7, the insulating patterns IP are spaced apart from each other across the slit S exposing the top surface of the first inorganic film 101.

Meanwhile, the insulating pattern IP includes a second inorganic pattern 102P on the first inorganic film 101. As described above, in some embodiments, at least one inorganic film may be formed in the central area CA on the substrate 100, and at this time, the plurality of insulation patterns IP may be coupled to the inorganic film in the pad area PDA. However, the present embodiment is not limited thereto, and the insulation pattern IP may be formed separately from the inorganic film formed in the central area CA.

Detailed embodiments of forming the second inorganic pattern 102P have been described above. In other words, the above-described embodiments are applicable to details regarding the coupling relationship of the inorganic films in the central area CA. In addition, the second inorganic pattern 102P may have a structure in which a plurality of inorganic pattern layers 103P and 105P are stacked on each other.

In the embodiment of fig. 7, the first inorganic film 101 has grooves (e.g., predetermined grooves) between the second inorganic patterns 102P. The groove (e.g., a predetermined groove) may have any one of various shapes, and as shown in fig. 7, may have a boundary line spaced apart from the second inorganic pattern 102P.

However, the present embodiment is not limited thereto. In other words, as shown in fig. 8, a boundary line of a groove (e.g., a predetermined groove) of the first inorganic film 101 may be coupled to a side surface of the second inorganic pattern 102P.

Alternatively, a groove (e.g., a predetermined groove) may be formed in the first inorganic film 101 in any of other various shapes, for example, a boundary line of the groove (e.g., a predetermined groove) of the first inorganic film 101 may be formed to cross a side surface of the second inorganic pattern 102P.

In the embodiment of fig. 7 and 8, the top surface of the first inorganic film 101 provided with the slit S is partially removed. Therefore, in one region (e.g., a predetermined region), the thickness of the first inorganic film 101 corresponding to the slit S is thinner than the thickness of the first inorganic film 101 corresponding to the insulating pattern IP.

Compared to the embodiments of fig. 3 and 5 to 8, the embodiments according to fig. 9 to 14 further include an organic film 107P for covering the insulating pattern IP.

Referring to fig. 9, an organic film 107P covering the top and side surfaces of the insulating pattern IP is further included, as compared to the embodiment of fig. 3, and referring to fig. 10, an organic film 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP is further included, as compared to the embodiment of fig. 5. Referring to fig. 11, in comparison with the embodiment of fig. 5, an organic film 107P covering top and side surfaces of the first and second

inorganic patterns

101P and 102P included in the insulating pattern IP is further included.

Referring to fig. 12, in comparison with the embodiment of fig. 6, an organic film 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP is further included. Referring to fig. 13, in comparison with the embodiment of fig. 7, an organic film 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP is further included.

Referring to fig. 14, in comparison with the embodiment of fig. 8, an organic film 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP is further included.

In some embodiments, the organic film 107P may be formed to be coupled to at least one organic film included in the central region CA. For example, the organic film 107P may be located in the central area CA to cover the TFT, and may be coupled to a passivation film that flattens unevenness caused by the TFT. According to another embodiment, the organic film 107P may be coupled to a pixel defining film for defining an emission region by covering a portion of a pixel electrode on the passivation film. In other words, when the passivation film or the pixel defining film is formed in the central region CA, the organic films 107P may be formed together so as not to have to perform additional processing.

According to the embodiments of fig. 9 to 14, even when a residual metal film remains on the side surface of the second inorganic pattern 102P, the organic film 107P covers the residual metal film, whereby short circuits generated by the residual metal film can be prevented.

Fig. 15 and 16 are enlarged plan views of the modified embodiment of fig. 2. For convenience of explanation, only the differences from the above-described embodiments are mainly described.

Referring to fig. 15, the plurality of pads 106' a have an inclined shape. For example, an angle θ formed by an extension line of the pad 106 ₁ May be less than 90. Further, an angle θ formed by a boundary line of the slit S '(e.g., a center line of the slit S') and an edge of the substrate ₂ May be less than 90.

In some embodiments, the angle θ ₁ And angle theta ₂ May be the same. Therefore, the pad 106' a is formed in parallel with the insulating pattern IP.

However, in other embodiments, the inclined shape of the plurality of pads 106' a may be changed. In other words, the angle θ ₁ May be greater than 90. In this case the angle theta ₂ And may be greater than 90.

Alternatively, the inclined shape of the plurality of pads 106'a formed in one region of the substrate and the inclined shape of the plurality of pads 106' a formed in another region of the substrate may be different from each other. In other words, there may be multiple angles θ on one substrate ₁ 。

Alternatively, as shown in fig. 16, the dummy insulation patterns DIP "and the dummy slits DS" may also be formed in cooperation with the plurality of pads 106"a and the plurality of slits S". The dummy insulation patterns DIP "do not correspond to the pads 106a, and are spaced apart from each other across the dummy slits DS.

The inclined shapes of the pad 106"a and the slit S" are the same as those of fig. 15, and thus the description thereof will not be repeated.

Here, the virtual slit DS "has a slanted shape, similar to the slit S".

Fig. 17 to 25 are sectional views describing a method of manufacturing the display device 1000 of fig. 1 based on a line b-b' of fig. 1, according to an embodiment of the present invention. Which includes a process of manufacturing the insulation pattern IP according to the embodiment of fig. 3.

Referring to fig. 17, a substrate 100 is first prepared. Substrate 100 may be formed from any of a variety of materials, and in some embodiments, may be formed from a flexible material as described above. The first inorganic film 101 is formed on the substrate 100. The first inorganic film 101 may be a functional buffer film formed on the entire central area CA of the substrate 100 including the display area DA, the non-display area NDA, and the pad area PDA, and a peripheral area PA around the cutting line CL and including the pad peripheral area PPA. In other words, the buffer film may be formed on the entire top surface of the substrate 100. Here, the substrate 100 may be the substrate 100 that will form one display device 1000, or a mother glass that will form a plurality of display devices 1000.

The buffer film can be formed by using SiO ₂ And/or SiN _x Formed via one of various deposition methods, such as a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, an Atmospheric Pressure CVD (APCVD) method, and a Low Pressure CVD (LPCVD) method.

Referring to fig. 18, tfts are formed in the display area DA on the buffer film. The TFT formed on the display area DA operates as a part of the pixel circuit. Here, the TFT may also be formed on the non-display area NDA. The TFT formed on the non-display area NDA may operate as a part of a circuit included in the driver.

Herein, the TFT is a top gate type including an active layer 102, a gate electrode 104, and source and

drain electrodes

106s and 106d in this order from a buffer film. However, the type of the TFT is not limited thereto, and the TFT may be any of various types, such as a bottom gate type.

The active layer 102 is formed on the buffer film in a pattern shape. The active layer 102 includes a semiconductor material, for example, amorphous silicon or polysilicon. However, embodiments of the present invention are not limited thereto, and the active layer 102 may include any of various materials. In some embodiments, the active layer 102 may include an organic semiconductor material.

In some embodiments, the active layer 102 may include an oxide semiconductor material. For example, the active layer 102 may include G-I-Z-O [ (In) ₂ O ₃ )a(Ga ₂ O ₃ )b(ZnO)c]Wherein a, b and c respectively satisfy a.gtoreq.0, b.gtoreq.0 and c>Real number of 0. In addition to G-I-Z-O, the active layer 102 may include, for example, a metal element selected from groups 12, 13, and 14 (e.g., zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (C)d) Germanium (Ge), and hafnium (Hf)), or combinations thereof.

As described above, the present embodiment may include a TFT in any one of various shapes, for example, a TFT having a bottom gate structure. When the active layer 102 includes oxide or amorphous silicon, the present embodiment may include a TFT having a bottom gate structure.

The TFT having the bottom-gate structure may have any of various shapes, for example, the gate electrode 104 may be formed on the substrate 100, the active layer 102 may be formed on the gate electrode 104, and the source electrode 106s and the drain electrode 106d may be disposed on the active layer 102. Alternatively, the gate electrode 104 may be formed on the substrate 100, the source electrode 106s and the drain electrode 106d may be formed on the gate electrode 104, and the active layer 102 may be formed on the source electrode 106s and the drain electrode 106 d. In this case, an insulating film (e.g., an inorganic film) may be formed to contact at least one of the gate electrode 104, the active layer 102, the source electrode 106s, and the drain electrode 106 d.

The active layer 102 includes source and drain regions contacting the source and

drain electrodes

106s and 106d, respectively, and a channel region between the source and drain regions. When the active layer 102 includes amorphous silicon or polycrystalline silicon, impurities may be selectively doped on the source and drain regions.

A gate insulating layer 103 is formed on the active layer 102. The gate insulating layer 103 may be formed of a single layer or a plurality of layers formed of an inorganic material (e.g., silicon oxide and/or silicon nitride). The gate insulating layer 103 insulates the active layer 102 and the gate electrode 104 from each other.

The gate insulating layer 103 may be a single layer forming the second inorganic pattern 102P, and may be formed on the entire central area CA of the substrate 100 including the display area DA, the non-display area NDA, and the pad area PDA and the peripheral area PA including the pad peripheral area PPA around the cutting line CL of the substrate 100. In other words, the gate insulating layer 103 may be formed on the entire substrate 100. Here, the substrate 100 may be the substrate 100 forming one display device 1000, or a mother glass forming a plurality of display devices 1000.

A gate electrode 104 is formed on the gate insulating layer 103 in a pattern shape. The gate electrode 104 is coupled to a gate line for applying an on/off signal to the TFT. The gate electrode 104 may be formed of a low-resistance metal material, for example, may be formed as a multi-layer or a single layer formed of a conductive material, for example, molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti).

An interlayer dielectric film 105 is formed on the gate electrode 104. The interlayer dielectric film 105 insulates the source electrode 106s, the drain electrode 106d, and the gate electrode 104 from each other. The interlayer dielectric film 105 may be formed as a multilayer or a single layer formed of an inorganic material. For example, the inorganic material may be a metal oxide or a metal nitride, and the inorganic material may include silicon oxide (SiO) ₂ ) Silicon nitride (SiN) _x ) Silicon oxynitride (SiON), aluminum oxide (Al) ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Tantalum oxide (Ta) ₂ O ₅ ) Hafnium oxide (HfO) ₂ ) And zinc oxide (ZnO) ₂ )。

The interlayer dielectric film 105 may be a single layer forming the second inorganic pattern 102P, and may be formed on the entire central area CA of the substrate 100 including the display area DA, the non-display area NDA, and the pad area PDA and the peripheral area PA including the pad peripheral area PPA around the cutting line CL. In other words, the interlayer dielectric film 105 may be formed on the entire substrate 100. Here, the substrate 100 may be the substrate 100 forming one display device 1000, or a mother glass forming a plurality of display devices 1000.

Then, referring to fig. 19, the contact hole CNT is formed in the gate insulating layer 103 and the interlayer dielectric film 105, and at the same time, is patterned with respect to the peripheral area PA.

The contact hole CNT is formed to expose a surface (e.g., a predetermined surface) of the active layer 102. The contact hole CNT may then enable the source electrode 106s and the drain electrode 106d to be electrically coupled to the active layer 102. Meanwhile, when the contact hole CNT is formed, the removal of the gate insulating layer 103 and the interlayer dielectric film 105 in the peripheral region PA and the formation of the insulating pattern IP in the pad peripheral region PPA are concurrently (e.g., simultaneously) performed. In other words, the gate insulating layer 103 and the interlayer dielectric film 105 in the peripheral region PA located around the cutting line CL are also removed, and the slit S for forming the insulating pattern IP is formed in the pad peripheral region PPA. Therefore, according to the embodiment of the present invention, since a separate process for patterning the gate insulating layer 103 and the interlayer dielectric film 105 in the peripheral area PA may not be required, the manufacturing process may be simplified.

Referring to fig. 20, a metal layer 106f for forming the source and

drain electrodes

106s and 106d and the pad 106a is formed on the interlayer dielectric film 105. The metal layer 106f may be formed as a multi-layer or a single-layer conductive material, for example, mo, al, cu, or Ti, which has a low resistance.

Then, referring to fig. 21, the metal layer 106f is patterned to form the source and

drain electrodes

106s and 106d and the pad 106a. The source electrode 106s and the drain electrode 106d contact the source region and the drain region of the active layer 102, respectively, through contact holes CNT formed in the interlayer dielectric film 105 and the gate insulating layer 103. In addition, the pad 106a is formed in the pad area PDA.

Meanwhile, if the metal layer is not completely removed, the remaining metal film 106p may remain on the side surfaces of the inorganic film of the pad peripheral region PPA, for example, the side surfaces of the gate insulating layer 103 and the interlayer dielectric film 105. When the circuit board 300 on which the external circuit is mounted is subsequently bonded to the pad 106a, the remaining metal film 106p may generate a short circuit.

Referring to fig. 22, a passivation film 107 is formed to cover the TFT.

The passivation film 107 eliminates a stepped portion caused by the TFT and flattens the top surface of the TFT, thereby preventing defects of the Organic Light Emitting Device (OLED) caused by bottom unevenness. The passivation film 107 may be formed as a single layer or a plurality of layers formed of an organic material. The organic material may include general commercial polymers such as Polymethylmethacrylate (PMMA) or Polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and combinations thereof. Alternatively, the passivation film 107 may be formed of a composite stack of an inorganic insulating film and an organic insulating film.

Then, the OLED is formed on the passivation film 107, referring to fig. 23 to 26.

A hole 107a exposing one of the source electrode 106s and the drain electrode 106d and an opening 107b exposing a top surface of the pad 106a are formed in the passivation film 107. The hole 107a is a channel for electrically coupling the TFT with an OLED formed later. Meanwhile, the opening 107b is a passage for electrically coupling the pad 106a with the circuit board 300 on which an external circuit is mounted by exposing the pad 106a.

Next, an OLED is formed on the passivation film 107. The OLED includes a pixel electrode 111, a counter electrode 112 facing the pixel electrode 111, and an intermediate layer 113 between the pixel electrode 111 and the counter electrode 112. The display devices are classified into a bottom emission type, a top emission type, and a dual emission type according to an emission direction of the OLED. In the bottom emission type, the pixel electrode 111 is a transmissive electrode and the counter electrode 112 is a reflective electrode. In the top emission type, the pixel electrode 111 is a reflective electrode and the counter electrode 112 is a semi-transmissive electrode. In the dual emission type, both the pixel electrode 111 and the counter electrode 112 are transmissive electrodes. In this embodiment mode, the organic light-emitting display device is a top emission type.

Referring to fig. 23, the pixel electrode 111 may be patterned into an island shape. Further, the pixel electrode 111 is in contact with the TFT included in the pixel circuit through the hole of the passivation film 107. Meanwhile, the pixel electrode 111 may be formed to overlap the TFT so that a pixel circuit under the pixel electrode 111 is hidden.

The pixel electrode 111 includes a reflective electrode layer and a transparent electrode layer so that light can be reflected in the direction of the counter electrode 112. When the pixel electrode 111 operates as an anode, the transparent electrode layer may include at least one material selected from the group consisting of transparent conductive oxides having a high work function, such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In) ₂ O ₃ ) Indium Gallium Oxide (IGO) and Aluminum Zinc Oxide (AZO). The reflective electrode layer may include a metal having high reflectivity, such as silver (Ag).

Further, a pixel defining film 109 is formed on the passivation film 107. The pixel defining film 109 may be formed by at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin via spin coating or the like. The pixel defining film 109 includes an opening 109a covering an edge of the pixel electrode 111 and opening at least a central portion of the pixel electrode 111. The region limited by the opening 109a corresponds to the emission region and the intermediate layer 113 is formed in the region.

Then, the first inorganic film 101 in the peripheral area PA is patterned, referring to fig. 24.

Although not shown, the first inorganic film 101 exposed around the cutting line CL is removed, and the first inorganic film 101 is removed with respect to the pad peripheral region PPA to form a slit S exposing the top surface of the substrate 100. Accordingly, in the pad peripheral region PPA, the insulating patterns IP each including the first and second

inorganic patterns

101P and 102P may be formed across the gap S exposing the substrate 100.

When patterning the first inorganic film 101, side end portions of the gate insulating layer 103 and the interlayer dielectric film 105 may match with side end portions of the first inorganic film 101. In this case, when the first inorganic film 101 is patterned, the residual metal film on the side surface of the second inorganic pattern 102P may be removed. Accordingly, the short circuit may be prevented (or substantially prevented) by removing the residual metal film of the pad peripheral area PPA, which may improve reliability of the display device 1000.

In the present embodiment, the insulating pattern IP may be formed by using the first inorganic film 101, the gate insulating layer 103, and the interlayer dielectric film 105 operating as a buffer film. Although not shown, when the TFT according to the present embodiment has the bottom gate structure as described above, for example, when an active layer including an oxide semiconductor material is formed, the insulating pattern IP may be formed by using the first inorganic film 101 operating as a buffer film, a gate insulating layer between the active layer and the gate electrode, and a passivation film that may be formed on the source electrode and the drain electrode.

Alternatively, the present embodiment may include a TFT having any one of various shapes, and in this case, the insulating pattern IP may be formed by extending any one of various types of insulating layers, which are adjacent to or directly contact the active layer, the gate electrode, and the source and drain electrodes.

Then, referring to fig. 25, an intermediate layer 113 is formed in the emission region. The intermediate layer 113 includes an organic emission layer emitting red, green, or blue light, wherein the organic emission layer may be formed of a low molecular organic material or a high molecular organic material. When the organic emission layer is a low molecular organic layer formed of a low molecular organic material, the Hole Transport Layer (HTL) and the Hole Injection Layer (HIL) are positioned in the direction of the pixel electrode 111, and the Electron Transport Layer (ETL) and the Electron Injection Layer (EIL) are stacked in the direction of the counter electrode 112 based on the organic emission layer. Here, any one of the respective layers other than the HTL, the HIL, the ETL, and the EIL may be stacked if necessary.

Meanwhile, the organic emission layer may be separately formed according to the organic light emitting device. In this case, the organic emission layer may emit red light, green light, or blue light, respectively, according to the organic light emitting device. However, embodiments of the present invention are not limited thereto, and the organic emission layer may be generally formed on the entire surface of the organic light emitting device. For example, a plurality of organic emission layers emitting red, green, and blue light may be vertically stacked or mixed to emit white light. Here, the color combination for emitting white light is not limited to the above description. However, in this case, a color conversion layer or a color filter for converting the white light into another color (e.g., a predetermined color) may be included, respectively.

Next, the counter electrode 112 is formed to cover the entire surface of the OLED. The counter electrode 112 may be formed of a conductive inorganic material. When the counter electrode 112 operates as a cathode, the counter electrode 112 may be formed of a metal having a low work function, such as lithium (Li), calcium (Ca), lithium fluoride/calcium (LiF/Ca), lithium fluoride/aluminum (LiF/Al), aluminum (Al), magnesium (Mg), or silver (Ag), or a metal thin film for light transmission. The counter electrode 112 may be formed as a common electrode on the entire surface of the display area DA where an image is realized. Here, the counter electrode 112 may be formed via an evaporation process that may not damage the intermediate layer 113. Meanwhile, polarities of the pixel electrode 111 and the counter electrode 112 may be switched with each other. Finally, the display device 1000 is completed by forming the counter electrode 112.

Although not shown, an insulating cover layer may also be formed on the counter electrode 112. When the encapsulation film is formed through a sputtering process or a PECVD process, the insulating capping layer may maintain the work function of the counter electrode 112 and prevent the organic material included in the intermediate layer 113 from being damaged. The insulating cover layer is an optional component and may not include the insulating cover layer.

Then, although not shown, the OLED may be sealed by a sealing film to block external moisture or external air. The sealing film may have a film shape in which, for example, an inorganic material (e.g., siO) _x Or SiN _x ) The formed films and the films formed of an organic material (e.g., epoxy resin or polyimide) are alternately stacked on top of each other. However, alternatively, the sealing film may include a film formed of low-melting glass.

By sealing the OLEDs using a sealing film, the display device 1000 may have an overall flexible characteristic. Accordingly, the display device 1000 according to some embodiments of the present invention may be bent, folded, and rolled.

However, the present embodiment is not limited thereto, and a sealing member formed of any of other various materials may be formed on the OLED.

Fig. 26 to 27 are sectional views describing a method of manufacturing the display device 1000 of fig. 1 based on a line b-b' of fig. 1, according to another embodiment of the present invention. In fig. 26 and 27, a process of manufacturing the insulation pattern IP according to the embodiment of fig. 5 is included.

According to fig. 26, when the first inorganic film 101 in the peripheral area PA is patterned, the gate insulating layer 103 and the interlayer dielectric film 105 may not completely cover the top surface of the first inorganic film 101, i.e., the first inorganic film 101 may protrude farther than the end portions of the gate insulating layer 103 and the interlayer dielectric film 105.

Meanwhile, in the process of manufacturing the insulation pattern IP according to the embodiment of fig. 6, the process of patterning the first inorganic film 101 is omitted from the methods of fig. 17 to 25, and a repetitive description will not be repeated here.

Meanwhile, in the process of manufacturing the insulation pattern IP according to the embodiment of fig. 7 and 8, the process of patterning a portion of the first inorganic film 101 is included in the methods of fig. 17 to 25, and a repetitive description will not be repeated here.

Fig. 28 to 31 are sectional views describing a method of manufacturing the display device 1000 of fig. 1 based on a line b-b' of fig. 1, according to another embodiment of the present invention. In fig. 28 to 31, a process of manufacturing the insulation pattern IP according to the embodiment of fig. 10 is included.

Referring to fig. 28, when the passivation film 107 is formed, the passivation film 107 may also cover the top and side surfaces of the second inorganic pattern 102P in the pad peripheral region PPA. Accordingly, a residual metal film that may remain on the side surface of the second inorganic pattern 102P may be covered by the passivation film 107, thereby preventing a short circuit.

Fig. 29 shows a process of forming a pixel defining film 109 like in fig. 23, and fig. 30 shows a process of patterning the first inorganic film 101 like in fig. 24 in the peripheral area PA. Unlike fig. 24, in fig. 30, the side end faces of the gate insulating layer 103 and the interlayer dielectric film 105 and the side end face of the first inorganic film 101 are patterned to be mismatched with each other so that the top surface of the first inorganic film 101 is partially exposed. Fig. 31 shows a process of forming the intermediate layer 113 and the counter electrode 112 similar to fig. 25.

Meanwhile, in the embodiments of fig. 9 and 11 to 14, a process of covering at least the second inorganic pattern 102P by the organic film 107P described above with reference to fig. 28 to 31 is also added, and a repeated description will not be repeated here.

Characteristics of the display device 1000 according to the embodiment of the present invention will now be described in more detail with reference to fig. 32 to 36.

Fig. 32 is a plan view schematically showing a display device 1000 according to a comparative embodiment. Fig. 33 is an enlarged plan view of the region VII of fig. 32.

In fig. 32, a circuit board 300 on which an external circuit is mounted is bonded to the pad 106a. On the circuit board 300, chips for transmitting various types of power or electrical signals to the display area DA are mounted. This chip is not shown in fig. 32. The circuit board 300 includes wires 106l for coupling the chip with the pads 106a of the substrate 100. Here, by bonding the wire 106l to the pad 106a, various types of electric power or electric signals output from the chip may be transmitted to the display area DA through the pad 106a.

Referring to fig. 33, when the insulating pattern IP and the slit S are not included in the pad peripheral region PPA, impurities, particles, or a residual metal film remaining when forming a metal film may be left, and the conductive line 106l may be electrically short-circuited due to the residual metal film, thereby generating a short circuit.

Fig. 34 is a plan view schematically showing a display apparatus 1000 according to an embodiment of the present invention, fig. 35 is an enlarged plan view of a region IX of fig. 34, and fig. 36 is a sectional view taken along a line Q-Q' of fig. 35.

Referring to fig. 34 and 36, the present embodiment is substantially similar to the comparative example in which the circuit board 300 includes the conductive line 106l, but is different from the comparative example in that the insulation pattern IP and the slit S are located in the pad peripheral region PPA of the substrate 100.

Referring to fig. 35, since the insulating pattern IP and the slit S are arranged in the pad peripheral region PPA, even when a residual metal film is left on the side surface of the inorganic film removed to form the slit S, the wire 106l is not electrically short-circuited by the residual metal film. In other words, the wires 106l are arranged corresponding to the insulation patterns IP, or the slits S are arranged between the wires 106l. As shown in fig. 36, the conductive line 106l may extend over the insulation pattern IP, for example, over the second inorganic pattern 102P of the insulation pattern IP.

Therefore, a short circuit similar to that in the comparative embodiment may not be generated.

As described above, according to one or more of the above-described embodiments of the present invention, in the display device, when a circuit board on which an external circuit is mounted is combined, a short-circuit defect is prevented (or substantially prevented).

Although one or more embodiments of the present invention have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. A display device, comprising:

a central region having a display region and a pad region on the substrate;

a peripheral region surrounding the central region;

a plurality of pads in the pad region, the pad region being between the display region and the peripheral region;

a plurality of insulation patterns in a pad peripheral region disposed in the peripheral region and adjacent to the pad region; and

a slit between the plurality of insulation patterns in the pad peripheral region.

2. The display device according to claim 1, wherein the plurality of pads each include an extension line, and wherein the plurality of insulating patterns overlap with the extension line.

3. The display device according to claim 1, wherein the plurality of insulating patterns comprise an inorganic material.

4. The display device according to claim 1, further comprising an organic film covering at least one region of side surfaces and an uppermost surface of the plurality of insulating patterns.

5. The display device according to claim 1, wherein the peripheral region comprises a region where a top surface of the substrate is exposed.

6. The display device according to claim 5, wherein the region where the top surface of the substrate is exposed is adjacent to the pad peripheral region.

7. The display device of claim 5, wherein the area exposing the top surface of the substrate is adjacent to an edge of the substrate.

8. The display device of claim 1, wherein an edge of the substrate is defined by a cut line.

9. The display device of claim 1, wherein at least one inorganic film is located in a center region of the substrate.

10. The display device according to claim 9, wherein the plurality of insulating patterns have a shape connected to the at least one inorganic film.

11. The display device of claim 9, wherein the at least one inorganic film extends to the pad region and the plurality of pads are on the at least one inorganic film.

12. The display device of claim 9, wherein the at least one inorganic film comprises a plurality of layers.

13. The display device according to claim 1, wherein each of the plurality of insulating patterns comprises a stacked plurality of inorganic patterns.

14. The display device according to claim 13, wherein each of the plurality of insulating patterns comprises a first inorganic pattern and a second inorganic pattern on the first inorganic pattern.

15. The display device according to claim 14, wherein a top surface of the first inorganic pattern is completely covered with the second inorganic pattern.

16. The display device according to claim 14, wherein a top surface of the first inorganic pattern has an exposed area.

17. The display device according to claim 14, further comprising an organic film covering at least side surfaces and a top surface of the second inorganic pattern of the plurality of insulating patterns.

18. The display device according to claim 1, wherein a first inorganic film is located between the plurality of insulating patterns and the substrate.

19. The display device according to claim 18, wherein a groove is formed in the first inorganic film, and wherein the groove is formed in a region where the first inorganic film overlaps with the slit.

20. The display device according to claim 18, further comprising an organic film covering at least side surfaces and a top surface of the plurality of insulating patterns without covering portions of the first inorganic film corresponding to the slits.

21. The display device according to claim 1, further comprising in the center region:

a buffer film on the substrate; and

a plurality of thin film transistors on the buffer film and including an active layer, a gate electrode, a source electrode, and a drain electrode,

wherein at least one insulating film is adjacent to at least one of the active layer, the gate electrode, the source electrode, and the drain electrode, and

the plurality of insulating patterns and the at least one insulating film are of the same material.

22. The display device according to claim 21, wherein the plurality of insulating patterns and the at least one insulating film are connected to each other.

23. The display device according to claim 21, wherein the at least one insulating film comprises at least one of a buffer film formed over the substrate, a gate insulating layer insulating the gate electrode and the active layer, and an interlayer dielectric film insulating the source electrode and the drain electrode from the gate electrode.

24. The display device according to claim 21, wherein the at least one insulating film comprises at least one of a buffer film formed over the substrate, a gate insulating layer insulating the gate electrode and the active layer, and a passivation film formed over the source electrode and the drain electrode.

25. The display device according to claim 21, further comprising an organic film covering the plurality of thin film transistors,

wherein the organic film covers at least one region of side surfaces and uppermost surfaces of the plurality of insulating patterns.

26. The display device according to claim 21, further comprising:

a pixel electrode electrically coupled to at least one of the plurality of thin film transistors; and

a pixel defining film covering a portion of the pixel electrode and defining an emission area,

wherein the pixel defining film covers at least one area of side surfaces and uppermost surfaces of the plurality of insulating patterns.

27. The display device according to claim 26, further comprising a counter electrode facing the pixel electrode,

wherein an organic emission layer is positioned between the pixel electrode and the counter electrode.

28. The display device of claim 1, wherein the substrate comprises a flexible material.

29. The display device according to claim 1, further comprising:

a dummy insulating pattern in the pad peripheral region and spaced apart from the plurality of insulating patterns, wherein the dummy insulating pattern does not correspond to the plurality of pads; and

dummy slits between the dummy insulating patterns, wherein a portion of the dummy insulating patterns is removed in the peripheral region to form the dummy slits.

30. The display device according to claim 1, wherein an angle formed by an extension line of the plurality of pads and an edge of the substrate is less than or greater than 90 ° to give the plurality of pads an inclined shape, and

an angle formed by an extension line of the slit and an edge of the substrate is less than or greater than 90 ° to give the slit an inclined shape.

31. The display device according to claim 30, wherein an angle formed by an extension line of the plurality of pads and an edge of the substrate is the same as an angle formed by an extension line of the slit and an edge of the substrate.

32. The display device according to claim 1, further comprising a circuit board on which an external circuit is mounted so that an electric signal is transmitted to the display area,

wherein a plurality of wires of the circuit board are coupled to the plurality of pads.

33. The display device according to claim 32, wherein the plurality of conductive lines of the circuit board are located on the plurality of insulation patterns and are separated by the slit.

34. A method of manufacturing a display device including a central region having a display region and a pad region on a substrate and a peripheral region surrounding the central region, the method comprising:

forming a plurality of pads in a pad region, the pad region being located between the display region and the peripheral region;

forming a plurality of insulation patterns corresponding to the plurality of pads in a pad peripheral region disposed in the peripheral region and adjacent to the pad region; and

forming a gap between the plurality of insulation patterns in the pad peripheral region.

35. The method of claim 34, further comprising forming an inorganic film in a central region of the substrate,

wherein the plurality of insulating patterns include the inorganic film.

36. The method of claim 35, wherein the inorganic film comprises a plurality of layers.

37. The method of claim 36, further comprising:

forming the plurality of insulating patterns spaced apart from each other across the gap by patterning a layer including at least an uppermost layer of the plurality of layers of the inorganic film; and

forming the plurality of pads on any one of the plurality of layers of the inorganic film after forming the plurality of insulating patterns.

38. The method of claim 37, further comprising, after forming the plurality of pads, removing a lowermost layer of the plurality of layers including at least the inorganic film in a region corresponding to the gap.

39. The method of claim 34, wherein the peripheral region comprises a region that exposes a top surface of the substrate.