KR102419177B1 - Display device and method of manufacturing the same - Google Patents

Abstract

One embodiment of the present invention relates to a display device including a central region having at least a display region on a substrate and a peripheral region disposed around the central region, wherein the central region includes a plurality of pads arranged in one direction. In at least a region adjacent to the pads among the peripheral regions, an insulating pattern corresponding to the plurality of pads and an insulating material formed between the insulating patterns and forming the insulating pattern are removed. Disclosed is a display device in which a slit is formed.

Description

Display device and method of manufacturing the same

Embodiments of the present invention relate to a display device and a manufacturing method thereof, and more particularly, to a display device using a flexible substrate and a manufacturing method thereof.

In the display field, a display device using a flexible substrate that is light and thin and has excellent impact resistance is being developed. A display device using a flexible substrate is formed by cutting from a mother glass. In detail, a plurality of display devices may be formed on the mother substrate. Such display devices are separated into individual display devices by, for example, cutting the display substrate along a cutting line using a press.

However, when it is cut by physical pressure such as a press, the periphery of the cut line of the display substrate is burr or distorted. There is a problem in that each layer on the display substrate is lifted or cracks are generated due to such distortion or distortion, thereby causing line breakage. In addition, there is a problem in that the layers on the display substrate around the cutting line are separated during cutting, thereby reducing the reliability of the display device.

In order to solve this problem, an attempt has been made to expose the display substrate by removing a layer around the cut line on the display substrate. However, when a metal residual film is present in the step formed by removing the layer around the cut line, when the pads formed on the display substrate and the circuit board on which the external circuit is mounted are connected, the lines and the residual film included in the circuit board are electrically There is a problem that a short circuit occurs due to the connection.

SUMMARY Embodiments of the present invention provide a display device using a flexible substrate and a method of manufacturing the same.

One embodiment of the present invention relates to a display device including a central region having at least a display region on a substrate and a peripheral region disposed around the central region, wherein the central region includes a plurality of pads arranged in one direction. In at least a region adjacent to the pads among the peripheral regions, an insulating pattern corresponding to the plurality of pads and an insulating material formed between the insulating patterns and forming the insulating pattern are removed. Disclosed is a display device in which a slit is formed.

In the present embodiment, the insulating pattern may overlap at least extension lines of the pads.

In this embodiment, the insulating pattern may include an inorganic material.

In the present embodiment, an organic layer formed to cover the top surface of the insulating pattern and at least one region of a side surface of the insulating pattern may be further included.

In the present embodiment, the peripheral region may include a region in which the upper surface of the substrate is exposed in at least one region.

In the present embodiment, the peripheral region may be adjacent to the pads and include a pad peripheral region in which the plurality of insulating patterns and slits are disposed, and the exposed region of the upper surface of the substrate may be formed adjacent to the pad peripheral region. can

In the present exemplary embodiment, the region where the upper surface of the substrate is exposed may be formed to be adjacent to a plurality of edges among the edges of the substrate.

In this embodiment, the edge of the substrate may be defined as a cutting line.

In the present embodiment, one or more inorganic layers may be formed in the central region of the substrate.

In this embodiment, the insulating patterns may have a shape connected to the inorganic layer.

In this embodiment, the plurality of pads may be formed on the inorganic layer.

In this embodiment, the inorganic film may have a form in which a plurality of layers are stacked.

In this embodiment, the insulating pattern may have a form in which a plurality of inorganic patterns are stacked.

In this embodiment, the insulating pattern may include a first inorganic pattern and a second inorganic pattern formed on the first inorganic pattern.

In the present embodiment, the insulating pattern may be formed such that an upper surface of the first inorganic pattern is completely covered by the second inorganic pattern.

In the present exemplary embodiment, the insulating pattern may be formed to have an exposed region of the upper surface of the first inorganic pattern.

In the present embodiment, the insulating pattern may further include an organic layer covering at least an upper surface and a side surface of the second inorganic pattern.

In the present embodiment, a first inorganic layer may be formed between the insulating pattern and the substrate.

In the present embodiment, a portion of the first inorganic layer may be removed to form a groove in a region overlapping the slit among the regions of the first inorganic layer.

In the present exemplary embodiment, an organic layer may further include an organic layer covering at least an upper surface and a side surface of the insulating pattern and not covering one of the regions corresponding to the slits among the regions of the first inorganic layer.

In the present embodiment, the central region further includes a buffer film formed on the substrate and a plurality of thin film transistors (TFTs) formed on the buffer film and including an active layer, a gate electrode, a source electrode and a drain electrode, At least one insulating layer may be formed adjacent to the active layer, the gate electrode, the source electrode, and the drain electrode, and the insulating pattern may be formed of the same material as the at least one insulating layer.

In this embodiment, the insulating pattern and the one or more insulating layers may be formed to be connected.

In this embodiment, the at least one insulating layer is at least one of a buffer layer formed on the substrate, a gate insulating layer insulating the gate electrode and the active layer, and an interlayer insulating layer insulating between the source and drain electrodes and the gate electrode. can

In the present embodiment, the one or more insulating layers may be at least one of a buffer layer formed on the substrate, a gate insulating layer insulating the gate electrode and the active layer, and a protective layer formed on the source electrode and the drain electrode.

In the present embodiment, an organic layer may further include an organic layer covering the thin film transistor, and the organic layer may be formed to cover at least one region of a top surface and a side surface of the insulating pattern.

In the present embodiment, the display device further includes a pixel electrode electrically connected to at least one of the thin film transistors (TFT) and a pixel defining layer covering a portion of the pixel electrode and defining a light emitting region, wherein the pixel defining layer is an uppermost surface of the insulating pattern. It may be formed so as to cover at least one region of the lateral surface.

In the present exemplary embodiment, an opposing electrode facing the pixel electrode may be further provided, and an organic emission layer may be interposed between the pixel electrode and the opposing electrode.

In this embodiment, a flexible material may be applied to the substrate.

In the present embodiment, in the peripheral region, a dummy insulating pattern spaced apart from the insulating pattern and not corresponding to the pads and at least a portion of an insulating material formed between the dummy insulating patterns and forming the dummy insulating pattern is removed. A dummy slit in the form of may be further formed.

In the present embodiment, the plurality of pads have an inclined shape so that an angle formed by the extension lines of the plurality of pads with the edge of the substrate is less than 90 degrees or greater than 90 degrees, and the slits have an inclined shape. An angle between the extension line and the edge of the substrate may be less than 90 degrees or greater than 90 degrees.

In the present embodiment, an angle between the extension lines of the plurality of pads and the edge of the substrate may be the same as an angle between the extension lines of the slit and the edge of the substrate.

In the present embodiment, the display device may further include a circuit board on which an external circuit is mounted so as to transmit an electrical signal to the display area, and a plurality of wires of the circuit board may be connected to the pad.

In the present embodiment, the plurality of wirings of the circuit board may be disposed on the insulating pattern and spaced apart from the slits.

Another embodiment of the present invention relates to a method of manufacturing a display device including a central region having at least a display region on a substrate and a peripheral region disposed around the central region, wherein the central region is arranged in one direction. A plurality of pads is formed, and at least a portion of an insulating pattern corresponding to the plurality of pads and an insulating material serving as a material of the insulating pattern between the insulating patterns is removed in at least a region adjacent to the pads among the peripheral regions. Disclosed is a method of manufacturing a display device, comprising forming a slit in the shape of a display device.

In the present embodiment, the method may include forming one or more inorganic layers in the central region of the substrate, and the insulating pattern may be formed using the inorganic layer.

In this embodiment, the inorganic film may be formed by laminating a plurality of layers.

In this embodiment, after patterning a layer including at least an uppermost layer among the plurality of layers of the inorganic film to form an insulating pattern spaced apart from each other with the slit therebetween, the plurality of pads are applied to the inorganic film. It may include the step of forming on any one of a plurality of layers.

In the present embodiment, after the forming of the plurality of pads is performed, the method may include removing a layer including at least a lowermost layer among the layers of the inorganic layer in the region corresponding to the slit.

In the present embodiment, the peripheral region may be formed to include a region in which the upper surface of the substrate is exposed in at least one region.

Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

The display device according to the embodiments of the present invention has a feature of solving a short-circuit defect during bonding of a circuit board on which an external circuit is mounted.

1 is a plan view schematically illustrating a display device according to an embodiment of the present invention.
FIG. 2 is an enlarged schematic plan view of II of FIG. 1 .
3 is a cross-sectional view showing an embodiment taken along a-a' of FIG.
4 is a plan view schematically illustrating a display device according to another embodiment of the present invention.
5 to 14 are cross-sectional views showing other embodiments taken along a-a' of FIG. 2 .
15 and 16 are views illustrating other modified examples of FIG. 2. FIGS. 17 to 25 show an embodiment of a method of manufacturing the display device of FIG. 1 sequentially based on the cutting line b-b'. A cross-sectional view is shown.
26 and 27 are cross-sectional views sequentially showing another embodiment of the method of manufacturing the display device of FIG. 1 based on the cutting line b-b'.
28 to 31 are cross-sectional views sequentially showing another embodiment of the method of manufacturing the display device of FIG. 1 taken along the line b-b'.
32 is a plan view schematically illustrating a display device according to a comparative example of the present invention.
FIG. 33 is an enlarged schematic plan view of VII of FIG. 32 .
34 is a plan view schematically illustrating a display device according to an embodiment of the present invention.
FIG. 35 is an enlarged schematic plan view of IX of FIG. 34 .
36 is a cross-sectional view taken along the line Q-Q' of FIG. 35 .

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and a method for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

In the following embodiments, terms such as first, second, etc. are used for the purpose of distinguishing one component from another, not in a limiting sense.

In the following examples, the singular expression includes the plural expression unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have means that the features or components described in the specification are present, and the possibility that one or more other features or components may be added is not excluded in advance.

In the following embodiments, when it is said that a part such as a film, region, or component is on or on another part, it is not only when it is directly on the other part, but also another film, region, component, etc. is interposed therebetween. Including cases where there is

In the drawings, the size of the components may be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

In the following embodiments, the x-axis, the y-axis, and the z-axis are not limited to three axes on the Cartesian coordinate system, and may be interpreted in a broad sense including them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

In cases where certain embodiments are otherwise practicable, a specific process sequence may be performed different from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the order described.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted. .

1 is a plan view schematically illustrating a display apparatus 1000 according to an embodiment of the present invention, FIG. 2 is a schematic plan view enlarged by II of FIG. 1, and FIG. It is a cross-sectional view showing an embodiment cut along.

Referring to FIG. 1 , a display apparatus 1000 according to an embodiment of the present invention includes a substrate 100 . The substrate 100 may include various materials. Specifically, the substrate 100 may be formed of glass, metal, or other organic material.

As an optional embodiment, the substrate 100 includes the substrate 100 made of a flexible material. Here, the substrate 100 made of a flexible material is a flexible substrate and refers to a substrate that can be bent, bent, and folded or rolled. The substrate 100 made of such a flexible material may be made of ultra-thin glass, metal, or plastic. For example, when plastic is used, the substrate 100 may be made of polyimide (PI), but this is exemplary and various materials may be applied.

A plurality of display apparatuses 1000 may be formed on the mother substrate, and may be separated into individual display apparatuses 1000 by cutting along the cutting line CL of the substrate 100 . 1 illustrates an individual display device 1000 cut and separated along a cutting line CL. Accordingly, the edge of the substrate 100 is defined by the cutting line CL.

The substrate 100 is divided into a peripheral area PA and a central area CA. Specifically, the peripheral area PA is an area around the cutting line CL, and the central area CA is an area inside the peripheral area PA.

However, the present embodiment is not limited thereto. That is, the cutting line CL may not exist. Specifically, one display device 1000 may be formed on one mother substrate, and in this case, the substrate 100 may be one mother substrate, so that there may be no cutting line CL. In this case, the peripheral area PA may be an area adjacent to the edge of the substrate 100 , and the central area CA may be an area inside the peripheral area PA. For convenience of description, only the case in which the cutting line CL is present will be described in the following embodiments.

The central area CA includes a display area DA and a non-display area NDA.

One or more display elements (not shown), for example, an organic light emitting diode (OLED), may be provided in the display area DA to display an image. Also, a plurality of pixels may be disposed in the display area DA.

The non-display area NDA is formed around the display area DA. Specifically, as illustrated in FIG. 1 , the non-display area NDA may be formed to surround the display area DA. Although not shown, as an optional embodiment, the non-display area NDA may be formed to be adjacent to a plurality of side surfaces of the display area DA. Also, as another optional embodiment, the non-display area NDA may be formed to be adjacent to one side of the display area DA.

The non-display area NDA includes at least a pad area PDA.

A driver or a plurality of pads 106a are disposed in the pad area PDA.

As an optional embodiment, one or more inorganic layers may be formed in the central area CA to prevent moisture permeation or impurity penetration into the display apparatus 1000 through the substrate 100 .

The peripheral area PA is an area around the cutting line CL and is provided on the periphery of the substrate 100 along the cutting line CL.

The peripheral area PA includes at least one area in which the top surface of the substrate 100 is exposed and the pad peripheral area PPA.

First, a description will be given of an area in which the upper surface of the substrate 100 in the peripheral area PA is exposed as it is.

Specifically, as shown in FIG. 1 , the peripheral area PA may include an area in which the top surface of the substrate 100 is exposed in areas adjacent to the upper edge, the left edge, and the right edge of the substrate 100 .

The area in which the upper surface of the substrate 100 provided in the peripheral area PA is exposed is cracked ( to prevent the propagation of cracks).

The width of the area in which the upper surface of the substrate 100 provided in the peripheral area PA is exposed may be about several micrometers to several hundred micrometers from the cutting line CL to the central area CA. For example, the width may be 40 to 500 micrometers, and as another example, it may be 50 to 350 micrometers.

Although not shown, the present invention may not include a region in which the upper surface of the substrate 100 is exposed in the peripheral region PA as a selective embodiment. That is, the peripheral area PA may include only a pad peripheral area PPA, which will be described later, and may be formed so that the top surface is not exposed in an area adjacent to the edge of the substrate 100 .

The pad peripheral area PPA of the peripheral area PA will be described.

The pad peripheral area PPA is an area adjacent to the pad area PDA among the peripheral areas PA.

As an optional embodiment, the pad peripheral area PPA is a case in which a circuit board (200 of FIG. 32 to be described later) on which an external circuit is mounted on the pad 106a, for example, a chip-on-film (COF), is bonded. It is assumed that the circuit board 200 may be an overlapping region.

The pad peripheral area PPA is provided at a position corresponding to at least the plurality of pads 106a.

The pad peripheral area PPA includes an insulating pattern IP. The insulating pattern IP is provided to correspond to the pads 106a, and the insulating pattern IP is disposed to be spaced apart from each other with a slit S interposed therebetween.

Specifically, the insulating pattern IP is disposed to overlap the extension line of the pad 106a. Through this, when the wiring (not shown) of the circuit board (not shown) is connected to the pad 106a, the wiring (not shown) is placed on the upper surface of the insulating pattern IP, so that the wiring (not shown) is on the substrate 100 . Prevents short circuit defects by preventing contact with foreign substances, especially metal residual film or metal particles.

As an optional embodiment, the short-circuit failure prevention effect may be increased by allowing the extension line of the pad 106a to be spaced apart from the slit S.

These effects will be described in detail later with reference to the drawings.

The insulating pattern IP provided in the pad peripheral area PPA will be described in more detail.

2 illustrates a portion of the pad area PDA in which the pad 106a is disposed and a portion of the pad peripheral area PPA adjacent to the pad area PDA. A plurality of pads 106a are formed on the substrate 100 .

At this time, as described above, as an optional embodiment, one or more inorganic layers may be formed in the central area CA on the substrate 100 . In this case, the inorganic layer may also be formed in the pad area PDA, and the pad 106a may be formed in the pad area. (PDA) can be formed on the inorganic film.

The plurality of pads 106a are arranged in one direction while being spaced apart from each other at a predetermined interval. As an optional embodiment, the plurality of pads 106a may be disposed in the width direction (x-axis direction of FIG. 2 ) of the individual pads 106a.

A plurality of insulating patterns IP are provided in the pad peripheral area PPA. As described above, as an optional embodiment, one or more inorganic layers may be formed on the central area CA of the substrate 100 . In this case, the plurality of insulating patterns IP may be connected to the inorganic layer of the pad area PDA. have. However, the present embodiment is not limited thereto, and the insulating pattern IP may be formed separately from the inorganic layer formed in the central region CA.

The insulating patterns IP are arranged in a row in a direction corresponding to the plurality of pads 106a. The insulating pattern IP may be made of an inorganic material. When one or more inorganic layers formed in the central area CA of the above-described selective embodiment and the insulating pattern IP are connected, the insulating pattern IP has a shape protruding from the pad area PDA to the pad peripheral area PPA, and each of the plurality of insulating patterns IP is provided at a position corresponding to each of the plurality of pads 106a. That is, the individual insulating patterns IP are respectively provided at positions where the individual pads 106a extend in the longitudinal direction (the y-axis direction of FIG. 2 ). A slit S is provided between adjacent insulating patterns IP, and the insulating patterns IP are spaced apart from each other with the slit S interposed therebetween. Here, the slit S means a narrow and long opening, and according to various embodiments to be described later, the slit S is a type of opening exposing the upper surface of the substrate 100 , or is greater than the upper surface of the insulating pattern IP. It may be a type of opening that exposes an inorganic film with a low top surface.

Referring to the embodiment of FIG. 3 , the slit S is a type of opening exposing the upper surface of the substrate 100 . In the embodiment of FIG. 3 , the insulating patterns IP are spaced apart from each other with a slit S exposing the upper surface of the substrate 100 therebetween.

Meanwhile, the insulating pattern IP sequentially includes a first inorganic pattern 101P and a second inorganic pattern 102P from the substrate 100 . The second inorganic pattern 102P includes a form in which a plurality of inorganic pattern layers 103P and 105P are stacked. The insulating pattern IP shown in FIG. 3 is an example, and the present embodiment is not limited thereto and may have various types of insulating patterns IP. For example, the insulating pattern IP may be formed of only one layer, may be formed of two layers, or may include four or more layers.

In addition, as described above, as an optional embodiment, one or more inorganic layers may be formed on the central area CA on the substrate 100 . In this case, the plurality of insulating patterns IP may be formed from the inorganic layer of the pad area PDA and the inorganic layer. can be connected That is, the sequentially stacked first and second inorganic patterns 101P and 102P of the insulating pattern IP may be connected to sequentially formed inorganic layers in the pad area PDA, respectively.

In addition, as an optional embodiment, various inorganic layers may be formed in the display area DA of the central area CA. That is, a buffer film (not shown) that may be formed adjacent to the substrate 100, a gate insulating film (not shown) that may be provided in a thin film transistor (TFT) for driving a pixel, and an interlayer insulating film ( A plurality of insulating patterns IP may be formed to be connected to at least one of a passivation layer (not shown), a passivation layer (not shown), and various other insulating layers.

For a specific example, the first inorganic pattern 101P is provided in the central area CA to planarize the upper surface of the substrate 100 , and is a buffer film serving as a barrier to prevent moisture permeation or foreign substances from permeating through the substrate 100 . It may include patterns. In addition, the second inorganic pattern 102P is provided in the central region CA, and the pattern 103P of the gate insulating layer insulating the active layer and the gate electrode of the thin film transistor from each other and the interlayer insulating layer insulating the gate electrode and the source and drain electrodes from each other. may include a pattern 105P of (specific details will be described later).

In the embodiment of FIG. 3 , the insulating pattern IP has a side cross-section in which the upper surface of the first inorganic pattern 101P is completely covered by the second inorganic pattern 102P. In other words, the side cross-section of the first inorganic pattern 101P and the side cross-section of the second inorganic pattern 102P may be positioned on the same line.

However, this is an exemplary drawing, and this embodiment may have various modifications. For example, when the side cross-section of the first weapon pattern 101P and the side cross-section of the second weapon pattern 102P are the same. It may be located on the photo line. As another example, the side cross-section of the first weapon pattern 101P and the side cross-section of the second weapon pattern 102P may not lie on the same line. In some cases, the width of the first inorganic pattern 101P may be smaller than the width of the second inorganic pattern 102P. 4 is a plan view schematically illustrating a display device according to another embodiment of the present invention.

The display apparatus 2000 of this embodiment includes a peripheral area PA and a center area CA on a substrate 200 , and the center area CA includes a display area DA and a non-display area NDA. and the peripheral area PA includes at least the pad peripheral area PPA.

For convenience of description, different points from the above-described embodiment will be mainly described.

The pad peripheral area PPA includes an insulating pattern IP and a dummy insulating pattern DIP.

The insulating pattern IP is provided to correspond to the pads 206a, and the insulating pattern IP is spaced apart from each other with a slit S interposed therebetween.

The dummy insulating pattern DIP does not correspond to the pads 206a, and the dummy insulating pattern DIP is disposed to be spaced apart from each other with the dummy slit DS interposed therebetween.

Specifically, the insulating pattern IP is disposed to overlap the extension line of the pad 206a. Through this, when a wiring (not shown) is connected to the pad 206a, the wiring (not shown) is prevented from coming into contact with a foreign material on the substrate 200 , in particular, a residual metal film or metal particles, thereby fundamentally blocking short circuit defects.

The dummy insulating pattern DIP may cover foreign substances or particles remaining when various members are formed on the substrate 200 to prevent defects due to foreign substances. In addition, the dummy insulating pattern DIP and the dummy slit DS may perform a stress relief function when the display device 2000 including the substrate 200 is bent or deformed, such as bending.

Since the contents of other configurations of the display device 2000 are the same as those of the display device 1000 and optional embodiments thereof, they can be applied as they are, and a more detailed description of the display device 2000 will be omitted.

5 to 14 are cross-sectional views showing other embodiments taken along a-a' of FIG. 2 .

Referring to the embodiment of FIG. 5 , the slit S is a type of opening exposing at least a portion of the upper surface of the substrate 100 . In the embodiment of FIG. 5 , the insulating patterns IP are disposed to be spaced apart from each other with a slit S that exposes at least a portion of the substrate 100 therebetween.

Meanwhile, the insulating pattern IP includes a first inorganic pattern 101P and a second inorganic pattern 102P sequentially from the substrate 100 in the same manner as in the embodiment of FIG. 3 . As described above, as an optional embodiment, one or more inorganic layers may be formed on the central area CA of the substrate 100 . In this case, the plurality of insulating patterns IP may be connected to the inorganic layer of the pad area PDA. have. However, the present embodiment is not limited thereto, and the insulating pattern IP may be formed separately from the inorganic layer formed in the central region CA.

A specific example in which the first inorganic pattern 101P and the second inorganic pattern 102P are formed is the same as described in the above-described embodiment. That is, the exemplary contents of the connection relationship with the inorganic layers formed in the central area CA may be applied to all of the descriptions in the above-described embodiments.

Also, the second inorganic pattern 102P may have a form in which a plurality of inorganic pattern layers 103P and 105P are stacked.

Unlike the embodiment of FIG. 3 , in the embodiment of FIG. 5 , a top surface of the first inorganic pattern 101P of the insulating pattern IP is partially exposed. In other words, the side cross-section of the first weapon pattern 101P and the side cross-section of the second weapon pattern 102P are not located on the same line, and the second weapon pattern 102P is the upper surface of the first weapon pattern 101P. Only part of it is covered.

In the case of the embodiment of FIG. 5 , a metal residual film may remain in the exposed area of the exposed upper surface of the first inorganic pattern 101P, but short circuit failure of the pad part 106a may be prevented. Referring to the embodiment of FIG. 6 , the slit S is a type of opening exposing the top surface of the first inorganic layer 101 . In the embodiment of FIG. 6 , the insulating patterns IP are disposed to be spaced apart from each other with the slit S exposing the upper surface of the first inorganic layer 101 therebetween.

Meanwhile, the insulating pattern IP includes the second inorganic pattern 102P on the first inorganic layer 101 . As described above, as an optional embodiment, one or more inorganic layers may be formed on the central area CA on the substrate 100 . In this case, the plurality of insulating patterns IP may be connected to the inorganic layer of the pad area PDA. have. However, the present embodiment is not limited thereto, and the insulating pattern IP may be formed separately from the inorganic layer formed in the central region CA.

A specific example in which the second inorganic pattern 102P is formed is the same as described in the above-described embodiment. That is, the exemplary contents of the connection relationship with the inorganic layers formed in the central area CA may be applied to all of the descriptions in the above-described embodiments. In addition, the second inorganic pattern 102P includes a form in which a plurality of inorganic pattern layers 103P and 105P are stacked.

In the embodiment of FIG. 6 , the first inorganic layer 101 is formed in the pad peripheral area PPA, and the insulating pattern IP includes only the second inorganic pattern 102P, so that the first inorganic layer 101 is Since the step of patterning can be omitted, the process is simplified.

Referring to the embodiment of FIG. 7 , the slit S is a type of opening exposing the top surface of the first inorganic layer 101 . In the embodiment of FIG. 7 , the insulating patterns IP are disposed to be spaced apart from each other with the slit S exposing the upper surface of the first inorganic layer 101 interposed therebetween.

Meanwhile, the insulating pattern IP includes the second inorganic pattern 102P on the first inorganic layer 101 . As described above, as an optional embodiment, one or more inorganic layers may be formed on the central area CA of the substrate 100 . In this case, the plurality of insulating patterns IP may be connected to the inorganic layer of the pad area PDA. have. However, the present embodiment is not limited thereto, and the insulating pattern IP may be formed separately from the inorganic layer formed in the central region CA.

A specific example in which the second inorganic pattern 102P is formed is the same as described in the above-described embodiment. That is, the exemplary contents of the connection relationship with the inorganic layers formed in the central area CA may be applied to all of the descriptions in the above-described embodiments. In addition, the second inorganic pattern 102P includes a form in which a plurality of inorganic pattern layers 103P and 105P are stacked.

In the embodiment of FIG. 7 , the first inorganic layer 101 has a predetermined groove between the second inorganic patterns 102P. The groove may have various shapes. As shown in FIG. 7 , a boundary line of the groove may be spaced apart from the second inorganic pattern 102P.

However, the present embodiment is not limited thereto. That is, as shown in FIG. 8 , the boundary line of the groove of the first inorganic layer 101 may be connected to the side surface of the second inorganic pattern 102P.

In addition, grooves may be formed in the first inorganic layer 101 in various other forms. For example, a boundary line of the grooves of the first inorganic layer 101 may be formed to pass through the side surface of the second inorganic pattern 102P. it might be

7 and 8 , the upper surface of the first inorganic layer 101 positioned in the slit S is partially removed. Accordingly, the thickness of the first inorganic layer 101 in the predetermined region corresponding to the slit S is smaller than the thickness of the first inorganic layer corresponding to the insulating pattern IP. 9 to 14 , an organic layer 107P covering the insulating pattern IP is further provided with respect to the embodiments of FIGS. 3 and 5 to 8 .

In detail, referring to FIG. 9 , an organic layer 107P covering the upper surface and side surfaces of the insulating pattern IP is further provided in the embodiment of FIG. 3 . Referring to FIG. 10 , the insulating pattern IP in the embodiment of FIG. 5 . An organic layer 107P is further provided to cover the top and side surfaces of the second inorganic pattern 102P included in the . Referring to FIG. 11 , an organic layer 107P covering upper surfaces and side surfaces of the first inorganic pattern 101P and the second inorganic pattern 102P included in the insulating pattern IP in the embodiment of FIG. 5 is further provided.

Referring to FIG. 12 , an organic layer 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP in the embodiment of FIG. 6 is further provided. Referring to FIG. 13 , an organic layer 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP in the embodiment of FIG. 7 is further provided.

Referring to FIG. 14 , an organic layer 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP in the embodiment of FIG. 8 is further provided.

As an optional embodiment, the organic layer 107P may be formed to be connected to one or more organic layers provided in the central area CA. As a specific example, the organic layer 107P may be provided in the central region CA to cover the thin film transistor and may be connected to a passivation layer for planarizing irregularities by the thin film transistor. In another embodiment, the organic layer 107P may be connected to a pixel defining layer that covers a portion of a pixel electrode provided on the passivation layer and defines a light emitting area. That is, when the passivation layer or the pixel defining layer is formed in the central region CA, the addition of the process can be prevented by forming the organic layer 107P together.

9 to 14 , even if a residual metal film remains on the side surface of the second inorganic pattern 102P, the organic layer 107P covers the metal residual film, thereby blocking the possibility that a short circuit may occur due to the remaining metal film. has a characteristic that

15 and 16 are views illustrating other modified examples of FIG. 2 . For convenience of description, different points from the above-described embodiment will be mainly described.

Referring to FIG. 15 , the plurality of pads 106a ′ have an inclined shape. Specifically, an angle θ ₁ between the extension line of the pad 106a ′, for example, the center line of the pad 106 ′ and the edge of the substrate, may be less than 90 degrees. Also, an angle θ ₂ between the boundary line of the slit S′ or the center line of the slit S′ and the edge of the substrate may be less than 90 degrees.

As an alternative embodiment, the angle θ ₁ may be equal to the angle θ ₂ . That is, through this, the pad 106a ′ and the insulating pattern IP are formed side by side.

Although not shown, the inclined shape of the plurality of pads 106a ′ may vary. That is, the angle θ ₁ may be greater than 90 degrees. In this case, the angle θ ₂ may also be greater than 90 degrees.

Also, the inclined shape of the plurality of pads 106a' formed in one area of the substrate and the inclined shape of the plurality of pads 106a' formed in the other area of the substrate may be different. That is, a plurality of angles θ ₁ may exist on one substrate instead of one.

Also, as shown in FIG. 16 , a dummy insulating pattern DIP″ and a dummy slit DS″ may be further formed together with the plurality of pads 106a″ and the plurality of slits S″. The dummy insulating pattern DIP" does not correspond to the pads 106"a, and the dummy insulating pattern DIP" is spaced apart from each other with the dummy slit DS" interposed therebetween.

The inclined shape of the plurality of pads 106a″ and the plurality of slits S″ is the same as that of the embodiment of FIG. 15 , and detailed description thereof will be omitted.

At this time, the dummy slit DS″ is also formed in an inclined shape like the slit S″. FIGS. 17 to 25 show an embodiment of the method of manufacturing the display device of FIG. 1 taken along the line b-b′. It is a cross-sectional view sequentially shown based on . Specifically, FIGS. 17 to 25 include a process of manufacturing the insulating pattern IP according to the embodiment of FIG. 3 .

Referring to FIG. 17 , first, a substrate 100 is prepared. The substrate 100 may be formed of various materials, and as an optional embodiment, as described above, may be formed of a flexible material. A first inorganic layer 101 is formed on the substrate 100 . The first inorganic layer 101 may be functionally, for example, a buffer layer, and the buffer layer is the central area CA of the substrate 100 including the display area DA, the non-display area NDA, and the pad area PDA. ) and the peripheral area PA around the cutting line CL including the pad peripheral area PPA. That is, the buffer layer may be all formed on the upper surface of the substrate 100 . Here, the substrate 100 may be a substrate 100 on which one display apparatus 1000 is to be formed, or may be a mother substrate on which a plurality of display apparatuses 1000 are formed.

The buffer layer may be formed by various deposition methods such as plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure CVD (APCVD), and low pressure CVD (LPCVD) using SiO ₂ and/or SiNx.

Referring to FIG. 18 , a thin film transistor is formed in the display area DA on the buffer layer. The thin film transistor TFT formed on the display area DA functions as a part of the pixel circuit. However, the thin film transistor TFT may also be formed on the non-display area NDA. The thin film transistor TFT formed on the non-display area NDA functions as a part of a circuit included in the driver.

Hereinafter, a case in which the thin film transistor TFT is a top gate type including the active layer 102 , the gate electrode 104 , and the source and drain electrodes 106s and d sequentially from the buffer layer is illustrated. However, the present invention is not limited thereto, and various types of thin film transistors (TFTs) such as a bottom gate type may be employed.

An active layer 102 (active layer) is formed on the buffer layer in the form of a pattern. The active layer 102 includes a semiconductor material, and may include, for example, amorphous silicon or poly crystalline silicon. However, the present invention is not limited thereto, and the active layer 102 may contain various materials. In an alternative embodiment, the active layer 102 may contain an organic semiconductor material.

As another alternative embodiment, the active layer 102 may contain an oxide semiconductor material. For example, the active layer 102 is GIZO[(In ₂ O ₃ )a(Ga ₂ O ₃ )b(ZnO)c] (a, b, and c each satisfy the conditions of a≥0, b≥0, c>0). mistakes to satisfy). In addition to GIZO, the active layer 102 may be formed of 12, 13 such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), or hafnium (Hf). , an oxide of a material selected from group 14 metal elements and combinations thereof.

As described above, the present embodiment may include various types of thin film transistors, for example, a thin film transistor having a bottom gate structure. In particular, when the active layer 102 contains an oxide or contains amorphous silicon, the thin film transistor having a bottom gate structure may be provided.

The thin film transistor having such a bottom gate structure may have various forms. For example, a gate electrode is formed on the substrate 100 , an active layer is formed on the gate electrode, and a source electrode and a drain electrode are formed on the active layer. This can be placed Also, as another example, a gate electrode may be formed on a substrate, a source electrode and a drain electrode may be formed on the gate electrode, and an active layer may be formed on the source electrode and the drain electrode. In this case, an insulating layer, for example, an inorganic layer, may be formed adjacent to at least one of the gate electrode, the active layer, the source electrode, and the drain electrode.

The active layer 102 includes a source region and a drain region in contact with the source electrode 106s and the drain electrode 106d, respectively, and a channel region positioned therebetween. When the active layer 102 includes amorphous silicon or polycrystalline silicon, the source region and the drain region may be doped with impurities if necessary.

A gate insulating layer 103 is formed on the active layer 102 . The gate insulating layer 103 may be formed of a multilayer or a single layer of an inorganic material such as silicon oxide and/or silicon nitride. The gate insulating layer 103 insulates the active layer 102 and the gate electrode 104 .

The gate insulating layer 103 may be a single layer forming the second inorganic pattern 102P, and the gate insulating layer 103 is a substrate including a display area DA, a non-display area NDA, and a pad area PDA. It may be formed on both the central area CA of 100 and the peripheral area PA around the cutting line CL including the pad peripheral area PPA. That is, the gate insulating layer 103 may be formed on the entire surface of the substrate 100 . Here, the substrate 100 may be a substrate 100 on which one display apparatus 1000 is to be formed, or may be a mother substrate on which a plurality of display apparatuses 1000 are formed.

The gate electrode 104 is formed on the gate insulating layer 103 in a pattern shape. The gate electrode 104 is connected to a gate line (not shown) for applying an on/off signal to the thin film transistor TFT. The gate electrode 104 may be made of a low-resistance metal material, for example, a layer made of a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. can

An inter layer dielectric layer 105 is formed on the gate electrode 104 . The interlayer insulating film 105 serves to insulate the source electrode 106s and the drain electrode 106d from the gate electrode 104 . The interlayer insulating layer 105 may be formed of a multilayer or a single layer made of an inorganic material. For example, the inorganic material may be a metal oxide or a metal nitride, specifically, the inorganic material is silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide ( TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZrO ₂ ) and the like may be included.

The interlayer insulating layer 105 may be one layer forming the second inorganic pattern 102P, and the interlayer insulating layer 105 is the substrate 100 including a display area DA, a non-display area NDA, and a pad area PDA. ) may be formed on both the central area CA and the peripheral area PA around the cutting line CL including the pad peripheral area PPA. That is, the interlayer insulating layer 105 may be formed on the entire surface of the substrate 100 . Here, the substrate 100 may be a substrate 100 on which one display apparatus 1000 is to be formed, or may be a mother substrate on which a plurality of display apparatuses 1000 are formed.

Next, referring to FIG. 19 , a contact hole CNT is formed in the gate insulating layer 103 and the interlayer insulating layer 105 , and the peripheral area PA is simultaneously patterned.

The contact hole CNT is formed to expose a predetermined surface of the active layer 102 . The contact hole CNT allows the source electrode 106s and the drain electrode 106d to be electrically connected to the active layer 102 later. Meanwhile, when the contact hole CNT is formed, the gate insulating layer 103 and the interlayer insulating layer 105 of the peripheral area PA are removed and the insulating pattern IP of the pad peripheral area PPA is formed at the same time. That is, the gate insulating layer 103 and the interlayer insulating layer 105 provided in the peripheral area PA around the cut line CL are removed together, and the slit for forming the insulating pattern IP is formed in the pad peripheral area PPA. S) is formed. As described above, according to the exemplary embodiment of the present invention, since a separate process for patterning the gate insulating layer 103 and the interlayer insulating layer 105 provided in the peripheral area PA is not required, the process can be simplified.

Next, referring to FIG. 20 , a metal layer 106f for forming the source and drain electrodes 106s and d and the pad 106a is formed on the interlayer insulating layer 105 . The metal layer 106f may be formed as a multi-layer or single layer formed of a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like having low electrical resistance.

Next, referring to FIG. 21 , the metal layer 106f is patterned to form the source and drain electrodes 106s and d and the pad 106a. The source electrode 106s and the drain electrode 106d contact the source region and the drain region of the active layer 102 through the contact hole CNT formed in the interlayer insulating layer 105 and the gate insulating layer 103 , respectively. A pad 106a is formed in the pad area PDA.

Meanwhile, the metal layer may not be completely removed from the side surfaces of the inorganic layers in the pad peripheral area PPA, for example, the side surfaces of the gate insulating layer 103 and the interlayer insulating layer 105 , and a metal residue 106p may remain. The metal residue 106p may cause a short-circuit failure when the circuit board 200 on which the external circuit is mounted is subsequently bonded to the pad 106a.

Referring to FIG. 22 , a passivation layer 107 is formed to cover the thin film transistor TFT.

The passivation layer 107 eliminates a step difference resulting from the thin film transistor TFT and flattens the top surface, thereby preventing defects from occurring in the organic light emitting diode OLED due to lower concavities and convexities. The passivation film 107 may be formed as a single layer or a multilayer film made of an organic material. Organic materials include general-purpose polymers such as Polymethylmethacrylate (PMMA) or Polystylene (PS), polymer derivatives with phenolic groups, acrylic polymers, imide-based polymers, arylether-based polymers, amide-based polymers, fluorine-based polymers, and p-xylene-based polymers. Polymers, vinyl alcohol-based polymers, and blends thereof may be included. In addition, the passivation film 107 may be formed of a composite laminate of an inorganic insulating film and an organic insulating film.

Next, referring to FIGS. 23 to 26 , an organic light emitting diode (OLED) is formed on the passivation layer 107 .

Specifically, a hole 107a exposing one of the source and drain electrodes 106s and d and an opening 107b exposing the top surface of the pad 106a are formed in the passivation layer 107 . The hole 107a serves as a passage for electrically connecting an organic light emitting device to be formed later and the thin film transistor TFT. Meanwhile, the opening 107b exposes the pad 106a and becomes a passage for electrically connecting the circuit board 200 on which an external circuit is mounted thereafter and the pad 106a.

Next, an organic light emitting diode (OLED) is formed on the passivation layer 107 . In detail, the organic light emitting diode OLED includes a pixel electrode 111 , an opposite electrode 112 opposed thereto, and an intermediate layer 113 interposed between both electrodes. According to the emission direction of the organic light emitting diode (OLED), the display device is classified into a bottom emission type, a top emission type, and a dual emission type. The pixel electrode 111 is provided as a light-transmitting electrode, and the opposite electrode 112 is provided as a reflective electrode. In the top emission type, the pixel electrode 111 is provided as a reflective electrode and the opposite electrode 112 is provided as a transflective electrode. In the double-sided emission type, both the pixel electrode 111 and the counter electrode 112 are provided as light-transmitting electrodes. In this embodiment, it is illustrated that the organic light emitting diode display is a top emission type.

First, referring to FIG. 23 , the pixel electrode 111 may be patterned and formed in an island shape. In addition, the pixel electrode 111 is formed to contact the thin film transistor TFT included in the pixel circuit through a hole in the passivation layer 107 . Meanwhile, the pixel electrode 111 may be disposed to overlap the thin film transistor TFT so as to cover the lower pixel circuit.

The pixel electrode 111 includes a reflective electrode layer in addition to the transparent electrode layer so that light can be reflected in the direction of the opposite electrode 112 . When the pixel electrode 111 functions as an anode, the transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin oxide (ITO) having a high work function; At least one selected from the group consisting of transparent conductive oxides such as indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO) may be included. . The reflective electrode layer may include a metal having high reflectance, such as silver (Ag).

Then, a pixel defining layer 109 is formed on the passivation layer 107 . The pixel defining layer 109 may be formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin by spin coating or the like. The pixel defining layer 109 includes an opening 109a that covers an edge of the pixel electrode 111 and opens at least a central portion of the pixel electrode 111 . The region defined by the opening 109a corresponds to the light emitting region, and the intermediate layer 113 is formed.

Next, referring to FIG. 24 , the first inorganic layer 101 in the peripheral area PA is patterned.

Although not shown, the first inorganic layer 101 exposed around the cutting line CL is removed, and in the case of the pad peripheral area PPA, a first slit S is formed through which the top surface of the substrate 100 is exposed. The inorganic film 101 is removed. Accordingly, an insulating pattern IP including the first inorganic pattern 101P and the second inorganic pattern 102P with the slit S through which the substrate 100 is exposed is formed in the pad peripheral area PPA. can

When the first inorganic layer 101 is patterned, the side ends of the gate insulating layer 103 and the interlayer insulating layer 105 may coincide with the side ends of the patterned first inorganic layer 101 . In this case, the metal residual layer formed on the side surface of the second inorganic pattern 102P may be removed together during the patterning process of the first inorganic layer 101 . As described above, the metal remaining film in the pad peripheral area PPA is removed, thereby preventing short circuit defects and manufacturing the highly reliable display apparatus 1000 .

In the present embodiment, the insulating pattern IP may be formed using the first inorganic layer 101 , the gate insulating layer 103 , and the interlayer insulating layer 105 serving as a buffer layer. Although not shown, when the thin film transistor of this embodiment has a bottom gate structure as described above, for example, when an active layer containing an oxide semiconductor material is formed, the first inorganic film 101 functioning as a buffer film, and the active layer The insulating pattern IP may be formed using a gate insulating layer to be disposed between the and the gate electrode, and a protective layer to be formed on the source electrode and the drain electrode.

In addition, in addition, the present embodiment may include various types of thin film transistors, and in that case, various types of insulating films adjacent to or in direct contact with the active layer, the gate electrode, the source electrode and the drain electrode are formed in an extended form for insulation A pattern IP may be formed.

Next, referring to FIG. 25 , the intermediate layer 113 is formed in the light emitting region. The intermediate layer 113 includes an organic light emitting layer emitting red, green, or blue light, and the organic light emitting layer may use a low molecular weight organic material or a high molecular weight organic material. When the organic light emitting layer is a low molecular organic layer formed of a low molecular weight organic material, a hole transport layer (HTL) and a hole injection layer (HIL) are positioned in the direction of the pixel electrode 111 with the organic light emitting layer as the center, and face each other. An electron transport layer (ETL) and an electron injection layer (EIL) are stacked in the direction of the electrode 112 . Of course, various layers other than the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be stacked as needed.

Meanwhile, the organic light emitting layer may be separately formed for each organic light emitting device. In this case, each of the organic light emitting devices may emit red, green, and blue light, respectively. However, the present invention is not limited thereto, and the organic light emitting layer may be formed in common throughout the organic light emitting device. For example, a plurality of organic light emitting layers emitting red, green, and blue light may be vertically stacked or formed to be mixed to emit white light. Of course, the combination of colors for emitting white light is not limited to the above. Meanwhile, in this case, a color conversion layer or a color filter for converting the emitted white light into a predetermined color may be separately provided.

Next, the counter electrode 112 is formed to cover the entire surface of the substrate 100 . The counter electrode 112 may be made of a conductive inorganic material. When the counter electrode 112 functions as a cathode, lithium (Li), calcium (Ca), lithium fluoride/calcium (LiF/Ca), lithium fluoride/aluminum (LiF/Al), aluminum (Al) having a small work function , magnesium (Mg), silver (Ag), and the like, and the metals may be formed as a thin film to enable light transmission. The opposite electrode 112 may be formed as a common electrode over the entire display area DA in which an image is displayed. In this case, the counter electrode 112 may be formed by an evaporation process that does not damage the intermediate layer 113 . Meanwhile, the polarities of the pixel electrode 111 and the counter electrode 112 may be opposite to each other. By forming the counter electrode 112 , the display apparatus 1000 is finally completed.

Although not shown, an insulating capping layer may be further formed on the opposite electrode 112 . The insulating capping layer maintains the work function of the counter electrode 112 when forming the encapsulation thin film using a sputtering process or a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and is formed on the intermediate layer 113 . The organic matter it contains can help prevent damage. The insulating capping layer is an optional configuration and may not be provided.

Although not shown next, the organic light emitting diode (OLED) may be sealed by a sealing film to prevent penetration of external moisture and air. The sealing film may be in the form of a thin film, for example, a structure in which a film made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx) and a film made of an organic material such as epoxy or polyimide are alternately formed. can take However, the sealing film is not limited thereto and may include a film made of low melting glass (low melting galss).

By sealing the organic light emitting element with such a thin film sealing film, the display apparatus 1000 has a flexible characteristic as a whole. Accordingly, the display apparatus 1000 according to an embodiment of the present invention can be bent, folded, and rolled up.

However, the present embodiment is not limited thereto, and an encapsulation member made of various other materials may be formed on the organic light emitting diode (OLED).

26 and 27 are cross-sectional views sequentially showing another embodiment of the method of manufacturing the display device of FIG. 1 taken along the line b-b'.

26 and 27 include a process of manufacturing the insulating pattern IP according to the embodiment of FIG. 5 .

Referring to FIG. 26 , when the first inorganic layer 101 of the peripheral area PA is patterned, the gate insulating layer 103 and the interlayer insulating layer 105 do not cover the upper surface of the first inorganic layer 101 , that is, The first inorganic layer 101 may protrude from the ends of the gate insulating layer 103 and the interlayer insulating layer 105 .

Meanwhile, in the case of the process of manufacturing the insulating pattern IP according to the embodiment of FIG. 6 , the process of patterning the first inorganic layer 101 among the processes of FIGS. 17 to 25 is omitted, and thus the overlapping description will be omitted. do it with

On the other hand, in the case of the process of manufacturing the insulating pattern IP according to the embodiments of FIGS. 7 and 8 , the process of patterning only a part of the first inorganic layer 101 among the processes of FIGS. 17 to 25 is substituted. A description will be omitted.

28 to 31 are cross-sectional views sequentially showing another embodiment of the method of manufacturing the display device of FIG. 1 taken along the line b-b'. 28 to 31 include a process of manufacturing the insulating pattern IP according to the embodiment of FIG. 10 .

Referring to FIG. 28 , when the passivation layer 107 is formed, it is characterized in that it covers both the top and side surfaces of the second inorganic pattern 102P in the pad peripheral area PPA. From this, there is an effect of preventing short circuit defects by covering the remaining metal film remaining on the side surface of the second inorganic pattern 102P with the passivation film 107 .

FIG. 29 is a process of forming a pixel defining layer similar to FIG. 23 , and FIG. 30 is a process of patterning the first inorganic layer 101 in the peripheral area PA similarly to FIG. 24 . In FIG. 30 , the side cross-sections of the gate insulating film 103 and the interlayer insulating film 105 and the side cross-sections of the first inorganic film 101 do not coincide with each other so that the top surface of the first inorganic film 101 is partially exposed, unlike in FIG. 24 . pattern so as not to FIG. 31 is a process of forming an intermediate layer and a counter electrode similar to FIG. 25 .

Meanwhile, in the case of the embodiments of FIGS. 9, 11, 12, 13, and 14, only the process in which the organic layer 107P covers at least the second inorganic pattern 102P is further added as shown in FIGS. 28 to 31 . , the overlapping description will be omitted.

Hereinafter, features of the display apparatus 1000 according to an embodiment of the present invention will be described in detail with reference to FIGS. 32 to 36 .

First, FIG. 32 is a plan view schematically illustrating a display apparatus 1000 according to a comparative example of the present invention. FIG. 33 is an enlarged schematic plan view of VII of FIG. 32 .

32 illustrates a state in which the circuit board 200 on which an external circuit is mounted is bonded to the pad 106a. In the circuit board 200 , a chip for transmitting various power sources or electric signals is mounted in the display area DA, and the chip is not shown in FIG. 32 . The circuit board 200 includes a wiring 106l for connecting the chip and the pad 106a of the substrate 100. When the wiring 106l is bonded to the pad 106a, various power sources or electricity output from the chip are included. A signal is transmitted to the display area DA through the pad 106a.

Referring to FIG. 33 , when the insulating pattern IP and the slit S are not provided in the pad peripheral area PPA, a residual metal film may remain when a foreign material, a particle, or a metal film is formed. Accordingly, there is a problem in that the wirings 106l are electrically short-circuited, resulting in a short circuit failure.

34 is a plan view schematically illustrating a display apparatus 1000 according to an embodiment of the present invention, FIG. 35 is an enlarged schematic plan view of IX of FIG. 34, and FIG. 36 is a line Q-Q' of FIG. It is a cross-sectional view taken along

In the case of FIGS. 34 to 36 , the circuit board 200 provided with the wiring 106l is the same, but comparison in that the insulating pattern IP and the slit S are provided in the pad peripheral area PPA of the substrate 100 . different from yes

Referring to FIG. 35 , since the insulating pattern IP and the slit S are provided in the pad peripheral area PPA, even if the metal residual film remains on the side of the inorganic film removed to form the slit S, the metal residual film Accordingly, the wirings 106l are not electrically shorted. That is, the wiring 106l is provided to correspond to the insulating pattern IP, and the slit S is disposed between the wiring 106l and the wiring 106l. Specifically, as shown in FIG. 36 , the wirings 106l may be formed to extend above the insulating pattern IP, for example, on the second inorganic pattern 102P of the insulating pattern IP.

Therefore, there is an effect that short-circuit defects like the comparative example do not occur.

As such, the present invention has been described with reference to one embodiment shown in the drawings, but this is merely exemplary, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be defined by the technical spirit of the appended claims.

100: substrate 101P: first weapon pattern
101: first inorganic film 102P: second weapon pattern
102: active layer 103P: gate insulating film pattern
103: gate insulating film 104: gate electrode
105P: interlayer insulating film pattern 105: interlayer insulating film
106f: metal layer 106d: drain electrode
106l: wiring 106s: source electrode
106a: pad 107b: opening
107P: organic film 107: passivation film
107a: hole 109a: opening
109: pixel defining layer 111: pixel electrode
112: counter electrode 113: intermediate layer
200: circuit board

Claims (13)

Board;
a display area positioned on the substrate and including a display element displaying an image;
a non-display area positioned outside the display area;
a plurality of conductive wires positioned in the non-display area and spaced apart from each other;
a first inorganic film positioned between the substrate and the plurality of conductive wirings; and
a second inorganic film positioned between the first inorganic film and the plurality of conductive wires;
The second inorganic layer includes a plurality of slits or openings exposing a top surface of the first inorganic layer by removing a portion of the second inorganic layer,
wherein the plurality of slits or openings are located corresponding to regions between the plurality of conductive wirings and are not located in regions in which the plurality of conductive wirings extend. The method of claim 1,
The materials of the first inorganic film and the second inorganic film are different from each other. 3. The method of claim 2,
The first inorganic film comprises silicon oxide,
The second inorganic layer comprises silicon nitride, a display device. delete The method of claim 1,
A display device, wherein a first thickness of the first inorganic film at a position corresponding to the plurality of slits or openings is the same as a second thickness of the first inorganic film at a position corresponding to the plurality of conductive wirings. The method of claim 1,
The display device of claim 1, wherein a first thickness of the first inorganic film at a position corresponding to the plurality of slits or openings is thinner than a second thickness of the first inorganic film at a position corresponding to the plurality of conductive wirings. The method of claim 1,
The second inorganic layer includes a plurality of insulating layers sequentially stacked in a direction away from the substrate,
The plurality of slits or openings are formed by removing a portion of the uppermost layer of the plurality of insulating layers. The method of claim 1,
The plurality of conductive wires includes a first conductive wire and a second conductive wire closest to the first conductive wire,
A distance between the first conductive line and the second conductive line is greater than a width of a slit or an opening disposed at a position corresponding to the position between the first conductive line and the second conductive line. 9. The method of claim 8,
A length of the slit or opening in an extension direction of the first conductive wiring and the second conductive wiring is greater than a width of the slit or opening. The method of claim 1,
and the first inorganic layer extends from the display area to the non-display area. The method of claim 1,
The second inorganic layer extends from the display area to the non-display area. The method of claim 1,
The substrate includes a flexible material, the display device. The method of claim 1,
and a thin film transistor positioned in the display area on the substrate and including an active layer, a gate electrode, and source and drain electrodes;
The plurality of conductive wirings include the same material as the source and drain electrodes,
The second inorganic layer includes the same material as the interlayer insulating layer positioned between the gate electrode and the source and drain electrodes.

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