KR20200094123A - Display device and method of manufacturing the same - Google Patents

Abstract

One embodiment of the present invention discloses a display device. The display device includes a central area having a display area on a substrate at least and a peripheral area disposed around the central area. A plurality of pads arranged in one direction are formed in the central area. In an area adjacent to the pads at least of the peripheral area, insulating patterns corresponding to the plurality of pads and a slit in a form that the slit is formed between the insulating patterns and at least a part of an insulating material forming the insulating patterns is removed are formed.

Description

Display device and method of manufacturing the same}

Embodiments of the present invention relates to a display device and a manufacturing method thereof, and more particularly, to a display device using a flexible substrate and a manufacturing method thereof.

In the display field, a display device using a flexible substrate that is light, thin, and has excellent impact resistance has been developed. A display device using a flexible substrate is formed by cutting from a mother glass. In detail, a plurality of display devices may be formed on the mother substrate. These display devices are separated into individual display devices by, for example, cutting the display substrate along a cutting line using a press.

However, when it is cut by a physical pressure such as a press, the periphery of the cutting line of the display substrate is crushed or distorted. Due to such distortion or distortion, each layer on the display substrate is lifted or cracked, resulting in a problem of line disconnection. In addition, there is a problem that the reliability of the display device is lowered because layers on the display substrate around the cutting line are separated during cutting.

To solve this problem, attempts have been made to expose the display substrate by removing a layer around the cutting line on the display substrate. However, when a metal residual film exists in a step formed by removing a layer around the cutting line, the lines and the residual film included in the circuit board are electrically connected when the pads formed on the display substrate and the circuit board equipped with the external circuit are connected. There is a problem in that a short occurs due to connection.

Embodiments of the present invention provide a display device using a flexible substrate and a method for manufacturing the same.

One embodiment of the present invention relates to a display device including a central area having at least a display area on a substrate and a peripheral area disposed around the central area, wherein the central area includes a plurality of pads arranged in one direction. The insulating pattern corresponding to the plurality of pads and at least a part of the insulating material formed between the insulating patterns and forming the insulating pattern are removed from at least a portion of the peripheral region adjacent to the pads. Disclosed is a display device in which a slit is formed.

In this embodiment, the insulating pattern may overlap at least the extension lines of the pads.

In this embodiment, the insulating pattern may include an inorganic material.

In the present exemplary embodiment, an organic layer formed to cover at least one region of a top surface of the insulating pattern and a side surface of the insulating pattern may be further included.

In this embodiment, the peripheral area may include an area where the upper surface of the substrate is exposed to at least one area.

In this embodiment, the peripheral area includes a pad peripheral area adjacent to the pads and the plurality of insulating patterns and slits are disposed, and an area where the upper surface of the substrate is exposed is formed to be adjacent to the pad peripheral area. Can.

In this embodiment, an area where the upper surface of the substrate is exposed may be formed to be adjacent to a plurality of edges of the edges of the substrate.

In this embodiment, the edge of the substrate may be defined as a cutting line.

In this embodiment, one or more inorganic films may be formed in the central region of the substrate.

In this embodiment, the insulating patterns may have a form connected to the inorganic film.

In this embodiment, the plurality of pads may be formed on the inorganic film.

In this embodiment, the inorganic film may have a form in which a plurality of layers are stacked.

In this embodiment, the insulating pattern may have a form in which a plurality of inorganic patterns are stacked.

In this embodiment, the insulating pattern may include a first inorganic pattern and a second inorganic pattern formed on the first inorganic pattern.

In this embodiment, the insulating pattern may be formed so that the upper surface of the first inorganic pattern is completely covered by the second inorganic pattern.

In this embodiment, the insulating pattern may be formed to have an area where the top surface of the first inorganic pattern is exposed.

In this embodiment, the insulating layer may further include an organic layer covering at least an upper surface and a side surface of the second inorganic pattern.

In this embodiment, a first inorganic film may be formed between the insulating pattern and the substrate.

In this embodiment, a portion of the first inorganic film may be removed so that a groove is formed in an area of the first inorganic film overlapping the slit.

In the present embodiment, an organic layer covering at least an upper surface and a side surface of the insulating pattern and not covering one region of a region corresponding to a slit among regions of the first inorganic layer may be further included.

In the present embodiment, the central region further includes a plurality of thin film transistors (TFTs) formed on the substrate and formed on the buffer layer and including an active layer, a gate electrode, a source electrode, and a drain electrode, One or more insulating films are formed to be adjacent to the active layer, the gate electrode, the source electrode, and the drain electrode, and the insulating pattern may be formed of the same material as the one or more insulating films.

In this embodiment, the insulating pattern and the at least one insulating layer may be formed to be connected.

In the present embodiment, the at least one insulating film is at least one of a buffer film formed on the substrate, a gate insulating film insulating the gate electrode and the active layer, and an interlayer insulating film insulating the source electrode and the drain electrode and the gate electrode. Can.

In the present embodiment, the one or more insulating films may be at least one of a buffer film formed on the substrate, a gate insulating film insulating the gate electrode and the active layer, and a protective film formed on the source electrode and the drain electrode.

In the present exemplary embodiment, an organic layer covering the thin film transistor may be further included, and the organic layer may be formed to cover at least one region of a top surface and a side surface of the insulating pattern.

In the present embodiment, a pixel electrode that is electrically connected to at least one of the thin film transistors (TFT) and a pixel defining layer that covers a portion of the pixel electrode and defines a light emitting area, wherein the pixel defining layer is an uppermost surface of the insulating pattern. It may be formed to cover at least one area of the side.

In the present exemplary embodiment, an opposite electrode facing the pixel electrode may be further provided, and an organic emission layer may be interposed between the pixel electrode and the opposite electrode.

In this embodiment, the substrate may be a flexible material.

In the present embodiment, at least a part of the dummy insulating pattern that is spaced apart from the insulating pattern and does not correspond to the pads and the dummy insulating patterns formed between the dummy insulating patterns and which forms the dummy insulating pattern is removed from the peripheral region. A dummy slit in the form may be further formed.

In this embodiment, the plurality of pads have an angle formed by an extension line of the plurality of pads with an edge of the substrate is less than 90 degrees or greater than 90 degrees so that the plurality of pads have an inclined shape, and the slits of the slits have an inclined shape. The angle formed by the extension line with the edge of the substrate may be less than 90 degrees or greater than 90 degrees.

In this embodiment, the angle of the extension lines of the plurality of pads with the edge of the substrate may be the same as the angle of the extension lines of the slit with the edge of the substrate.

In this embodiment, the circuit board further includes an external circuit to transmit an electrical signal to the display area, and a plurality of wirings of the circuit board can be connected to the pad.

In this embodiment, a plurality of wirings of the circuit board are disposed on the insulating pattern and may be spaced apart from the slit.

Another embodiment of the present invention relates to a method of manufacturing a display device including a central area having at least a display area on a substrate and a peripheral area disposed around the central area, wherein the central area is arranged in one direction. A plurality of pads are formed, and at least a portion of the peripheral area adjacent to the pads removes at least a portion of an insulating pattern corresponding to the plurality of pads and an insulating material that becomes a material of the insulating pattern between the insulating patterns. Disclosed is a method of manufacturing a display device comprising forming a slit in a shape.

In this embodiment, the step of forming at least one inorganic film in the central region of the substrate, and the insulating pattern may be formed using the inorganic film.

In this embodiment, the inorganic film may be formed by stacking a plurality of layers.

In this embodiment, after performing a step of patterning a layer including at least the uppermost layer among a plurality of layers of the inorganic film to form an insulating pattern spaced apart between the slits, the plurality of pads are applied to the inorganic film. It may include forming on any one of the plurality of layers.

In the present embodiment, after the step of forming the plurality of pads may be performed, a step of removing a layer including at least the lowest layer of the layer of the inorganic layer in a region corresponding to the slit.

In this embodiment, the peripheral area may be formed to include an area in which an upper surface of the substrate is exposed in at least one area.

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

The display device according to the embodiments of the present invention has a feature of eliminating short circuit defects when bonding a circuit board equipped with an external circuit.

1 is a plan view schematically showing a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a schematic plan view enlarging II of FIG. 1.
3 is a cross-sectional view showing an embodiment cut along a-a' in FIG. 2.
4 is a plan view schematically showing a display device according to another embodiment of the present invention.
5 to 14 are cross-sectional views showing other embodiments of FIG. 2 taken along line a-a'.
15 and 16 are views showing other modified examples of FIG. 2. FIGS. 17 to 25 sequentially illustrate an embodiment of a method of manufacturing the display device of FIG. 1 based on a cutting line of b-b'. It is a cross-sectional view.
26 and 27 are cross-sectional views sequentially showing another embodiment of a method of manufacturing the display device of FIG. 1 based on a cutting line of b-b'.
28 to 31 are cross-sectional views sequentially showing another embodiment of a method of manufacturing the display device of FIG. 1 based on a cutting line of b-b'.
32 is a plan view schematically showing a display device according to a comparative example of the present invention.
FIG. 33 is a schematic plan view of FIG. 32 in an enlarged scale.
34 is a plan view schematically illustrating a display device according to an exemplary embodiment of the present invention.
35 is a schematic plan view of FIG. 34 in an enlarged scale.
36 is a cross-sectional view taken along line Q-Q' of FIG. 35.

The present invention can be applied to various transformations and can have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention and methods for achieving them will be clarified with reference to embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms.

In the following examples, terms such as first and second are not used in a limiting sense, but for the purpose of distinguishing one component from other components.

In the following embodiments, the singular expression includes a plural expression unless the context clearly indicates otherwise.

In the examples below, terms such as include or have are meant to mean that features or components described in the specification exist, and do not preclude the possibility of adding one or more other features or components.

In the following embodiments, when a part such as a film, a region, or a component is said to be on or on another part, other films, regions, components, and the like are interposed therebetween, as well as directly above the other part. Also included.

In the drawings, the size of components may be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, the present invention is not necessarily limited to what is shown.

In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes on the Cartesian coordinate system, and can be interpreted in a broad sense including them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

When an embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to that described.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be given the same reference numerals when describing with reference to the drawings, and redundant description thereof will be omitted. .

1 is a plan view schematically showing a display apparatus 1000 according to an embodiment of the present invention, FIG. 2 is a schematic plan view enlarging II of FIG. 1, and FIG. 3 is a-a' of FIG. 2. It is a cross-sectional view showing an embodiment cut along.

Referring to FIG. 1, a display device 1000 according to an embodiment of the present invention includes a substrate 100. The substrate 100 may include various materials. Specifically, the substrate 100 may be formed of glass, metal, or organic materials.

As an optional embodiment, the substrate 100 includes a flexible substrate 100. Here, the flexible substrate 100 refers to a flexible substrate that can be bent, bent, folded, or rolled. The flexible substrate 100 may be made of ultra-thin glass, metal, or plastic. For example, when using plastic, the substrate 100 may be made of polyimide (PI), but this is exemplary and various materials may be applied.

A plurality of display devices 1000 may be formed on the mother substrate, and may be separated into individual display devices 1000 by cutting along the cutting line CL of the substrate 100. In FIG. 1, an individual display device 1000 cut and separated along a cutting line CL is shown. Therefore, the edge of the substrate 100 is defined by the cutting line CL.

The substrate 100 is divided into a peripheral area PA and a central area CA. Specifically, the peripheral area PA is an area around the cut line CL, and the central area CA is an area inside the peripheral area PA.

However, the present embodiment is not limited to this. That is, the cut line CL may not exist. Specifically, one display device 1000 may be formed on one mother substrate, and in this case, the substrate 100 may be one mother substrate, and thus there may be no cut line CL. In this case, the peripheral area PA is an area adjacent to the edge of the substrate 100, and the central area CA can be an area inside the peripheral area PA. For convenience of description, only the case where the cutting line CL is present will be described in the embodiments described below.

The central area CA includes a display area DA and a non-display area NDA.

The display area DA may be provided with one or more display elements (not shown), for example, an organic light emitting diode (OLED), to display an image. Also, a plurality of pixels may be disposed in the display area DA.

The non-display area NDA is formed around the display area DA. Specifically, as shown in FIG. 1, the non-display area NDA may be formed to surround the display area DA. Although not illustrated, as an optional embodiment, the non-display area NDA may be formed to be adjacent to a plurality of side surfaces of the display area DA. Also, as another exemplary embodiment, the non-display area NDA may be formed to be adjacent to one side of the display area DA.

The non-display area NDA includes at least a pad area PDA.

In the pad area PDA, a driver or a plurality of pads 106a is disposed.

In an exemplary embodiment, one or more inorganic films may be formed in the central area CA to prevent moisture permeation or impurity penetration into the display device 1000 through the substrate 100.

The peripheral area PA is an area around the cutting line CL and is provided around the substrate 100 along the cutting line CL.

The peripheral area PA includes an area where the top surface of the substrate 100 is exposed to at least one area and a pad peripheral area PPA.

First, the upper surface of the substrate 100 of the peripheral area PA will be described in relation to the exposed area.

Specifically, as illustrated in FIG. 1, the peripheral area PA may include an area where the upper surface of the substrate 100 is exposed in areas adjacent to the upper edge, the left edge, and the right edge of the substrate 100.

The area where the top surface of the substrate 100 provided in the peripheral area PA is exposed by cutting and separating the individual display device 1000 from the mother substrate is cracked by an insulating film on the substrate 100, particularly inorganic films ( crack).

The width of the area where the upper surface of the substrate 100 provided in the peripheral area PA is exposed may be about several micrometers to hundreds of micrometers from the cutting line CL to the central area CA. For example, the width may be 40 to 500 micrometers, and as another example, it may be 50 to 350 micrometers.

Although not shown, the present invention may not include an area in which the upper surface of the substrate 100 is exposed in the peripheral area PA as an optional embodiment. That is, the peripheral area PA may include only the pad peripheral area PPA, which will be described later, and may be formed such that the upper surface is not exposed to the area adjacent to the edge of the substrate 100.

The pad peripheral area PPA of the peripheral area PA will be described.

The pad peripheral area PPA is an area adjacent to the pad area PDA among the peripheral areas PA.

As an optional embodiment, the pad peripheral area PPA is a circuit board (200 of FIG. 32 to be described later) having an external circuit mounted on the pad 106a, for example, a chip on film (COF), which is bonded. Assuming, the circuit board 200 may be an overlapping region.

The pad peripheral area PPA is provided at a position corresponding to at least a plurality of pads 106a.

The pad peripheral area PPA has an insulating pattern IP. The insulating pattern IP is provided in correspondence with the pads 106a, and the insulating pattern IP is disposed with a slit S therebetween.

Specifically, the insulating pattern IP is disposed to overlap the extension line of the pad 106a. Through this, when the wiring (not shown) of the circuit board (not shown) is connected to the pad 106a, the wiring (not shown) is placed on the upper surface of the insulating pattern IP so that the wiring (not shown) is on the substrate 100. By preventing contact with foreign objects, especially metal residues or metal particles, short defects are fundamentally blocked.

As an optional embodiment, the extension defect of the pad 106a is spaced apart from the slit S, so that the short defect prevention effect can be increased.

This effect will be described in detail through later drawings.

The insulation pattern IP provided in the pad peripheral area PPA will be described in more detail.

2 illustrates a part of the pad area PDA where the pad 106a is disposed, and a part of the pad peripheral area PPA adjacent to the pad area PDA. The plurality of pads 106a are formed on the substrate 100.

At this time, as described above, as an optional embodiment, one or more inorganic films may be formed in the central area CA on the substrate 100. In this case, the inorganic films may also be formed in the pad area PDA, and the pad 106a may be formed in the pad area. (PDA) may be formed on the inorganic film.

The plurality of pads 106a are spaced apart at a predetermined distance and disposed in one direction. As an optional embodiment, the plurality of pads 106a may be arranged in the width direction (the x-axis direction of FIG. 2) of the individual pads 106a.

A plurality of insulating patterns IP are provided in the pad peripheral area PPA. As described above, as an optional embodiment, one or more inorganic films may be formed in the central area CA on the substrate 100. In this case, a plurality of insulating patterns IP may be connected to the inorganic films of the pad area PDA. have. However, the present exemplary embodiment is not limited thereto, and it is needless to say that an insulating pattern IP may be formed separately from the inorganic film formed in the central region CA.

The insulating patterns IP are arranged in a line in a direction corresponding to the plurality of pads 106a. The insulating pattern IP may be made of an inorganic material. When one or more inorganic films formed in the central area CA of the above-described optional embodiment and the insulating pattern IP are connected, the insulating pattern IP has a shape protruding from the pad area PDA to the pad peripheral area PPA. Each of the plurality of insulating patterns IP is provided at a position corresponding to each of the plurality of pads 106a. That is, individual insulating patterns IP are provided at positions where the individual pads 106a extend in the longitudinal direction (y-axis direction in FIG. 2 ). Slits S are provided between adjacent insulating patterns IP, and the insulating patterns IP are spaced apart from each other with the slits S therebetween. Here, the slit (S) means that the narrow and long, slit (S) according to various embodiments to be described later is a type of opening that exposes the top surface of the substrate 100, or than the top surface of the insulating pattern (IP) It may be a type of opening exposing an inorganic film having a low top surface.

Referring to the embodiment of FIG. 3, the slit S is a type of opening exposing the top surface of the substrate 100. In the embodiment of FIG. 3, the insulating patterns IP are spaced apart from each other with slits S exposing the top surface of the substrate 100 therebetween.

Meanwhile, the insulating pattern IP sequentially includes a first inorganic pattern 101P and a second inorganic pattern 102P from the substrate 100. The second inorganic pattern 102P includes a form in which a plurality of inorganic pattern layers 103P and 105P are stacked. The insulating pattern IP shown in FIG. 3 is an example, and the present embodiment is not limited thereto and may have various types of insulating patterns IP. For example, the insulating pattern (IP) may be made of only one layer, may be made of two layers, or may be made of four or more layers.

In addition, as described above, as an optional embodiment, one or more inorganic films may be formed in the central area CA on the substrate 100. In this case, the plurality of insulating patterns IP may be formed from the inorganic films of the pad area PDA. Can be connected. That is, the first inorganic pattern 101P and the second inorganic pattern 102P sequentially stacked of the insulating pattern IP may be connected to inorganic films sequentially formed in the pad area PDA, respectively.

In addition, as an optional embodiment, various inorganic films may be formed in the display area DA of the central area CA. That is, a buffer film (not shown) that may be formed adjacent to the substrate 100, a gate insulating film (not shown) that may be provided in a thin film transistor (TFT) for driving a pixel, an interlayer insulating film ( A plurality of insulating patterns (IP) may be formed to be connected to at least one of various passivation layers (not shown) and other various insulating layers.

For a specific example, the first inorganic pattern 101P is provided in the central region CA to planarize the top surface of the substrate 100 and to provide a barrier film that serves as a barrier to prevent moisture permeation or foreign matter from passing through the substrate 100. It may include a pattern. In addition, the second inorganic pattern 102P is provided in the central region CA, and the pattern 103P of the gate insulating film isolating the active layer and the gate electrode of the thin film transistor from each other, and the interlayer insulating film isolating the gate electrode, the source and drain electrodes from each other It may include a pattern (105P) of (specific content will be described later).

In the embodiment of FIG. 3, the insulating pattern IP has a side cross-section that the upper surface of the first inorganic pattern 101P is completely covered by the second inorganic pattern 102P. In other words, a side end surface of the first inorganic pattern 101P and a side end surface of the second inorganic pattern 102P may be positioned on the same line.

However, this is an exemplary drawing, and this embodiment may include various modifications, for example, when the side cross-section of the first inorganic pattern 101P and the side cross-section of the second inorganic pattern 102P are the same. It can be located on the photo line. As another example, the side cross-section of the first inorganic pattern 101P and the side cross-section of the second inorganic pattern 102P may not be placed on the same line. In some cases, the width of the first inorganic pattern 101P may be smaller than the width of the second inorganic pattern 102P. 4 is a plan view schematically showing a display device according to another embodiment of the present invention.

The display device 2000 of the present embodiment is provided with a peripheral area PA and a central area CA on the substrate 200, and the central area CA includes a display area DA and a non-display area NDA. The peripheral area PA includes at least a pad peripheral area PPA.

For convenience of description, description will be made focusing on differences from the above-described embodiments.

The pad peripheral area PPA includes an insulating pattern IP and a dummy insulating pattern DIP.

The insulating pattern IP is provided corresponding to the pads 206a, and the insulating pattern IP is disposed spaced apart with a slit S therebetween.

The dummy insulating pattern DIP does not correspond to the pads 206a, and the dummy insulating pattern DIP is spaced apart with the dummy slit DS interposed therebetween.

Specifically, the insulating pattern IP is disposed to overlap the extension line of the pad 206a. Through this, when the wiring (not shown) is connected to the pad 206a, the wiring (not shown) is prevented from coming into contact with a foreign material on the substrate 200, in particular, a metal residual film or a metal particle, thereby fundamentally blocking a short circuit.

The dummy insulating pattern DIP may cover residual foreign matter or particles when forming various members on the substrate 200 to prevent defects due to foreign matter. In addition, the dummy insulating pattern DIP and the dummy slit DS may perform a stress relaxation function during deformation such as bending or bending of the display device 2000 including the substrate 200.

Since the contents of other components of the display apparatus 2000 are the same as those of the above-described display apparatus 1000 and optional embodiments thereof, a more detailed description of the display apparatus 2000 will be omitted.

5 to 14 are cross-sectional views showing other embodiments of FIG. 2 taken along line a-a'.

Referring to the embodiment of FIG. 5, the slit S is a type of opening exposing the top surface of at least some of the substrate 100. In the embodiment of FIG. 5, the insulating pattern IP is disposed to be spaced apart from each other with a slit S exposing at least a top surface of the substrate 100.

Meanwhile, the insulating pattern IP includes a first inorganic pattern 101P and a second inorganic pattern 102P sequentially from the substrate 100 in the same manner as in the embodiment of FIG. 3. As described above, as an optional embodiment, one or more inorganic films may be formed in the central area CA on the substrate 100. In this case, a plurality of insulating patterns IP may be connected to the inorganic films of the pad area PDA. have. However, the present exemplary embodiment is not limited thereto, and it is needless to say that an insulating pattern IP may be formed separately from the inorganic film formed in the central region CA.

Specific examples in which the first inorganic pattern 101P and the second inorganic pattern 102P are formed are the same as those described in the above-described embodiment. That is, the exemplary contents of the connection relationship with the inorganic films formed in the central area CA can be applied to all of the above-described embodiments.

Further, the second inorganic pattern 102P may include a form in which a plurality of inorganic pattern layers 103P and 105P are stacked.

Different from the embodiment of FIG. 3, in the embodiment of FIG. 5, the upper surface of the first inorganic pattern 101P of the insulating pattern IP is partially exposed. In other words, the side cross-section of the first inorganic pattern 101P and the side cross-section of the second inorganic pattern 102P are not located on the same line, and the second inorganic pattern 102P is the top surface of the first inorganic pattern 101P. Only some of them are covered.

In the embodiment of FIG. 5, a metal residual film may remain on the exposed area of the upper surface of the exposed first inorganic pattern 101P, but short defects of the pad portion 106a may be prevented. Referring to the embodiment of FIG. 6, the slit S is a type of opening exposing the top surface of the first inorganic film 101. In the embodiment of FIG. 6, the insulating patterns IP are disposed spaced apart from each other with slits S exposing the top surface of the first inorganic layer 101.

Meanwhile, the insulating pattern IP includes a second inorganic pattern 102P on the first inorganic layer 101. As described above, as an optional embodiment, one or more inorganic films may be formed in the central area CA on the substrate 100. In this case, a plurality of insulating patterns IP may be connected to the inorganic films of the pad area PDA. have. However, the present exemplary embodiment is not limited thereto, and it is needless to say that an insulating pattern IP may be formed separately from the inorganic film formed in the central region CA.

A specific example in which the second inorganic pattern 102P is formed is the same as described in the above-described embodiment. That is, the exemplary contents of the connection relationship with the inorganic films formed in the central area CA can be applied to all of the above-described embodiments. In addition, the second inorganic pattern 102P includes a form in which a plurality of inorganic pattern layers 103P and 105P are stacked.

In the embodiment of FIG. 6, the first inorganic layer 101 is formed in the pad peripheral area PPA, and the insulating pattern IP includes only the second inorganic pattern 102P, thereby forming the first inorganic layer 101. The step of patterning can be omitted, so the process is simplified.

Referring to the embodiment of FIG. 7, the slit S is a type of opening exposing the top surface of the first inorganic film 101. In the embodiment of FIG. 7, the insulating pattern IP is disposed spaced apart from each other with a slit S exposing the top surface of the first inorganic layer 101.

Meanwhile, the insulating pattern IP includes a second inorganic pattern 102P on the first inorganic layer 101. As described above, as an optional embodiment, one or more inorganic films may be formed in the central area CA on the substrate 100. In this case, a plurality of insulating patterns IP may be connected to the inorganic films of the pad area PDA. have. However, the present exemplary embodiment is not limited thereto, and it is needless to say that an insulating pattern IP may be formed separately from the inorganic film formed in the central region CA.

A specific example in which the second inorganic pattern 102P is formed is the same as described in the above-described embodiment. That is, the exemplary contents of the connection relationship with the inorganic films formed in the central area CA can be applied to all of the above-described embodiments. In addition, the second inorganic pattern 102P includes a form in which a plurality of inorganic pattern layers 103P and 105P are stacked.

In the embodiment of FIG. 7, the first inorganic film 101 has a predetermined groove between the second inorganic patterns 102P. The groove may have various shapes, as shown in FIG. 7, and the boundary of the groove may be spaced apart from the second inorganic pattern 102P.

However, this embodiment is not limited to this. That is, as illustrated in FIG. 8, the boundary line of the groove of the first inorganic layer 101 may be connected to the side surface of the second inorganic pattern 102P.

In addition, grooves may be formed on the first inorganic film 101 in various forms, for example, a boundary line of the groove of the first inorganic film 101 may be formed to pass the side surface of the second inorganic pattern 102P. It may be.

7 and 8, the upper surface of the first inorganic film 101 positioned in the slit S is partially removed. Accordingly, the thickness of the first inorganic film 101 in a predetermined region corresponding to the slit S is thinner than the thickness of the first inorganic film corresponding to the insulating pattern IP. According to the embodiment of FIGS. 9 to 14, the organic film 107P covering the insulating pattern IP is further provided with respect to the embodiments of FIGS. 3 and 5 to 8.

In detail, referring to FIG. 9, an organic layer 107P covering the top and side surfaces of the insulating pattern IP is further provided in the embodiment of FIG. 3, and referring to FIG. 10, the insulating pattern IP in the embodiment of FIG. 5 The organic layer 107P covering the upper surface and the side surface of the second inorganic pattern 102P included therein is further provided. Referring to FIG. 11, in the embodiment of FIG. 5, an organic layer 107P covering the top and side surfaces of the first inorganic pattern 101P and the second inorganic pattern 102P included in the insulating pattern IP is further provided.

Referring to FIG. 12, in the embodiment of FIG. 6, an organic layer 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP is further provided. Referring to FIG. 13, in the embodiment of FIG. 7, an organic layer 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP is further provided.

Referring to FIG. 14, in the embodiment of FIG. 8, an organic layer 107P covering the top and side surfaces of the second inorganic pattern 102P included in the insulating pattern IP is further provided.

As an optional embodiment, the organic layer 107P may be formed to be connected to one or more organic layers provided in the central region CA. For example, the organic layer 107P may be provided in the central region CA to cover a thin film transistor and be connected to a passivation film that flattens irregularities caused by the thin film transistor. In another embodiment, the organic layer 107P may be connected to a pixel defining layer defining a light emitting area by covering a part of the pixel electrode provided on the passivation layer. That is, when forming the passivation film or the pixel-defining film in the central area CA, it is possible to prevent the process from being added by forming the organic film 107P together.

According to the embodiment of FIGS. 9 to 14, even if the metal residual film remains on the side surface of the second inorganic pattern 102P, the organic film 107P covers the metallic residual film, thereby blocking the possibility of short defects due to the metallic residual film. There is a characteristic.

15 and 16 are views showing other modified examples of FIG. 2. For convenience of description, description will be made focusing on differences from the above-described embodiments.

15, the plurality of pads 106a' has an inclined shape. Specifically, the angle θ ₁ between the extension line of the pad 106a', for example, the center line of the pad 106' and the edge of the substrate may be less than 90 degrees. Also, the angle θ ₂ between the boundary of the slit S'or the center line of the slit S'and the edge of the substrate may be less than 90 degrees.

As an optional embodiment, the angle θ ₁ may be the same as the angle θ ₂ . That is, through this, the pad 106a' and the insulating pattern IP are formed side by side.

Although not illustrated, the shape in which the plurality of pads 106a' are inclined may vary. That is, the angle θ ₁ may be greater than 90 degrees. In this case, the angle θ ₂ may also be greater than 90 degrees.

Further, a plurality of pads 106a' formed in one region on the substrate may be inclined and a plurality of pads 106a' formed in another region on the substrate may be inclined. That is, a plurality of angles (θ ₁ ) may exist on one substrate instead of one.

Also, as illustrated in FIG. 16, a dummy insulating pattern DIP” and a dummy slit DS” may be further formed along with a plurality of pads 106a″ and a plurality of slits S″. The dummy insulating pattern DIP" does not correspond to the pads 106"a, and the dummy insulating pattern DIP" is disposed spaced apart with the dummy slit DS" interposed therebetween.

The inclined shapes of the plurality of pads 106a" and the plurality of slits S" are the same as those of the embodiment of FIG. 15, and detailed descriptions thereof will be omitted.

At this time, the dummy slit DS" is also formed in an inclined shape like the slit S". FIGS. 17 to 25 are b-b' cut lines of an embodiment of a method of manufacturing the display device of FIG. 1. It is a cross-sectional view sequentially shown on the basis of. Specifically, FIGS. 17 to 25 include a process of manufacturing an insulating pattern IP according to the embodiment of FIG. 3.

Referring to FIG. 17, first, the substrate 100 is prepared. The substrate 100 may be formed of various materials, and as an optional embodiment, may be made of a flexible material as described above. The first inorganic film 101 is formed on the substrate 100. The first inorganic film 101 may be functionally, for example, a buffer film, and the buffer film may be a central area CA of the substrate 100 including the display area DA, the non-display area NDA, and the pad area PDA. ) And the peripheral area PA around the cutting line CL including the pad peripheral area PPA. That is, the buffer film may be formed on all of the upper surface of the substrate 100. Here, the substrate 100 may be a substrate 100 on which one display device 1000 is to be formed, or may be a mother substrate on which a plurality of display devices 1000 are formed.

The buffer film may be formed by various deposition methods such as plasma enhanced chemical vapor deosition (PECVD) method, atmospheric pressure CVD (APCVD) method, and low pressure CVD (LPCVD) method using SiO ₂ and/or SiNx.

Referring to FIG. 18, a thin film transistor is formed in the display area DA on the buffer film. The thin film transistor TFT formed on the display area DA functions as a part of the pixel circuit. However, the thin film transistor TFT may also be formed on the non-display area NDA. The thin film transistor TFT formed on the non-display area NDA functions as a part of the circuit included in the driver.

Hereinafter, a case in which the thin film transistor TFT is a top gate type that sequentially includes the active layer 102, the gate electrode 104, and the source and drain electrodes 106s and d from the buffer film is illustrated. However, the present invention is not limited to this, and various types of thin film transistors (TFTs) such as a bottom gate type may be employed.

The active layer 102 (active layer) is formed on the buffer film in the form of a pattern. The active layer 102 includes a semiconductor material, and may include, for example, amorphous silicon or poly crystalline silicon. However, the present invention is not limited to this, and the active layer 102 may contain various materials. As an optional embodiment, the active layer 102 may contain an organic semiconductor material.

As another alternative embodiment, the active layer 102 may contain an oxide semiconductor material. For example, the active layer 102 is GIZO[(In ₂ O ₃ )a(Ga ₂ O ₃ )b(ZnO)c](a, b, c are a≥0, b≥0, c>0, respectively. Satisfying mistakes). In addition to GIZO, the active layer 102 is 12, 13, for example, zinc (Zn), indium (In), gallium (Ga), tin (Sn) cadmium (Cd), germanium (Ge), or hafnium (Hf). , Group 14 metal elements and oxides of materials selected from combinations thereof.

As described above, this embodiment may include various types of thin film transistors, for example, a bottom gate structured thin film transistor. In particular, when the active layer 102 contains oxide or amorphous silicon, a thin film transistor having a bottom gate structure may be provided.

The thin film transistor having the bottom gate structure may have various forms, for example, a gate electrode is formed on the substrate 100, an active layer is formed on the gate electrode, and a source electrode and a drain electrode are formed on the active layer. It can be placed. Further, as another example, a gate electrode may be formed on the substrate, a source electrode and a drain electrode may be formed on the gate electrode, and an active layer may be formed on the source electrode and the drain electrode. In this case, an insulating film, for example, an inorganic film, may be formed to be adjacent to at least one of the gate electrode, active layer, source electrode, and drain electrode.

The active layer 102 includes a source region and a drain region to which the source electrode 106s and the drain electrode 106d contact, respectively, and a channel region positioned therebetween. When the active layer 102 includes amorphous silicon or polycrystalline silicon, impurities may be doped in the source region and the drain region, if necessary.

A gate insulating layer 103 is formed on the active layer 102. The gate insulating layer 103 may be formed of a multilayer or a single layer formed of an inorganic material such as silicon oxide and/or silicon nitride. The gate insulating layer 103 serves to insulate the active layer 102 and the gate electrode 104.

The gate insulating layer 103 may be a single layer layer forming the second inorganic pattern 102P, and the gate insulating layer 103 may include a substrate including a display area DA, a non-display area NDA, and a pad area PDA ( 100 may be formed on both the peripheral area PA around the cutting line CL including the central area CA and the pad peripheral area PPA. That is, the gate insulating film 103 may be formed on the entire surface of the substrate 100. Here, the substrate 100 may be a substrate 100 on which one display device 1000 is to be formed, or may be a mother substrate on which a plurality of display devices 1000 are formed.

The gate electrode 104 is formed on the gate insulating layer 103 in a pattern form. The gate electrode 104 is connected to a gate line (not shown) that applies an on/off signal to the thin film transistor TFT. The gate electrode 104 may be made of a low-resistance metal material, for example, a film made of a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, to be formed in a multi-layer or single layer. Can.

An inter-layer dielectric (105) is formed on the gate electrode 104. The interlayer insulating film 105 serves to insulate the source electrode 106s and the drain electrode 106d from the gate electrode 104. The interlayer insulating film 105 may be formed of a multi-layered or single-layered film made of an inorganic material. For example, the inorganic material may be a metal oxide or a metal nitride, and specifically, the inorganic material is silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide ( TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZrO ₂ ).

The interlayer insulating layer 105 may be one layer forming the second inorganic pattern 102P, and the interlayer insulating layer 105 may include a substrate 100 including a display area DA, a non-display area NDA, and a pad area PDA. ) May be formed on both the peripheral area PA around the cutting line CL including the central area CA and the pad peripheral area PPA. That is, the interlayer insulating film 105 may be formed on the entire surface of the substrate 100. Here, the substrate 100 may be a substrate 100 on which one display device 1000 is to be formed, or may be a mother substrate on which a plurality of display devices 1000 are formed.

Next, referring to FIG. 19, contact holes CNTs are formed in the gate insulating layer 103 and the interlayer insulating layer 105, and at the same time, the peripheral area PA is patterned.

The contact hole CNT is formed to expose a predetermined surface of the active layer 102. This contact hole (CNT) allows the source electrode 106s and the drain electrode 106d to be electrically connected to the active layer 102 later. Meanwhile, when forming the contact hole CNT, the gate insulating layer 103 and the interlayer insulating layer 105 in the peripheral region PA are removed and the insulating pattern IP in the pad peripheral region PPA is formed at the same time. That is, the gate insulating film 103 and the interlayer insulating film 105 provided in the peripheral area PA around the cutting line CL are removed together, and the slits for forming the insulating pattern IP are formed in the pad peripheral area PPA. S) is formed. As described above, according to an embodiment of the present invention, a separate process for patterning the gate insulating layer 103 and the interlayer insulating layer 105 provided in the peripheral area PA is not required, so that the process can be simplified.

Next, referring to FIG. 20, a metal layer 106f for forming source, drain electrodes 106s and d and pads 106a is formed on the interlayer insulating layer 105. In the metal layer 106f, a film made of a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti) having low electrical resistance may be formed in multiple layers or single layers.

Next, referring to FIG. 21, the metal layer 106f is patterned to form source, drain electrodes 106s,d and pads 106a. The source electrode 106s and the drain electrode 106d respectively contact the source region and the drain region of the active layer 102 through contact holes CNTs formed in the interlayer insulating layer 105 and the gate insulating layer 103. Further, a pad 106a is formed in the pad area PDA.

Meanwhile, a metal layer may not be completely removed and metal residues 106p may remain on the side surfaces of the inorganic layers of the pad peripheral area PPA, for example, the side surfaces of the gate insulating layer 103 and the interlayer insulating layer 105. The metal residue 106p may cause short circuit defects when bonding the circuit board 200 having the external circuit mounted on the pad 106a.

Referring to FIG. 22, a passivation film 107 is formed to cover the thin film transistor TFT.

The passivation film 107 eliminates the step resulting from the thin film transistor TFT and makes the upper surface flat, thereby preventing defects in the organic light emitting device OLED due to lower irregularities. The passivation film 107 may be formed of a single layer or multiple layers of an organic material. Organic materials include general-purpose polymers such as polymethylmethacrylate (PMMA) and polystylene (PS), polymer derivatives with phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, and p-xylene polymers. Polymers, vinyl alcohol-based polymers, and blends thereof. Further, the passivation film 107 may be formed of a composite laminate of an inorganic insulating film and an organic insulating film.

Next, referring to FIGS. 23 to 26, an organic light emitting diode (OLED) is formed on the passivation film 107.

Specifically, a hole 107a exposing one of the source and drain electrodes 106s and d and an opening 107b exposing the top surface of the pad 106a are formed in the passivation film 107. The hole 107a serves as a passage for electrically connecting the organic light emitting device to be formed later and the thin film transistor (TFT). On the other hand, the opening 107b exposes the pad 106a, and then becomes a passage for electrically connecting the circuit board 200 on which the external circuit is mounted and the pad 106a.

Next, an organic light emitting diode (OLED) is formed on the passivation film 107. In detail, the organic light emitting device (OLED) includes a pixel electrode 111, an opposite electrode 112 opposed thereto, and an intermediate layer 113 interposed between both electrodes. According to the light emission direction of the organic light emitting diode (OLED), the display device is divided into a bottom emission type, a top emission type, and a dual emission type. The pixel electrode 111 is provided as a light transmitting electrode, and the counter electrode 112 is provided as a reflective electrode. In the front emission type, the pixel electrode 111 is provided as a reflective electrode, and the counter electrode 112 is provided as a semi-transmissive electrode. In the double-sided emission type, both the pixel electrode 111 and the counter electrode 112 are provided as electrodes that transmit light. In this embodiment, it is illustrated that the organic light emitting diode display is of a front emission type.

First, referring to FIG. 23, the pixel electrode 111 may be formed by patterning in an island shape. Also, the pixel electrode 111 is formed to contact the thin film transistor (TFT) included in the pixel circuit through the hole of the passivation film 107. Meanwhile, the pixel electrode 111 may be disposed to overlap the thin film transistor TFT to cover the lower pixel circuit.

The pixel electrode 111 includes a reflective electrode layer in addition to the transparent electrode layer so that light can be reflected in the direction of the counter electrode 112. When the pixel electrode 111 functions as an anode, the transparent electrode layer includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), It may include at least one selected from the group containing a transparent conductive oxide such as indium oxide (In2O3), indium galium oxide (IGO), and aluminum zinc oxide (AZO). . The reflective electrode layer may include a metal having high reflectance, such as silver (Ag).

Then, a pixel defining layer 109 is formed on the passivation layer 107. The pixel defining layer 109 may be formed by a method such as spin coating with one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene and phenol resin. The pixel defining layer 109 includes an opening 109a covering an edge of the pixel electrode 111 and opening at least a central portion. The region defined by the opening 109a corresponds to a light emitting region, and an intermediate layer 113 is formed.

Next, referring to FIG. 24, the first inorganic layer 101 in the peripheral area PA is patterned.

Although not shown, the first inorganic film 101 exposed around the cutting line CL is removed, and in the case of the pad peripheral area PPA, the first surface is formed to form a slit S exposing the upper surface of the substrate 100. The inorganic film 101 is removed. Accordingly, an insulating pattern IP including the first inorganic pattern 101P and the second inorganic pattern 102P is formed in the pad peripheral area PPA with the slit S exposing the substrate 100 therebetween. Can.

When patterning the first inorganic layer 101, the side ends of the gate insulating layer 103 and the interlayer insulating layer 105 and the side ends of the patterned first inorganic layer 101 may be matched. In this case, the metal residual film formed on the side surface of the second inorganic pattern 102P may be removed together in the process of patterning the first inorganic film 101. As such, the metal residual film in the area around the pad (PPA) is removed, thereby preventing short defects and manufacturing a reliable display device 1000.

In this embodiment, an insulating pattern IP may be formed using the first inorganic layer 101, the gate insulating layer 103, and the interlayer insulating layer 105, which function as a buffer layer. Although not shown, when the thin film transistor of the present embodiment has a bottom gate structure as described above, for example, when an active layer containing an oxide semiconductor material is formed, the first inorganic layer 101 serving as a buffer layer and the active layer An insulating pattern IP may be formed using a gate insulating layer to be disposed between the gate electrode and a protective layer that may be formed on the source electrode and the drain electrode.

In addition, in addition to this, the present embodiment may include various types of thin film transistors, in which case, various types of insulating films adjacent to or directly in contact with the active layer, gate electrode, source electrode, and drain electrode are formed in an extended form to insulate. A pattern IP can be formed.

Next, referring to FIG. 25, an intermediate layer 113 is formed in the emission region. The intermediate layer 113 includes an organic emission layer that emits red, green, or blue light, and the organic emission layer may be a low molecular organic material or a high molecular organic material. When the organic light-emitting layer is a low-molecular organic layer formed of a low-molecular organic material, a hole transport layer (HTL) and a hole injection layer (HIL) are located in the direction of the pixel electrode 111 centering on the organic light-emitting layer. In the direction of the electrode 112, an electron transport layer (ETL) and an electron injection layer (EIL) are stacked. Of course, in addition to these hole injection layers, hole transport layers, electron transport layers, and electron injection layers, various layers may be stacked and formed as necessary.

Meanwhile, the organic light emitting layer may be separately formed for each organic light emitting device. In this case, red, green, and blue light can be emitted for each organic light emitting device. However, the present invention is not limited to this, and the organic light emitting layer may be commonly formed in the entire organic light emitting device. For example, a plurality of organic emission layers that emit red, green, and blue light may be vertically stacked or mixed to emit white light. Of course, the combination of colors for emitting white light is not limited to the above. Meanwhile, in this case, a color conversion layer or a color filter for converting the emitted white light into a predetermined color may be separately provided.

Next, the counter electrode 112 is formed to cover the entire surface of the substrate 100. The counter electrode 112 may be made of a conductive inorganic material. When the counter electrode 112 functions as a cathode, lithium (Li), calcium (Ca), lithium fluoride/calcium (LiF/Ca), lithium fluoride/aluminum (LiF/Al), aluminum (Al) having a small work function , May be formed of magnesium (Mg), silver (Ag), or the like, and the metals may be formed as a thin film to allow light transmission. The counter electrode 112 may be formed as a common electrode throughout the display area DA in which an image is implemented. At this time, the counter electrode 112 may be formed by an evaporation process that does not damage the intermediate layer 113. Meanwhile, the polarity of the pixel electrode 111 and the counter electrode 112 may be reversed. The display device 1000 is finally formed by forming the counter electrode 112.

Although not shown on the counter electrode 112, an insulating capping layer may be further formed. The insulating capping layer maintains a work function of the counter electrode 112 when the encapsulation thin film is formed using a sputtering process or a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and the intermediate layer 113 The organics contained can prevent damage. The insulating capping layer is an optional configuration and may not be provided.

Next, although not shown, on the other hand, the organic light emitting device (OLED) is sealed by a sealing film to prevent the external moisture and air, etc. from penetrating. The sealing film may be in the form of a thin film, for example, a structure formed by alternately forming a film made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx) and an organic material such as epoxy and polyimide. Can take However, the present invention is not limited to this, and the sealing film may include a film made of low melting galss.

By sealing the organic light emitting element with such a thin film sealing film, the display apparatus 1000 has a flexible characteristic as a whole. Accordingly, the display apparatus 1000 according to an exemplary embodiment of the present invention can be bent, folded, and rolled.

However, the present embodiment is not limited to this, and a sealing member of various other materials may be formed on the organic light emitting device (OLED).

26 and 27 are cross-sectional views sequentially showing another embodiment of a method of manufacturing the display device of FIG. 1 based on a cutting line of b-b'.

26 and 27 include a process of manufacturing an insulating pattern IP according to the embodiment of FIG. 5.

According to FIG. 26, when patterning the first inorganic layer 101 in the peripheral area PA, the gate insulating layer 103 and the interlayer insulating layer 105 do not cover the upper surface of the first inorganic layer 101, that is, The first inorganic layer 101 may protrude compared to the ends of the gate insulating layer 103 and the interlayer insulating layer 105.

On the other hand, in the case of the process of manufacturing the insulating pattern (IP) according to the embodiment of FIG. 6, since the process of patterning the first inorganic film 101 among the processes of FIGS. 17 to 25 is omitted, redundant description will be omitted. Shall be

On the other hand, in the process of manufacturing the insulating pattern (IP) according to the embodiment of FIGS. 7 and 8 is replaced by a process of patterning only a part of the first inorganic film 101 among the processes of FIGS. The description will be omitted.

28 to 31 are cross-sectional views sequentially showing another embodiment of a method of manufacturing the display device of FIG. 1 based on a cutting line of b-b'. 28 to 31 include a process of manufacturing an insulating pattern IP according to the embodiment of FIG. 10.

Referring to FIG. 28, when forming the passivation film 107, it is characterized in that the top and side surfaces of the second inorganic pattern 102P of the pad peripheral area PPA are covered together. From this, the metal residual film that may remain on the side surface of the second inorganic pattern 102P is covered with the passivation film 107, thereby preventing short defects.

FIG. 29 is a process of forming a pixel defining layer similar to FIG. 23, and FIG. 30 is a process of patterning the first inorganic layer 101 of the peripheral area PA similarly to FIG. 24. In FIG. 30, the side cross-sections of the gate insulating layer 103 and the interlayer insulating layer 105 and the side cross-sections of the first inorganic layer 101 do not match so that the upper surface of the first inorganic layer 101 is partially exposed differently from FIG. 24. To avoid patterning. 31 is a process of forming the intermediate layer and the counter electrode similar to FIG. 25.

Meanwhile, in the embodiments of FIGS. 9, 11, 12, 13, and 14, only the process in which the organic film 107P covers at least the second inorganic pattern 102P is further added as shown in FIGS. 28 to 31. , Redundant description will be omitted.

Hereinafter, features of the display apparatus 1000 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 32 to 36.

First, FIG. 32 is a plan view schematically showing a display apparatus 1000 according to a comparative example of the present invention. FIG. 33 is a schematic plan view of FIG. 32 in an enlarged scale.

FIG. 32 illustrates a state in which the circuit board 200 on which the external circuit is mounted is bonded to the pad 106a. The circuit board 200 is equipped with a chip for transmitting various power or electric signals to the display area DA, and the chip is not illustrated in FIG. 32. The circuit board 200 includes a wiring 106l for connecting the chip and the pad 106a of the substrate 100. When the wiring 106l bonds with the pad 106a, various power sources or electricity output from the chip The signal is transmitted to the display area DA through the pad 106a.

Referring to FIG. 33, when the insulating pattern IP and the slit S are not provided in the pad peripheral area PPA, a residual metal residual film may remain when a foreign material, particle, or metal film is formed, and such a metal residual film Due to this, there is a problem in that short circuits occur because the wirings 106l are electrically shorted.

34 is a plan view schematically showing the display apparatus 1000 according to an embodiment of the present invention, FIG. 35 is a schematic plan view of FIG. 34, and FIG. 36 is a Q-Q' line of FIG. 35. It is a cross-sectional view taken along.

In the case of FIGS. 34 to 36, the circuit board 200 provided with the wiring 106l is the same, but the point in which the insulating pattern IP and the slit S are provided in the area around the pad PPA of the substrate 100 is compared. It is different from yes.

Referring to FIG. 35, an insulating pattern IP and a slit S are provided in the pad peripheral area PPA, so that even if a metal residual film remains on the side surface of the inorganic film removed to form the slit S, this metallic residual film Due to this, the wirings 106l are not electrically shorted. That is, the wirings 106l are provided corresponding to the insulating pattern IP, or the slit S is disposed between the wirings 106l and 106l. Specifically, as illustrated in FIG. 36, the wirings 106l may be formed to extend above the insulating pattern IP, for example, on the second inorganic pattern 102P of the insulating pattern IP.

Therefore, there is an effect that short defects do not occur as in the comparative example.

As described above, the present invention has been described with reference to one embodiment shown in the drawings, but this is only an example, and those skilled in the art will understand that various modifications and modifications of the embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: substrate 101P: first weapon pattern
101: first weapon film 102P: second weapon pattern
102: active layer 103P: pattern of the gate insulating film
103: gate insulating film 104: gate electrode
105P: pattern of the interlayer insulating film 105: interlayer insulating film
106f: metal layer 106d: drain electrode
106l: wiring 106s: source electrode
106a: pad 107b: opening
107P: organic film 107: passivation film
107a: hole 109a: opening
109: pixel defining layer 111: pixel electrode
112: counter electrode 113: intermediate layer
200: circuit board

Claims (1)

A display device comprising a central area having at least a display area on a substrate and a peripheral area disposed on at least one side of the central area,
One or more pads are disposed in the pad area of the central area,
A display device including an insulating pattern corresponding to at least the pad and a slit formed adjacent to the insulating pattern in an area around the pad in the peripheral area.

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