CN111312655A - Semiconductor interconnection structure and preparation method thereof - Google Patents

Semiconductor interconnection structure and preparation method thereof Download PDF

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Publication number
CN111312655A
CN111312655A CN202010126040.6A CN202010126040A CN111312655A CN 111312655 A CN111312655 A CN 111312655A CN 202010126040 A CN202010126040 A CN 202010126040A CN 111312655 A CN111312655 A CN 111312655A
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silicon
layer
conductive
dielectric layer
substrate
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沈鑫帅
石艳伟
董金文
夏志良
伍术
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor interconnection structure and a preparation method thereof, comprising the following steps: providing a layer structure, and forming a through hole in the layer structure; forming a conductive structure at least on the side wall of the through hole, wherein the inner side of the conductive structure is provided with a gap; and forming a filling dielectric layer in the gap at the inner side of the conductive structure. In the preparation method of the semiconductor interconnection structure, the inner side of the conductive structure still has the gap after the conductive structure is formed in the through hole, so that the surface area of the conductive structure can be increased; the diffusion coefficient of hydrogen in metal is larger, the diffusion at the interface belongs to short-circuit diffusion, the diffusion coefficient of hydrogen at the metal interface is larger, and the diffusion of hydrogen in the semiconductor interconnection structure is easier; when a semiconductor interconnect structure electrically connects a NAND string in a memory array with a landing pad, the diffusion of hydrogen along the interconnect structure can be enhanced, making it easier for hydrogen to diffuse into the capacitor.

Description

Semiconductor interconnection structure and preparation method thereof
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a semiconductor interconnection structure and a preparation method thereof.
Background
In a 3D NAND structure, a support substrate formed with a memory array is bonded to a CMOS substrate and then electrically led out via a lead-out pad located on the back surface of the support substrate or the back surface of the CMOS substrate. In a 3D NAND process, to passivate channel layer traps in the channel of NAND strings in a memory array, a layer of hydrogen-containing material needs to be formed, which serves as a source of hydrogen.
However, in the above volume of the 3DNAND structure, the hydrogen-containing material layer is formed on the back surface where the lead pad is formed in both the support substrate and the CMOS substrate; due to substrate surface defects and dopant impediments, and the interconnect structures in the prior art that lead out pads electrically connected to NAND strings in the memory array are all solid conductive structures, hydrogen in the hydrogen-containing material layer is difficult to pass through the substrate to reach the NAND strings in the memory array.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a semiconductor interconnect structure and a method for fabricating the same, which solve the above-mentioned problems in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor interconnect structure, the method comprising the steps of:
providing a layer structure, and forming a through hole in the layer structure;
forming a conductive structure at least on the side wall of the through hole, wherein a gap is formed inside the conductive structure; and
and forming a filling dielectric layer in the gap at the inner side of the conductive structure.
In the preparation method of the semiconductor interconnection structure, the inner side of the conductive structure still has the gap after the conductive structure is formed in the through hole, so that the surface area of the conductive structure can be increased; the diffusion coefficient of hydrogen in metal is larger, the diffusion at the interface belongs to short-circuit diffusion, the diffusion coefficient of hydrogen at the metal interface is larger, and the diffusion of hydrogen in the semiconductor interconnection structure is easier; when a semiconductor interconnect structure electrically connects a NAND string in a memory array with a landing pad, the diffusion of hydrogen along the interconnect structure can be enhanced, making it easier for hydrogen to diffuse into the capacitor.
Optionally, the conductive structure also covers the bottom of the via.
Optionally, the layer structure comprises a dielectric layer, the layer structure being formed on a substrate; the method also comprises the following steps after the filling dielectric layer is formed:
forming a through silicon via in the substrate, wherein the through silicon via penetrates through the substrate in the thickness direction and the through silicon via is exposed out of the conductive structure;
forming an insulating isolation layer on the side wall of the through silicon via; and
and forming a through silicon conductive plunger on the surface of the insulating isolation layer and the bottom of the through silicon via, wherein the through silicon conductive plunger fills the through silicon via and is electrically connected with the conductive structure.
Optionally, the layer structure includes a dielectric layer, the filling dielectric layer is a first filling dielectric layer, and the layer structure is formed on the substrate; the method also comprises the following steps after the first filling dielectric layer is formed:
forming a through silicon via in the substrate, wherein the through silicon via penetrates through the substrate in the thickness direction and the through silicon via is exposed out of the conductive structure;
forming an insulating isolation layer on the side wall of the through silicon via;
forming a through-silicon conductive plunger on the surface of the insulating isolation layer and the bottom of the through-silicon via, wherein a gap is formed inside the through-silicon conductive plunger, and the through-silicon conductive plunger is electrically connected with the conductive structure; and
and forming a second filling medium layer in the gap on the inner side of the silicon-through conductive plunger.
Optionally, the layer structure includes a substrate, the through hole is a through silicon through hole, and the conductive structure is a through silicon conductive plunger; the method also comprises the following steps before the through silicon via is formed:
forming a dielectric layer on the substrate;
forming an interconnection through hole in the dielectric layer; and
forming an interconnection structure in the interconnection through hole, wherein the interconnection structure fills the interconnection through hole; wherein the content of the first and second substances,
the through silicon via exposes the interconnection structure, and the through silicon conductive plunger is electrically connected with the interconnection structure.
The present invention also provides a semiconductor interconnect structure comprising:
a layer structure; and
a conductive plunger located within the layer structure, the conductive plunger comprising a fill dielectric layer and a conductive structure surrounding the fill dielectric layer.
The inner side of the conductive structure in the semiconductor interconnection structure still has the gap, so that the surface area of the conductive structure can be increased; the diffusion coefficient of hydrogen in metal is larger, the diffusion at the interface belongs to short-circuit diffusion, the diffusion coefficient of hydrogen at the metal interface is larger, and the diffusion of hydrogen in the semiconductor interconnection structure is easier; when a semiconductor interconnect structure electrically connects a NAND string in a memory array with a landing pad, the diffusion of hydrogen along the interconnect structure can be enhanced, making it easier for hydrogen to diffuse into the capacitor.
Optionally, the layer structure comprises a dielectric layer, the layer structure being formed on a substrate; the semiconductor interconnect structure further comprises:
the through-silicon conductive plunger is positioned in the substrate and penetrates through the substrate along the thickness direction, and the through-silicon conductive plunger is electrically connected with the conductive plunger; and
and the insulating isolation layer is positioned between the substrate and the through-silicon conductive plunger.
Optionally, the filling dielectric layer is a first filling dielectric layer; the through-silicon conductive plunger comprises a second filling medium layer and a through-silicon conductive structure surrounding the second filling medium layer.
Optionally, the layer structure comprises a substrate, the conductive plug is a through-silicon conductive plug; the interconnect structure further comprises:
the dielectric layer is positioned on the substrate; and
an interconnect structure within the dielectric layer; the interconnect structure is electrically connected with the through-silicon conductive plunger.
Drawings
Fig. 1 is a flow chart illustrating a method for fabricating a film semiconductor interconnect structure according to the present invention.
Fig. 2 to 12 are schematic cross-sectional views illustrating steps in a method for fabricating a semiconductor interconnect structure according to a first embodiment of the invention.
Fig. 13 to 15 are schematic cross-sectional views illustrating the formation of a through-silicon conductive plug with a void inside and a second dielectric filling layer in the method for manufacturing a semiconductor interconnect structure according to the second embodiment of the present invention.
Fig. 16 is a schematic cross-sectional view of an interconnect structure obtained by the method for manufacturing a semiconductor interconnect structure according to the third embodiment of the present invention.
Description of the element reference numerals
100 dielectric layer
101 interconnect vias
102 interconnect structure
103 first filling dielectric layer
104 substrate
105 through silicon via
106 insulating spacer layer
107 through silicon conductive plunger
108 second filling dielectric layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1, the present invention provides a method for fabricating a semiconductor interconnect structure, which includes the following steps:
s11: providing a layer structure, and forming a through hole in the layer structure;
s12: forming a conductive structure at least on the side wall of the through hole, wherein a gap is formed inside the conductive structure; and
s13: and forming a filling dielectric layer in the gap at the inner side of the conductive structure.
In this example, the layer structure is a dielectric layer, the vias are interconnect vias, and the conductive structure is an interconnect structure. The dielectric layer 100 is formed on a substrate 104 as shown in fig. 2. Specifically, the substrate 104 may be any substrate that can play a supporting role, and preferably, in this embodiment, the substrate 104 is a silicon substrate, and functional devices such as CMOS devices and the like may be formed in the substrate 104. The dielectric layer 100 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
In step S11, the dielectric layer 100 may be etched by a photolithography process to form the interconnection via 101, as shown in fig. 2, the interconnection via 101 penetrates through the dielectric layer 100 along a thickness direction to expose the surface of the substrate 104.
In one example, in step S12, an interconnect structure 102 may be formed on the sidewall, the bottom and the surface of the dielectric layer 100 of the interconnect via 101, as shown in fig. 3; specifically, the interconnect structure 102 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the thickness of the interconnection structure 102 is less than half of the width of the interconnection through hole 101, so as to ensure that the inside of the interconnection structure 102 has a gap; the interconnect structure 102 may include a metal interconnect structure such as copper, gold, aluminum, nickel, etc.; in step S13, a filling dielectric layer is formed on the surface of the interconnect structure 102, where the filling dielectric layer is the first filling dielectric layer 103, and the first filling dielectric layer 103 fills the interconnect via 101 and is located on the surface of the dielectric layer 100, as shown in fig. 4; specifically, the first filling dielectric layer 103 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the first filling dielectric layer 103 may include, but is not limited to, a silicon oxide layer; step S13 further includes a step of removing the interconnect structure 102 on the surface of the dielectric layer 100 and the first filling dielectric layer 103 on the surface of the dielectric layer 100, as shown in fig. 5; specifically, a Chemical Mechanical Polishing (CMP) process may be used to remove the interconnect structure 102 on the surface of the dielectric layer 100 and the first filling dielectric layer 103 on the surface of the dielectric layer 100. That is, in this example, the interconnect structure 102 covers the bottom of the via 101 in addition to the sidewalls of the via 101.
In another example, in step S12, the interconnect structure 102 may be formed before the sidewalls and bottom of the interconnect via 101 and the surface of the dielectric layer 100, as shown in fig. 3; specifically, the interconnect structure 102 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the thickness of the interconnection structure 102 is less than half of the width of the interconnection through hole 101, so as to ensure that the inside of the interconnection structure 102 has a gap; the interconnect structure 102 may include a metal interconnect structure such as copper, gold, aluminum, nickel, etc.; then, removing the interconnection structure 102 on the surface of the dielectric layer 100 and at the bottom of the interconnection via 101, as shown in fig. 6; specifically, the interconnect structure 102 on the surface of the dielectric layer 100 and at the bottom of the interconnect via 101 may be removed by, but not limited to, an etching-back process; in step S13, a filling dielectric layer is formed in the interconnection via 101 and on the surface of the dielectric layer 100, where the filling dielectric layer is the first filling dielectric layer 103, and the first filling dielectric layer 103 fills the interconnection via 101 and is located on the surface of the dielectric layer 100, as shown in fig. 7; specifically, the first filling dielectric layer 103 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the first filling dielectric layer 103 may include, but is not limited to, a silicon oxide layer; step S13 further includes removing the first filling dielectric layer 103 on the surface of the dielectric layer 100, as shown in fig. 8; specifically, the first filling dielectric layer 103 on the surface of the dielectric layer 100 may be removed by, but not limited to, a Chemical Mechanical Polishing (CMP) process. I.e. in this example the interconnect structure 10 is only located at the sidewalls of the via 101.
In one example, step S13 may be followed by the following steps:
s14: forming a through silicon via 105 in the substrate 104, where the through silicon via 105 penetrates through the substrate 104 in a thickness direction, and the through silicon via 105 exposes the interconnect structure 102, as shown in fig. 9; specifically, the through silicon via 105 may be formed by a photolithography and etching process; the through silicon via 105 penetrates the entire substrate 104, and the substrate 104 is not limited to a silicon substrate, that is, the material of the substrate 104 is not limited;
s15: forming an insulating isolation layer 106 on the sidewall of the tsv 105, as shown in fig. 10; the insulating isolation layer 106 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like; and
s16: forming a through-silicon conductive plug 107 on the surface of the insulating isolation layer 106 and the bottom of the through-silicon via 105, wherein the through-silicon conductive plug 107 fills the through-silicon via 105, and the through-silicon conductive plug 107 is electrically connected with the interconnect structure 102; the through silicon conductive plug 107 may be the same material as the interconnect structure 102; the through-silicon conductive plug 107 may be formed to fill the through-silicon via 105 and cover the back surface of the substrate 104, as shown in fig. 11, in this case, step S16 further includes a step of removing the through-silicon conductive plug 107 located on the back surface of the substrate 104, and the resulting structure is shown in fig. 12.
Referring to fig. 12, the present invention further provides a semiconductor interconnect structure, comprising: a layer structure; and the conductive plunger is positioned in the layer structure and comprises a filling medium layer and a conductive structure surrounding the filling medium layer.
In this embodiment, the layer structure includes a dielectric layer 100, the via is an interconnection via 101, the conductive structure is an interconnection structure 102, and the interconnection structure 102 is at least located on a sidewall of the interconnection via 101 that penetrates through the dielectric layer 100 in a thickness direction; the layer structure is formed on a substrate 104.
In one example, the interconnect structure 102 may be located only on the sidewalls of the interconnect via 101; in another example, the interconnect structure 102 may be on a sidewall of the interconnect via 101, and cover a bottom of the interconnect via 101, as shown in fig. 12.
In an example, the substrate 104 may be any substrate that can serve as a support, and preferably, in this embodiment, the substrate 104 is a silicon substrate, and functional devices such as CMOS devices and the like may be formed in the substrate 104. The dielectric layer 100 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
In one example, the thickness of the interconnect structure 102 is less than half the width of the interconnect via 101 to ensure that there is a void inside the interconnect structure 102; the interconnect structure 102 may include a metal interconnect structure such as copper, gold, aluminum, nickel, etc.; the first filling dielectric layer 103 may include, but is not limited to, a silicon oxide layer.
In one example, the semiconductor interconnect structure further comprises a through-silicon conductive plug 107, the through-silicon conductive plug 107 being located within the substrate 104, in particular within a through-silicon via 105 within the substrate 104; the through-silicon conductive plug 104 penetrates through the substrate 104 along the thickness direction, and the through-silicon conductive plug 107 is electrically connected with the interconnection structure 102; and an insulating isolation layer 106, the insulating isolation layer 106 being located between the substrate 104 and the through-silicon conductive plunger 107. In this embodiment, the through-silicon conductive plunger 107 is a solid conductive structure.
In one example, the insulating isolation layer 106 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like; the through silicon conductive plug 107 may be the same material as the interconnect structure 102.
In the preparation method of the semiconductor structure, the inner side of the interconnection structure 102 is provided with the gap, so that the surface area of the interconnection structure can be increased; the through silicon via is electrically connected with the lead-out bonding pad, the interconnection structure is electrically connected with the capacitor through the metal connecting line layer, the diffusion coefficient of hydrogen in metal is larger, the diffusion at the interface belongs to short circuit diffusion, the diffusion coefficient of hydrogen at the metal interface is larger, the diffusion of hydrogen along the interconnection structure can be enhanced, and the hydrogen is easier to diffuse into the capacitor through the interconnection structure and the through silicon conductive plunger.
Example two
Referring to fig. 13 to 15, the present invention further provides a method for fabricating a semiconductor interconnect structure, the method for fabricating the semiconductor interconnect structure in this embodiment is substantially the same as the method for fabricating the semiconductor interconnect structure in the first embodiment, and the difference between the methods is as follows: in the first embodiment, the through-silicon conductive plunger 107 is a solid conductive structure; in this embodiment, the through-silicon conductive plunger 107 has a gap inside, as shown in fig. 13; the filling dielectric layer 102 is used as a first filling dielectric layer, and after the through-silicon conductive plug 107 is formed, a step of forming a second filling dielectric layer 108 in a gap inside the through-silicon conductive plug 107 is further included, as shown in fig. 14 to 15. The second filling dielectric layer 108 may include, but is not limited to, a silicon oxide layer.
Referring to fig. 15, the present embodiment further provides a semiconductor interconnect structure, the semiconductor interconnect structure in the present embodiment is substantially the same as the semiconductor interconnect structure in the first embodiment, and the difference between the semiconductor interconnect structure and the semiconductor interconnect structure is as follows: in the semiconductor interconnect structure of the first embodiment, the through-silicon conductive plug 107 is a solid conductive structure; in the semiconductor interconnect structure of this embodiment, the through-silicon conductive plug 107 has a void inside; the semiconductor interconnect structure further comprises a second filling dielectric layer 108, wherein the second filling dielectric layer 108 is located in the gap inside the through-silicon conductive plug 107. The second filling dielectric layer 108 may include, but is not limited to, a silicon oxide layer.
EXAMPLE III
Referring to fig. 16, the present invention further provides a method for fabricating a semiconductor interconnect structure, the method for fabricating the semiconductor interconnect structure in this embodiment is substantially the same as the method for fabricating the semiconductor interconnect structure in the second embodiment, and the difference between the two methods is: in the second embodiment, the inner side of the interconnect structure 102 has a void, and the step of forming the first filling dielectric layer 103 in the void inside the interconnect structure 102 is further included after the interconnect structure 102 is formed; in the present embodiment, the interconnect structure 102 fills the interconnect via 101.
Referring to fig. 16, the present invention further provides a method for fabricating a semiconductor interconnect structure, the semiconductor interconnect structure of the present embodiment is substantially the same as the semiconductor interconnect structure of the second embodiment, and the difference between the semiconductor interconnect structure of the present embodiment and the semiconductor interconnect structure of the second embodiment is: in the second embodiment, a gap is formed inside the interconnect structure 102, and the gap inside the interconnect structure 102 is filled with a first filling dielectric layer 103; in this embodiment, the interconnect structure 102 is a solid conductive structure, and fills the interconnect via 101.
As described above, the semiconductor interconnect structure and the method for manufacturing the same of the present invention includes the steps of: providing a layer structure, and forming a through hole in the layer structure; forming a conductive structure at least on the side wall of the through hole, wherein a gap is formed inside the conductive structure; and forming a filling dielectric layer in the gap at the inner side of the conductive structure. In the preparation method of the semiconductor interconnection structure, the inner side of the conductive structure still has the gap after the conductive structure is formed in the through hole, so that the surface area of the conductive structure can be increased; the diffusion coefficient of hydrogen in metal is larger, the diffusion at the interface belongs to short-circuit diffusion, the diffusion coefficient of hydrogen at the metal interface is larger, and the diffusion of hydrogen in the semiconductor interconnection structure is easier; when a semiconductor interconnect structure electrically connects a NAND string in a memory array with a landing pad, the diffusion of hydrogen along the interconnect structure can be enhanced, making it easier for hydrogen to diffuse into the capacitor.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (9)

1. A preparation method of a semiconductor interconnection structure is characterized by comprising the following steps:
providing a layer structure, and forming a through hole in the layer structure;
forming a conductive structure at least on the side wall of the through hole, wherein a gap is formed inside the conductive structure; and
and forming a filling dielectric layer in the gap at the inner side of the conductive structure.
2. The method of manufacturing a semiconductor interconnect structure of claim 1, wherein: the conductive structure also covers the bottom of the via.
3. The method of manufacturing a semiconductor interconnect structure according to any of claims 1 to 2, wherein the layer structure comprises a dielectric layer, the layer structure being formed on a substrate; the method also comprises the following steps after the filling dielectric layer is formed:
forming a through silicon via in the substrate, wherein the through silicon via penetrates through the substrate in the thickness direction and the through silicon via is exposed out of the conductive structure;
forming an insulating isolation layer on the side wall of the through silicon via; and
and forming a through silicon conductive plunger on the surface of the insulating isolation layer and the bottom of the through silicon via, wherein the through silicon conductive plunger fills the through silicon via and is electrically connected with the conductive structure.
4. The method of manufacturing a semiconductor interconnect structure according to any of claims 1 to 2, wherein the layer structure comprises a dielectric layer, the filled dielectric layer is a first filled dielectric layer, and the layer structure is formed on a substrate; the method also comprises the following steps after the first filling dielectric layer is formed:
forming a through silicon via in the substrate, wherein the through silicon via penetrates through the substrate in the thickness direction and the through silicon via is exposed out of the conductive structure;
forming an insulating isolation layer on the side wall of the through silicon via;
forming a through-silicon conductive plunger on the surface of the insulating isolation layer and the bottom of the through-silicon via, wherein a gap is formed inside the through-silicon conductive plunger, and the through-silicon conductive plunger is electrically connected with the conductive structure; and
and forming a second filling medium layer in the gap on the inner side of the silicon-through conductive plunger.
5. The method of manufacturing a semiconductor interconnect structure according to any of claims 1 to 2, wherein the layer structure comprises a substrate, the via is a through silicon via, and the conductive structure is a through silicon conductive plug; the method also comprises the following steps before the through silicon via is formed:
forming a dielectric layer on the substrate;
forming an interconnection through hole in the dielectric layer; and
forming an interconnection structure in the interconnection through hole, wherein the interconnection structure fills the interconnection through hole; the through silicon via exposes the interconnection structure, and the through silicon conductive plunger is electrically connected with the interconnection structure.
6. A semiconductor interconnect structure, comprising:
a layer structure; and
a conductive plunger located within the layer structure, the conductive plunger comprising a fill dielectric layer and a conductive structure surrounding the fill dielectric layer.
7. The semiconductor interconnect structure of claim 6, wherein the layer structure comprises a dielectric layer, the layer structure being formed on a substrate; the semiconductor interconnect structure further comprises:
the through-silicon conductive plunger is positioned in the substrate and penetrates through the substrate along the thickness direction, and the through-silicon conductive plunger is electrically connected with the conductive plunger; and
and the insulating isolation layer is positioned between the substrate and the through-silicon conductive plunger.
8. The semiconductor interconnect structure of claim 7, wherein the fill dielectric layer is a first fill dielectric layer; the through-silicon conductive plunger comprises a second filling medium layer and a through-silicon conductive structure surrounding the second filling medium layer.
9. The semiconductor interconnect structure of claim 6, wherein the layer structure comprises a substrate, the conductive plug is a through silicon conductive plug; the interconnect structure further comprises:
the dielectric layer is positioned on the substrate; and
an interconnect structure within the dielectric layer; the interconnect structure is electrically connected with the through-silicon conductive plunger.
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Application publication date: 20200619