CN111293092A - Ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies and packaging process - Google Patents

Ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies and packaging process Download PDF

Info

Publication number
CN111293092A
CN111293092A CN202010143736.XA CN202010143736A CN111293092A CN 111293092 A CN111293092 A CN 111293092A CN 202010143736 A CN202010143736 A CN 202010143736A CN 111293092 A CN111293092 A CN 111293092A
Authority
CN
China
Prior art keywords
substrate
packaging
plastic
ultra
plastic package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010143736.XA
Other languages
Chinese (zh)
Inventor
周小磊
郝杰
张贤祝
康文斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Luxshare Electronic Technology Kunshan Ltd
Original Assignee
Luxshare Electronic Technology Kunshan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Luxshare Electronic Technology Kunshan Ltd filed Critical Luxshare Electronic Technology Kunshan Ltd
Priority to CN202010143736.XA priority Critical patent/CN111293092A/en
Publication of CN111293092A publication Critical patent/CN111293092A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

The invention discloses an ultra-miniaturized SIP packaging product integrating multiple plastic packaging technologies and a packaging process, wherein the ultra-miniaturized SIP packaging product comprises a first substrate and a second substrate which are vertically stacked, a conductor support piece for conducting the first substrate and the second substrate, a plurality of component devices arranged on the upper surface and the lower surface of the first substrate and the upper surface of the second substrate, a plurality of plastic packaging parts which cover part or all of the components and have a three-dimensional block-shaped structure in the peripheral outline, and electromagnetic shielding layers covering the upper surface and the peripheral side surfaces of the plastic packaging parts. The invention organically combines the selective plastic package, the double-sided plastic package and the 3D package technology, and stacks and interconnects a plurality of substrates, thereby improving the product performance and realizing the ultra-micro design.

Description

Ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies and packaging process
[ technical field ] A method for producing a semiconductor device
The invention belongs to the technical field of electronic components, and particularly relates to an ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies and a packaging process.
[ background of the invention ]
The ultra-miniaturized SIP packaging technology is to integrate one or more active semiconductor devices and passive components (generally, one or more ICs and supporting circuits) on a complete substrate, so as to not only miniaturize the product size on the XY plane, but also limit the thickness reduction of the product in the Z direction. And various functional devices such as WiFi, Bluetooth, satellite navigation (GPS), NFC, NAND, CPU and the like can be embedded, so that a functional module of the processing system is realized.
Compared with a non-integrated circuit, the multifunctional ultra-miniaturized system module has the advantages of obvious miniaturization and anti-interference, replaces the traditional module mode with the ultra-miniaturized SIP system module, enables products to be widely applied to various high-end electronic products with higher requirements on size miniaturization, such as mobile phones, flat computers and wearable devices, and meets the requirements of high cost performance, high speed, low energy consumption, small size and multiple functions.
With the design trend of miniaturization and ultra-thinness of electronic products and the diversified design of functions, the realization of the encapsulation of ultra-miniaturized electronic products becomes a great difficulty.
Therefore, it is necessary to provide a new ultra-miniaturized SIP package product and a new packaging process integrating multiple plastic packaging technologies to solve the above problems.
[ summary of the invention ]
One of the main objectives of the present invention is to provide an ultra-miniaturized SIP package product integrating multiple plastic packaging technologies, which organically combines selective plastic packaging, double-sided plastic packaging and 3D packaging technologies to stack and interconnect multiple substrates, thereby improving product performance and realizing ultra-miniaturized design.
The invention realizes the purpose through the following technical scheme: the ultra-miniaturized SIP packaging product integrated with multiple plastic packaging technologies comprises a first substrate and a second substrate which are arranged in an up-and-down laminated mode, a conductor support piece for conducting the first substrate and the second substrate, a plurality of component devices arranged on the upper surface and the lower surface of the first substrate and the upper surface of the second substrate, a plurality of plastic packaging parts which cover part or all of the components and are in a three-dimensional block structure in peripheral outline, and electromagnetic shielding layers covering the upper surface of the plastic packaging parts and the peripheral side surfaces.
Further, the second substrate is located above the first substrate.
Furthermore, the plurality of component devices comprise a first component device arranged on the upper surface of the first substrate, a second component device arranged on the lower surface of the first substrate, and a third component device arranged on the upper surface of the second substrate.
Furthermore, the plurality of plastic package portions comprise a first plastic package portion, a second plastic package portion and a third plastic package portion, wherein the first plastic package portion wraps up part of the first group of components and fills gaps between the first substrate and the second substrate, the second plastic package portion wraps up the second group of components and the third group of components.
Furthermore, chips are embedded in the first substrate and the second substrate, and a plurality of surface bonding pads are arranged on the upper surface and the lower surface of the first substrate and the second substrate.
Furthermore, the conductor support comprises a plurality of solder ball structures.
Another object of the present invention is to provide an ultra-miniaturized SIP packaging process integrating various plastic packaging technologies, which comprises the following steps:
1) providing a multilayer substrate as a circuit carrier plate to form a first substrate, wherein the thickness of the first substrate is 0.3-0.4 mm;
2) finishing the mounting of a first component device on the upper surface of the first substrate by using an SMT (surface mount technology) surface mounting process to form a first module, wherein the thickness of the first module is controlled to be 1.2-1.4 mm;
3) providing a second substrate, and finishing the mounting of a third group of components on the upper surface of the second substrate by using an SMT (surface mount technology), wherein the thickness is controlled to be 1.2-1.4 mm;
4) soldering a plurality of solder balls at set positions on the first substrate to form a second module;
5) welding the second module to the first module by using a 3D (three-dimensional) multilayer stacking three-dimensional packaging process to form a third module;
6) the surface mounting of a second component device is completed on the lower surface of the first substrate by utilizing an SMT (surface mounting technology), the 3D stacking of a second surface is completed, and the thickness is controlled to be 4.2-4.6 mm;
7) plastic packaging is carried out on the area needing plastic packaging by utilizing a selective plastic packaging process, and the area not needing plastic packaging is protected; simultaneously carrying out plastic package on two sides of the substrate by using a double-sided plastic package process, and simultaneously enabling the thickness of a plastic package area in the Z direction after the plastic package is carried out to be the lowest, so as to form a first plastic package part, a second plastic package part and a third plastic package part;
8) and finally, carrying out metal sputtering on the exposed surface of the plastic package part by using a metal sputtering process to form the electromagnetic shielding layer.
Further, the thickness of electromagnetic shield layer is 5 ~ 12 um.
Further, the first plastic package part wraps a set part of the first group of components; the second plastic package part wraps the second group of components completely; and the third plastic package part is used for completely wrapping the third group of components.
Furthermore, the diameter of the solder ball is 0.7-1.2 mm.
Compared with the prior art, the ultra-miniaturized SIP packaging product integrating multiple plastic packaging technologies and the packaging process have the beneficial effects that: the selective plastic package, the double-sided plastic package and the 3D package technology are organically combined, 3D three-dimensional package among the multilayer substrates is realized, the product performance is improved, and meanwhile, the ultra-micro design is realized.
[ description of the drawings ]
FIG. 1 is a schematic structural diagram of a first substrate according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a first set of components mounted on a first substrate according to an embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of a first module according to an embodiment of the present disclosure;
FIG. 4 is a schematic structural diagram of a second substrate according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram illustrating a third component mounted on the second substrate according to an embodiment of the present disclosure;
FIG. 6 is a schematic structural diagram of a second module according to an embodiment of the present disclosure;
FIG. 7 is a schematic structural diagram of a third module according to an embodiment of the present disclosure;
FIG. 8 is a diagram illustrating a second component mounted on a bottom surface of a third module according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating a bonded structure of a bonded chip according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a packaged structure according to an embodiment of the invention;
FIG. 11 is a schematic overall structure diagram of an embodiment of the present invention;
the figures in the drawings represent:
100 ultra-miniaturized SIP packaging products integrated with various plastic packaging technologies;
1 a first substrate; 2 a second substrate; 3 a conductor support; 4 an electromagnetic shielding layer; 5 a first component device; 6 a second group of components; 7 a third group of components; 8, a first plastic package part; 9 a second plastic package part; 10 a third plastic package part; 11 chips; 12 surface bonding pads; 13 binding the chip.
[ detailed description ] embodiments
Example (b):
referring to fig. 11, an ultra-miniaturized SIP package product 100 integrating multiple plastic package technologies in this embodiment includes a first substrate 1 and a second substrate 2 stacked up and down, a conductor support 3 for connecting the first substrate 1 and the second substrate 2, a plurality of component devices disposed on the upper and lower surfaces of the first substrate 1 and the upper surface of the second substrate 2, a plurality of plastic package portions covering part or all of the component devices and having a three-dimensional block-shaped peripheral outline, and an electromagnetic shielding layer 4 covering the upper surface and the peripheral side surfaces of the plastic package portions.
The second substrate 2 is positioned above the first substrate 1.
The plurality of component devices comprise a first component 5 arranged on the upper surface of the first substrate 1, a second component 6 arranged on the lower surface of the first substrate 1, and a third component 7 arranged on the upper surface of the second substrate 2.
The plurality of plastic package parts comprise a first plastic package part 8 which wraps part of the first group of components 5 and fills a gap between the first substrate 1 and the second substrate 2, a second plastic package part 9 which wraps the second group of components 6 in a full-covering mode, and a third plastic package part 10 which wraps the third group of components 7 in a full-covering mode.
The conductor support 3 includes a plurality of solder ball structures.
The first substrate 1 and the second substrate 2 are both provided with embedded chips 11, and the upper and lower surfaces of the first substrate 1 and the second substrate 2 are both provided with a plurality of surface pads 12.
The embodiment also provides an ultra-miniaturized SIP packaging process integrating various plastic packaging technologies, which comprises the following steps:
1) providing a multi-layer substrate as a circuit carrier to form a first substrate 1; the multi-layer substrate is selected as the circuit carrier plate, so that a multifunctional integrated circuit board can be realized, and a foundation is laid for the design of the integrated circuit with a multifunctional ultra-microminiaturized structure; the thickness of the first substrate 1 is controlled within the range of 0.3-0.4 mm; as shown in fig. 1;
2) the surface mounting of the first group of components 5 is completed on the upper surface of the first substrate 1 by utilizing an SMT surface mounting process to form a first module, and the thickness is controlled within the range of 1.2-1.4 mm; as shown in fig. 2-3;
3) providing a second substrate 2, and finishing the mounting of a third group of components 7 on the upper surface of the second substrate 2 by using an SMT (surface mount technology), wherein the thickness is controlled within the range of 1.2-1.4 mm; as shown in fig. 4-5;
4) soldering a plurality of solder balls, namely the conductor support 3, at the set positions on the lower surface of the second substrate 2 to form a second module; the diameter of the solder ball is 0.7-1.2 mm; as shown in fig. 6;
specifically, a high-precision steel mesh is coated on the other surface of the 3D stacked substrate with one surface of the second substrate 2 already pasted on the surface, scaling powder is added in an area needing ball planting, a ball planting machine is used for planting balls on corresponding bonding pads, the substrate is placed into a reflow oven for reflow for a set number of times after the ball planting is finished, then a detection instrument is used for online detection and control of the quality and the height of the solder balls, and thus the chip is integrated to form the second substrate
5) Welding the second module to the first module to form a third module; putting the third module into a reflow oven for reflow for a set number of times, and after the reflow is finished, detecting and controlling the quality and the height of the solder balls on line by using a detection instrument, so that the total Z-direction height of the third module is controlled, and 3D stacking is realized; as shown in fig. 7;
6) the surface mounting of the second group of components 6 is completed on the lower surface of the first substrate 1 by utilizing an SMT surface mounting process, and 3D stacking of the second surface is completed; wherein, the second group of components 6 comprises a binding chip 13, and a gold wire or a copper wire is bonded on a bonding pad of the binding chip 13 and a bonding pad of the substrate by using a gold wire bonding machine, so that the whole system is electrically communicated; as shown in fig. 8-9;
7) plastic packaging is carried out on the area needing plastic packaging by utilizing a selective plastic packaging process, and the area not needing plastic packaging is protected; simultaneously carrying out plastic package on two sides of the substrate by using a double-sided plastic package process, and simultaneously enabling the thickness of a plastic package area after the plastic package area in the Z direction to be the lowest to form a first plastic package part 8, a second plastic package part 9 and a third plastic package part 10; as shown in fig. 10;
cleaning and activating an area needing plastic package by using an ion cleaning machine, then putting a substrate formed by 3D stacking into a mold, determining the temperature of the mold according to the characteristics of a plastic package material, finishing selective double-sided plastic package in one step by a Transfermold mode, then putting a product finished by plastic package into an oven for post-curing treatment, fully reacting materials in a plastic material, and enhancing physical characteristics; the structure shown in fig. 9 is completed by one-time injection molding and plastic packaging;
the first plastic package part 8 is formed by performing plastic package treatment on a space region between the first substrate 1 and the second substrate 2, and wraps a set part of the first group of components 5; the second plastic package part 9 wraps the second group of components 6 completely, and the third plastic package part 10 wraps the third group of components 7 completely; the thickness is controlled within the range of 4.2-4.6 mm;
the peripheral side surfaces of the second substrate 2 are flush with the peripheral side surfaces of the first plastic packaging part 8 and the third plastic packaging part 10, so that a structural foundation is laid for realizing a full-coverage plastic packaging process;
8) finally, metal sputtering is performed on the exposed surface of the plastic package part by using a metal sputtering process to form the electromagnetic shielding layer 4, as shown in fig. 11. The thickness of electromagnetic shielding layer 4 is 5 ~ 12 um.
Wherein, step 2 specifically includes: baking and dehumidifying the substrate, wherein the temperature is generally 110-130 ℃, the best temperature is 125 ℃, then performing laser two-dimensional code on the baked substrate to facilitate the tracing of product information, then covering a high-precision printing steel mesh on the substrate, controlling the height of the printed tin paste by using the steel mesh so as to make a paving pad for meeting the requirement that the total height of the surface-mounted parts is lower, adding soldering flux into an area needing to be printed with the tin paste, then performing tin paste printing, detecting the quality and the height of the printed tin paste on line by using a detection instrument, then performing surface mounting on the qualified printed substrate by using a surface mounting machine to ensure that the gaps among the parts meet the design requirement, generally controlling the gaps among the parts to be 50-60 mu m without deviation or leakage, finally performing reflow treatment on the product by using a reflow oven, wherein the temperature in the reflow oven is generally determined according to the characteristics of the selected tin paste material, if the solder paste is high-temperature solder paste, the nitrogen protection is generally recommended to be carried out at 210 ℃ in the reflow process, so that the solder ball is prevented from being oxidized, and finally, the overall quality and height of the integrally surface-mounted part are detected on line by using a detection instrument, so that the height is controlled within a design range; after the surface of the substrate is pasted, a dispensing machine is used for carrying out bottom glue sealing and filling on a tin ball or a copper column of a BGA component to form a bottom plastic sealing area, as shown in figure 3, the substrate after surface pasting is placed on an online ion cleaning machine for cleaning a dispensing area, and the surface of the substrate in the dispensing area is activated, so that the subsequent bottom filling glue and the substrate can be better combined conveniently, and the phenomena of layering, inner cavities and glue overflow are avoided; preheating the substrate after the ion cleaning on a dispensing machine, releasing the internal stress of the substrate, preventing the substrate from being warped too much, adding the bottom filling glue after the temperature returning is finished into the dispensing machine for liquefying, dispensing along a set path by using a computer to control a dispensing head, and filling the bottom of the BGA component; after dispensing is finished, the substrate is placed into an oven for baking, and curing treatment is carried out on the bottom filling glue, so that the glue material can further carry out complete reaction, and the required physical performance is realized; finally, the first module is formed.
The plastic package portion in this embodiment is made of epoxy resin, phenolic resin, silicone resin, and unsaturated polyester resin, which are most commonly used, and preferably, epoxy resin plastic package is used as a raw material. Specifically, the softened epoxy resin plastic sealant is injected into a mold cavity through a molding machine for curing and molding, and mainly plays the following roles: protecting the die/gold wire; isolating external electrical influence; so as to have thermal stability; good mechanical strength is kept; is convenient for use, transportation and assembly.
The present embodiment mainly organically combines a selective plastic packaging process, a double-sided plastic packaging process and a 3D three-dimensional packaging process to realize ultra-miniaturization of SIP packaging. In particular, the method comprises the following steps of,
1) the 3D stereo packaging technology is a solution developed based on the idea of multilayer stacking, and the core idea of the 3D stereo packaging technology is a high-density technology developed to the space on the basis of two-dimensional packaging of an XY plane. The multilayer stacked 3D package generally comprises flip-chip bonding a bump-grown qualified chip to a substrate, the substrate having conductor wiring, interconnection pads inside and external interconnection pads on both sides, and then stacking and interconnecting a plurality of substrates. The 3D packaging technology is used for replacing the traditional 2D two-dimensional packaging technology, so that the product can be further miniaturized in size, and meanwhile, the weight of the product is lighter; meanwhile, in the aspect of speed, the 3D multilayer stack packaging technology effectively reduces parasitic capacitance and parasitic inductance in a circuit due to the fact that the length of interconnection between chips is shortened, power consumption requirements are reduced, meanwhile, saved power enables the conversion speed of elements to operate faster without increasing extra energy consumption, power density is improved, and the purpose of noise reduction is achieved;
2) the selective plastic packaging process is utilized to carry out plastic packaging protection on some parts, such as connectors, antennas and the like, and some parts are exposed, so that a specific functional module is formed, the space of a main board is saved, and the ultra-miniaturization of an SiP product is realized;
3) the double-sided plastic package structure has the advantages that the product with high requirements on assembly reliability and light weight and thinness is required, multiple functions are required to be realized in a self limited space, and the structure of the product is more compact by using a double-sided plastic package process.
What has been described above are merely some embodiments of the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the inventive concept thereof, and these changes and modifications can be made without departing from the spirit and scope of the invention.

Claims (10)

1. An ultra-miniaturized SIP packaging product integrating multiple plastic packaging technologies is characterized in that: the device comprises a first substrate and a second substrate which are arranged in an up-and-down laminated manner, a conductor support piece for conducting the first substrate and the second substrate, a plurality of component devices arranged on the upper surface and the lower surface of the first substrate and the upper surface of the second substrate, a plurality of plastic package parts which cover part or all of the components and have three-dimensional block-shaped peripheral outlines, and electromagnetic shielding layers covering the upper surface and the peripheral side surfaces of the plastic package parts.
2. The ultra-miniaturized SIP package product integrating multiple plastic package technologies as claimed in claim 1, wherein: the second substrate is positioned above the first substrate.
3. The ultra-miniaturized SIP package product integrating multiple plastic package technologies as claimed in claim 1, wherein: the plurality of component devices comprise a first component arranged on the upper surface of the first substrate, a second component arranged on the lower surface of the first substrate, and a third component arranged on the upper surface of the second substrate.
4. The ultra-miniaturized SIP package product integrating multiple plastic package technologies as claimed in claim 3, wherein: the plurality of plastic package parts comprise a first plastic package part, a second plastic package part and a third plastic package part, wherein part of the first group of components are wrapped up and filled in a gap between the first substrate and the second substrate, the second plastic package part is used for wrapping up the second group of components in a fully-covered mode, and the third plastic package part is used for wrapping up the third group of components in a fully-covered mode.
5. The ultra-miniaturized SIP package product integrating multiple plastic package technologies as claimed in claim 1, wherein: the first substrate and the second substrate are internally provided with chips, and the upper surface and the lower surface of the first substrate and the second substrate are provided with a plurality of surface bonding pads.
6. The ultra-miniaturized SIP package product integrating multiple plastic package technologies as claimed in claim 1, wherein: the conductor support comprises a plurality of solder ball structures.
7. An ultra-miniaturized SIP packaging process integrating multiple plastic packaging technologies is characterized in that: which comprises the following steps:
1) providing a multilayer substrate as a circuit carrier plate to form a first substrate, wherein the thickness of the first substrate is 0.3-0.4 mm;
2) finishing the mounting of a first group of components on the upper surface of the first substrate by using an SMT (surface mount technology) to form a first module, wherein the thickness of the first module is controlled to be 1.2-1.4 mm;
3) providing a second substrate, and finishing the mounting of a third group of components on the upper surface of the second substrate by using an SMT (surface mount technology), wherein the thickness is controlled to be 1.2-1.4 mm;
4) soldering a plurality of solder balls at set positions on the first substrate to form a second module;
5) welding the second module to the first module by using a 3D (three-dimensional) multilayer stacking and three-dimensional packaging process to form a third module;
6) the surface mounting of a second group of components is completed on the lower surface of the first substrate by utilizing an SMT surface mounting process, the 3D stacking of a second surface is completed, and the thickness is controlled to be 4.2-4.6 mm;
7) plastic packaging is carried out on the area needing plastic packaging by utilizing a selective plastic packaging process, and the area not needing plastic packaging is protected; simultaneously carrying out plastic packaging on two sides of the substrate by using a double-sided plastic packaging process, and simultaneously enabling the thickness of a plastic packaging area in the Z direction after the plastic packaging to be the lowest to form a first plastic packaging part, a second plastic packaging part and a third plastic packaging part;
8) and finally, carrying out metal sputtering on the exposed surface of the plastic package part by using a metal sputtering process to form the electromagnetic shielding layer.
8. The ultra-miniaturized SIP packaging process integrating multiple plastic packaging technologies according to claim 6, wherein: the thickness of electromagnetic shielding layer is 5 ~ 12 um.
9. The ultra-miniaturized SIP packaging process integrating multiple plastic packaging technologies according to claim 6, wherein: the first plastic package part wraps a set part of the first group of components; the second plastic package part wraps the second group of components completely; and the third plastic package part wraps the third group of components completely.
10. The ultra-miniaturized SIP packaging process integrating multiple plastic packaging technologies according to claim 6, wherein: the diameter of the solder ball is 0.7-1.2 mm.
CN202010143736.XA 2020-03-04 2020-03-04 Ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies and packaging process Pending CN111293092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010143736.XA CN111293092A (en) 2020-03-04 2020-03-04 Ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies and packaging process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010143736.XA CN111293092A (en) 2020-03-04 2020-03-04 Ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies and packaging process

Publications (1)

Publication Number Publication Date
CN111293092A true CN111293092A (en) 2020-06-16

Family

ID=71027341

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010143736.XA Pending CN111293092A (en) 2020-03-04 2020-03-04 Ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies and packaging process

Country Status (1)

Country Link
CN (1) CN111293092A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111786702A (en) * 2020-07-10 2020-10-16 歌尔科技有限公司 NFC module and wearable equipment
CN112885743A (en) * 2021-01-14 2021-06-01 江苏和睿半导体科技有限公司 Plastic packaging device for chip packaging and testing
CN113035826A (en) * 2021-02-23 2021-06-25 青岛歌尔智能传感器有限公司 Packaging module, manufacturing method of packaging module and electronic equipment
CN113555327A (en) * 2021-06-21 2021-10-26 青岛歌尔智能传感器有限公司 Packaging structure and electronic equipment
WO2023098693A1 (en) * 2021-12-01 2023-06-08 展讯通信（上海）有限公司 Double-sided packaging assembly and forming method therefor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111786702A (en) * 2020-07-10 2020-10-16 歌尔科技有限公司 NFC module and wearable equipment
CN112885743A (en) * 2021-01-14 2021-06-01 江苏和睿半导体科技有限公司 Plastic packaging device for chip packaging and testing
CN113035826A (en) * 2021-02-23 2021-06-25 青岛歌尔智能传感器有限公司 Packaging module, manufacturing method of packaging module and electronic equipment
CN113035826B (en) * 2021-02-23 2022-08-19 青岛歌尔智能传感器有限公司 Packaging module, manufacturing method of packaging module and electronic equipment
CN113555327A (en) * 2021-06-21 2021-10-26 青岛歌尔智能传感器有限公司 Packaging structure and electronic equipment
WO2023098693A1 (en) * 2021-12-01 2023-06-08 展讯通信（上海）有限公司 Double-sided packaging assembly and forming method therefor

Similar Documents

Publication Publication Date Title
CN111293092A (en) Ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies and packaging process
US7413929B2 (en) Integrated chip package structure using organic substrate and method of manufacturing the same
US9955582B2 (en) 3-D stacking of active devices over passive devices
US9646922B2 (en) Methods and apparatus for thinner package on package structures
US20090206461A1 (en) Integrated circuit and method
EP1965615A1 (en) Module having built-in component and method for fabricating such module
CN103747616B (en) Parts installation module
CN108807297A (en) Electronic package and manufacturing method thereof
KR20090039411A (en) Semiconductor package, module, system having a solder ball being coupled to a chip pad and manufacturing method thereof
JP2002510148A (en) Semiconductor component having a plurality of substrate layers and at least one semiconductor chip and a method for manufacturing the semiconductor component
CN105428341A (en) Semiconductor Device, And Method For Manufacturing Semiconductor Device
CN102569268A (en) Semiconductor device and method for manufacturing same
US10741499B2 (en) System-level packaging structures
CN114899155A (en) Multi-type multi-quantity chip three-dimensional stacking integrated packaging structure and manufacturing method thereof
CN110246812A (en) A kind of semiconductor package and preparation method thereof
CN211605137U (en) Ultra-miniaturized SIP (Session initiation protocol) packaging product integrating multiple plastic packaging technologies
CN104981102A (en) Multi-chip-embedded flexible printed circuit board and manufacturing method thereof
KR20010063236A (en) Stack package and manufacturing method thereof
CN108630626A (en) Without substrate encapsulation structure
CN108447829A (en) Package structure and method for fabricating the same
TW201944573A (en) System-in-package structure with embedded substrates and manufacturing method thereof
US20190279935A1 (en) Semiconductor package having package substrate containing non-homogeneous dielectric layer
CN114126189B (en) Circuit board with embedded element and manufacturing method thereof
CN216563093U (en) Packaging module
KR100907730B1 (en) Semiconductor package and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
CB03 Change of inventor or designer information

Inventor after: Zhou Xiaolei

Inventor after: Hao Jie

Inventor after: Zhang Xianzhu

Inventor after: Kang Wenbin

Inventor before: Zhou Xiaolei

Inventor before: Hao Jie

Inventor before: Zhang Xianzhu

Inventor before: Kang Wenbin

CB03 Change of inventor or designer information
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20200616

WD01 Invention patent application deemed withdrawn after publication