CN111292797B - Memory chip and test circuit and test method thereof - Google Patents
Memory chip and test circuit and test method thereof Download PDFInfo
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- CN111292797B CN111292797B CN202010166388.8A CN202010166388A CN111292797B CN 111292797 B CN111292797 B CN 111292797B CN 202010166388 A CN202010166388 A CN 202010166388A CN 111292797 B CN111292797 B CN 111292797B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The invention discloses a memory chip and a test circuit and a test method thereof.A microprocessor of the multiplexing memory chip is used as a controller of the test circuit in the memory chip, a page buffer of the multiplexing memory chip is used as a comparison circuit of the test circuit, and a self-test circuit can be built in the memory chip only by adding a test vector generation circuit in the memory chip.
Description
Technical Field
The invention relates to the technical field of memory chips, in particular to a memory chip and a test circuit and a test method thereof.
Background
With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.
Electronic devices need to store data through a memory chip. With the performance of electronic devices becoming more and more powerful, more and more data need to be stored and processed, and in order to ensure safe and reliable operation of the electronic devices, the electronic devices need to integrate a test circuit inside a memory chip to detect whether the memory chip has a fault.
In the prior art, a test circuit is generally required to be additionally arranged in a chip structure of a memory chip, so that the manufacturing cost is high, and the chip miniaturization design is not convenient.
Disclosure of Invention
In view of the above, the present application provides a memory chip, a test circuit thereof and a test method thereof, and the scheme is as follows:
a test circuit of a memory chip, the memory chip comprises a microprocessor and a memory structure, the memory structure comprises a memory array and a page buffer; the microprocessor is at least used for reading the storage data in the storage array through the page buffer;
the test circuit includes:
a comparison circuit that multiplexes the page buffers;
a test vector generation circuit for generating a test vector based on the address information;
a controller that multiplexes the microprocessor; the controller is used for executing a test instruction, controlling the comparison circuit to read the test data from the storage array after the comparison circuit writes the test data into the storage array based on the address information and the test vector, and obtaining a comparison result of the test data and standard data through the comparison circuit.
Preferably, in the above test circuit, the microprocessor includes a read only memory for storing a read instruction; the microprocessor is used for executing the reading instruction to read the storage data in the storage array through the page buffer;
the read-only memory also stores the test instruction, and the controller is used for reading the test instruction matched with the instruction pointer from the read-only memory based on the instruction pointer.
Preferably, in the test circuit, the controller is configured to determine whether to execute an operation end instruction after decoding the test instruction, and if so, end the test on the memory chip, and if not, execute the decoded test instruction to obtain the comparison result.
Preferably, in the test circuit, the comparison circuit is configured to perform an exclusive or logic operation on the test data and the standard data to obtain the comparison result;
the controller is further configured to determine failure information of the memory chip based on the comparison result.
Preferably, in the test circuit, the controller is configured to obtain a comparison result corresponding to current address information, perform address increment, determine whether the incremented address information reaches a maximum address, and if not, obtain the comparison result corresponding to the incremented address information.
The present invention also provides a memory chip, including:
a microprocessor and a memory structure, the memory structure comprising a memory array and a page buffer; the microprocessor is at least used for reading the storage data in the storage array through the page buffer;
the test circuit is characterized by further comprising a test circuit, wherein the test circuit is any one of the test circuits.
The invention also provides a test method of the memory chip, the memory chip comprises a microprocessor and a memory structure, and the memory structure comprises a memory array and a page buffer; the microprocessor is at least used for reading the storage data in the storage array through the page buffer;
multiplexing the microprocessor to execute the test method, wherein the test method comprises the following steps:
acquiring a test instruction;
for the test instruction
Decoding is carried out;
after decoding is completed, starting a test vector generating circuit to generate a test vector based on the address information;
executing the decoded test instruction, including:
multiplexing the page buffer based on the address information and the test vector, and writing test data into the memory array;
multiplexing the page buffer, reading the test data from the memory array, and obtaining the comparison result of the test data and the standard data.
Preferably, in the above test method, the microprocessor includes a read only memory for storing a read instruction; the microprocessor is used for executing the reading instruction to read the storage data in the storage array through the page buffer;
the read-only memory further stores the test instruction, and the obtaining the test instruction comprises: and reading the test instruction matched with the instruction pointer from the read-only memory based on the instruction pointer.
Preferably, after the decoding is completed, before the test vector generation circuit is started, the method further includes:
and judging whether an operation ending instruction is executed or not, if so, ending the test on the memory chip, and if not, executing the decoded test instruction to obtain the comparison result.
Preferably, in the above test method, the method of obtaining the comparison result includes: carrying out XOR logic operation on the test data and the standard data to obtain the comparison result;
or, the test method further comprises: determining fault information of the memory chip based on the comparison result;
or, the test method comprises: and obtaining a comparison result corresponding to the current address information, carrying out address increment, judging whether the incremented address information reaches the maximum address, and if not, obtaining the comparison result corresponding to the incremented address information.
As can be seen from the above description, in the memory chip and the test circuit and the test method thereof according to the technical solutions of the present invention, the microprocessor multiplexing the memory chip is used as the controller of the test circuit in the memory chip, the page buffer multiplexing the memory chip is used as the comparison circuit of the test circuit, and only a test vector generation circuit needs to be added to the memory chip, so that the self-test circuit can be built in the memory chip.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
The structure, proportion, size and the like shown in the drawings are only used for matching with the content disclosed in the specification, so that the person skilled in the art can understand and read the description, and the description is not used for limiting the limit condition of the implementation of the invention, so the method has no technical essence, and any structural modification, proportion relation change or size adjustment still falls within the scope of the technical content disclosed by the invention without affecting the effect and the achievable purpose of the invention.
FIG. 1 is a circuit diagram of a NAND memory chip;
FIG. 2 is a schematic diagram of a built-in self-test circuit in a memory chip;
FIG. 3 is a schematic diagram of another memory chip with a built-in self-test circuit;
FIG. 4 is a schematic diagram of a memory chip;
FIG. 5 is a schematic diagram of a test circuit according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating a memory chip microprocessor according to an embodiment of the present invention;
FIG. 7 is a flowchart of a testing method according to an embodiment of the present invention;
fig. 8 is a schematic flowchart of another testing method according to an embodiment of the present invention.
Detailed Description
The embodiments of the present application will be described in detail and fully with reference to the accompanying drawings, wherein the description is only for the purpose of illustrating the embodiments of the present application and is not intended to limit the scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
Since 3D NAND memory chips are mainly composed of arrays and the storage capacity depends on the area of the array, it is desirable to compress the built-in self-test circuit as much as possible in order to reduce the chip cost. The difficulty of the built-in self-test algorithm suitable for the 3D NAND memory chip is to design a test sequence to cover various modes of interference faults, increase the test efficiency and reduce the test cost.
As shown in fig. 1, fig. 1 is a circuit diagram of a NAND memory chip, including: microprocessor (MCU), memory structure, data path, interface components, and internal registers. The data path is respectively connected with the storage structure, the interface component and the internal register, and the data path is used for acquiring user data, address information and instructions and sending the user data, the address information and the instructions to the corresponding connected components. The interface component is connected with the MCU. The memory structure includes a memory array, a page buffer, a column decoder, and a word line decoder. The internal register is connected with the page buffer through an independent port, is connected with the word line decoder through an independent port and sequentially passes through the analog circuit and the word line switch, is connected with the interface component through an independent port, and is connected with the MCU through an independent port.
The MCU includes an instruction acquisition circuit, is connected with a Read Only Memory (ROM) through an individual port, is also connected with a random access controller through an individual port, and is also connected with a decoder through an individual port. In the MCU, a decoder is connected with an execution circuit, the execution circuit is respectively connected with a data write-back circuit, a bus control circuit and an arithmetic logic arithmetic unit, and a Random Access Memory (RAM) controller is connected with a RAM. The main functions of the MCU include: programming, erasing and reading data in the storage array based on a preset algorithm and an instruction; controlling an internal register; and controlling data between the MCU and the data path.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a built-in self-test circuit in a memory chip, in which the built-in self-test circuit is required to be separately added in the memory chip, the built-in self-test circuit includes a test vector generation circuit and a comparison circuit, and a controller for separately adding the built-in self-test circuit is required. The controller needs to access enable signals CE, OE and WE. The built-in self-test circuit requires access to the interface signals BSI, BSO, BMS, BRS, CLK, and BNS. The built-in self-test circuit and the controller are connected with a storage structure of the storage chip through a test interface. In this manner, the memory structure includes at least an address buffer, an X decoder, a test analog register, a power module, a memory array, a Y decoder, and a sense amplifier.
Referring to fig. 3, fig. 3 is a schematic diagram of a structure of a built-in self-test circuit in a memory chip, in this way, the built-in self-test circuit includes: the test device comprises a controller, a test vector generation circuit and a comparison circuit, wherein the controller, the test vector generation circuit and the comparison circuit are all connected with an RAM in a storage chip through a test interface, and the test interface is also connected with an RAM controller in the storage chip. The controller of the built-in self-test circuit includes a hardware FSM (finite state machine).
As can be seen from the manners shown in fig. 2 and fig. 3, in general, the test circuit is integrated in the memory chip, and a three-part structure of the controller, the test vector generation circuit and the comparison circuit needs to be added separately, so that the hardware area is large, and is generally about 0.1863mm2The test cost is high, and the miniaturization design of the memory chip is not convenient.
In order to solve the above problem, an embodiment of the present invention provides a test circuit for a memory chip, where the memory chip is shown in fig. 4, fig. 4 is a schematic structural diagram of a memory chip, the memory chip at least includes a microprocessor 11 and a memory structure 12, and the memory structure 12 includes a memory array 121 and a page buffer 122; the microprocessor 11 is at least used for reading the storage data in the storage array 121 through the page buffer 122. The microprocessor 11 may be a dedicated microprocessor inherent in a memory chip or a general-purpose processor.
In the embodiment of the present invention, the memory chip is described by taking a 3D NAND memory chip as an example, and it should be noted that the memory chip in the embodiment of the present invention is not limited to be a 3D NAND memory chip, and may be other types of memory chips.
Fig. 5 shows the test circuit, and fig. 5 is a schematic diagram of a test circuit structure provided in an embodiment of the present invention, where the test circuit includes:
a comparison circuit 21, the comparison circuit 21 multiplexing the page buffer;
a test vector generation circuit 22, the test vector generation circuit 22 being configured to generate a test vector based on the address information;
a controller 23, said controller 23 multiplexing said microprocessor 11; the controller 23 is configured to execute a test instruction, control the comparison circuit 21 to write test data into the memory array 121 based on the address information and the test vector, control the comparison circuit 21 to read the test data from the memory array 121, and obtain a comparison result between the test data and standard data through the comparison circuit 21.
In the memory chip, the page buffer 122 has a data reading circuit and a comparison circuit, so the page buffer 122 can be multiplexed as the comparison circuit 21, the data reading circuit writes the test data into the memory array 121 and reads the test circuit from the memory array 121, and the comparison circuit obtains the comparison result between the test data and the standard data, without additionally providing the comparison circuit 21.
In the memory chip, the microprocessor 11 may be in a test mode or in a data read/write mode based on a preset instruction, in the test mode, the microprocessor 11 is multiplexed as the controller 21 to execute the test method of the embodiment of the present invention to test the memory chip, and in the data read/write mode, the memory unit of the memory chip may be subjected to operations such as conventional programming, data reading, erasing, and the like without separately adding a controller of a test circuit.
In the memory chip and the test circuit and the test method thereof provided by the technical scheme of the invention, the microprocessor multiplexing the memory chip is used as the controller 13 of the test circuit in the memory chip, the page buffer multiplexing the memory chip is used as the comparison circuit 11 of the test circuit, and compared with the traditional scheme of singly adding the controller, the comparison circuit and the test vector generation circuit, the built-in self-test circuit in the memory chip can be realized only by adding the test vector generation circuit 12 in the memory chip, thereby greatly reducing the size of the test circuit, facilitating the miniaturization design of the memory chip and reducing the manufacturing cost.
In the memory chip, the microprocessor 11 includes a read only memory for storing a read instruction; the microprocessor 11 is configured to execute the read instruction to read the storage data in the storage array 121 through the page buffer 122. Optionally, the read only memory further stores the test instruction, and the read only memory is multiplexed to store the test instruction, so that the controller 23 executes the test instruction to perform a fault test on the memory chip. When the test instruction is executed to perform a fault test on the memory chip, the controller 23 is configured to read the test instruction adapted to the instruction pointer from the read only memory based on the instruction pointer. The test instruction includes a test data write instruction, the controller 23 executes the test data write instruction to control the comparison circuit 21 to write the test data in the memory array 121, and the test instruction further includes a test data read instruction, and the controller 23 executes the test data read instruction to control the comparison circuit 21 to read the test data in the memory array 121.
When the memory chip is tested, the controller 23 is configured to decode the test instruction, and then determine whether to execute an operation ending instruction, if so, end the test on the memory chip, and if not, execute the decoded test instruction to obtain the comparison result.
When the memory chip is tested, the comparison circuit 21 is configured to perform an exclusive or logic operation on test data and standard data to obtain the comparison result; if the values of the test data and the standard data are not the same, the XOR result is 1. If the test data and the standard data have the same value, the XOR result is 0. The controller 23 is further configured to determine failure information of the memory chip based on the comparison result. If the comparison result indicates that the values of the test data and the standard data are the same, the test data are characterized to be free of faults, otherwise, the fault is indicated.
When the memory chip is tested and a current test instruction is executed, the controller 23 is configured to obtain a comparison result corresponding to current address information, perform address increment, determine whether the incremented address information reaches a maximum address, and if not, obtain the comparison result corresponding to the incremented address information.
Fig. 6 shows a structure of a microprocessor according to an embodiment of the present invention, where fig. 6 is a schematic structural diagram of a memory chip microprocessor according to an embodiment of the present invention, including: a microcode storage module 231, an instruction pointer acquisition module 232, an address generation module 234, and a read-write control module 233. The microcode storage module 231 includes a ROM of the memory chip. A read instruction and a test instruction are stored.
The microcode storage module 231 is connected to the test vector generation circuit 22, the instruction pointer acquisition module 232, the address generation module 234, and the read/write control module 233, respectively. The comparison circuit 21, the test vector generation circuit 22, the address generation module 234, and the read/write control module 233 are all connected to the memory array 121.
If the instruction pointer of the instruction pointer obtaining module 232 is used to start the memory chip to perform data read/write operations, the microcode storage module 231 reads a control instruction corresponding to the data read/write operations, and executes the control instruction, and the address generating module 234 and the read/write control module 233 provide the page buffer with address information and a read/write command to perform data read/write operations on the memory array 121.
If the instruction pointer of the instruction pointer obtaining module 232 is used to start the memory chip to perform a test operation, at this time, the microprocessor 11 is multiplexed as the controller 23, reads a test instruction corresponding to the test operation from the microcode storage module 231, executes the test instruction, controls the test vector generating circuit 22 to generate a test vector based on address information, controls the address generating module 234 and the read/write control module 233 to provide address information and a test command for the comparison circuit 21, so as to store test data in the storage column 121, and then reads the test data in the storage array through the comparison circuit 21 and performs comparison between the test data and standard data.
The test circuit further comprises a fault output module 24 connected to the comparison circuit 21, and the controller 23 is further configured to output a fault detection result based on a comparison result of the comparison circuit.
As can be seen from the above description, in the test circuit according to the embodiment of the present invention, the microprocessor 11 inherent to the multiplexing memory chip forms a built-in test circuit of the chip to test the chip, and the multiplexing microprocessor 11 has hardware with a data read-write-erase algorithm, so that different test sequences of the memory chip can be controlled without separately setting the controller 11. The comparison circuit 21 in the test circuit multiplexes the memory chip page buffer 122, performs exclusive or logic operation, and determines failure information without separately providing the comparison circuit 21. According to the technical scheme of the embodiment of the invention, the increased area loss is only the RAM capacity occupied by the test vector generation circuit 22 and the algorithm, and the circuit area of the test vector generation circuit 22 is about 7000 mu m2The sum of the test sequence and the original hardware does not exceed the inherent RAM capacity of the chip, the size of the chip is not increased by the partial structure, the occupation of a test circuit on the area of the chip can be greatly reduced, the test area and the test time of the memory chip are effectively reduced, and various test algorithms can be realized by changing the internal hardware.
Based on the foregoing embodiment, another embodiment of the present invention further provides a memory chip, where the memory chip includes: a microprocessor and a memory structure, the memory structure comprising a memory array and a page buffer; the microprocessor is at least used for reading the storage data in the storage array through the page buffer. The memory chip further comprises a test circuit, and the test circuit is the test circuit in the embodiment. The structures of the memory chip and the test circuit can be described with reference to the above embodiments, and are not described herein again.
In the memory chip, the controller of the test circuit can multiplex the inherent microprocessor of the memory chip, and the comparison circuit of the test circuit can multiplex the inherent page buffer of the memory chip, so that the occupation of the test circuit on the chip area can be greatly reduced.
Based on the foregoing embodiment, another embodiment of the present invention further provides a method for testing a memory chip, where the memory chip includes a microprocessor and a memory structure, and the memory structure includes a memory array and a page buffer; the microprocessor is at least used for reading the storage data in the storage array through the page buffer. The structure of the memory chip can refer to the above description, and is not described herein again.
The test method is multiplexed with the microprocessor to execute the test method, and can be realized based on the test circuit.
Fig. 7 shows the testing method, where fig. 7 is a flowchart of the testing method provided in the embodiment of the present invention, and the method includes:
step S11: and acquiring a test instruction.
Step S12: decoding the test instruction;
step S13: after decoding is completed, the test vector generation circuit is activated to generate a test vector based on the address information.
Step S14: and executing the decoded test instruction.
In step S14, the executing the decoded test command includes:
step S141: and multiplexing the page buffer based on the address information and the test vector, and writing test data into the memory array.
Step S142: multiplexing the page buffer, reading the test data from the memory array, and obtaining the comparison result of the test data and the standard data.
In the test method, the microprocessor comprises a read-only memory for storing a read instruction; the microprocessor is used for executing the reading instruction to read the storage data in the storage array through the page buffer. The read-only memory also stores the test instructions. The obtaining of the test instruction comprises: and reading the test instruction matched with the instruction pointer from the read-only memory based on the instruction pointer.
In the test method, after decoding is completed and before the test vector generation circuit is started, the method further includes: and judging whether an operation ending instruction is executed or not, if so, ending the test on the memory chip, and if not, executing the decoded test instruction to obtain the comparison result.
In the test method, the method for obtaining the comparison result comprises the following steps: and carrying out exclusive-or logic operation on the test data and the standard data to obtain the comparison result.
In the testing method, the testing method further comprises: determining failure information of the memory chip based on the comparison result.
In the test method, the test method comprises the following steps: and obtaining a comparison result corresponding to the current address information, carrying out address increment, judging whether the incremented address information reaches the maximum address, and if not, obtaining the comparison result corresponding to the incremented address information.
Referring to fig. 8, fig. 8 is a schematic flow chart of another testing method according to an embodiment of the present invention, where the testing method includes:
step S21: the test instructions are read from the ROM of the memory chip.
Step S22: the read test instruction is decoded.
Step S23: after the decoding is completed, it is determined whether to execute an operation end instruction, if so, the test operation is ended, if not, the subsequent test is executed, and the process proceeds to step S24.
Step S24: a test vector generation circuit is enabled to generate a test vector based on the address information.
Step S25: and after the test vector is generated, executing the decoded test instruction, acquiring a comparison result corresponding to the current instruction based on a preset program algorithm, and performing address increment.
Step S26: and after finishing the address increment, judging whether the maximum address is reached.
If not, returning to the step S25, and continuing to execute the current instruction until the comparison results corresponding to all the addresses are obtained, and the maximum address is reached. If so, the process proceeds to step S27.
Step S27: and judging whether the current test instruction is finished, if so, returning to the step S21 to obtain the next test instruction, and if not, returning to the step S25 until the comparison results corresponding to all the addresses under the test instruction before obtaining reach the maximum address.
As can be seen from the above description, the testing method can multiplex the built-in self-test circuit of the inherent microprocessor and the inherent page buffer framework chip of the memory chip, and can greatly reduce the occupation of the testing circuit on the chip area.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. For the memory chip and the test method disclosed by the embodiment, since the memory chip and the test method correspond to the test circuit disclosed by the embodiment, the description is relatively simple, and relevant points can be just described by referring to the corresponding part of the test circuit.
It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A test circuit of a memory chip is characterized in that the memory chip comprises a microprocessor and a memory structure, wherein the memory structure comprises a memory array and a page buffer; the microprocessor is at least used for reading the storage data in the storage array through the page buffer;
the test circuit includes:
a comparison circuit that multiplexes the page buffers;
a test vector generation circuit for generating a test vector based on the address information;
a controller that multiplexes the microprocessor; the controller is used for executing a test instruction, controlling the comparison circuit to read the test data from the storage array after the comparison circuit writes the test data into the storage array based on the address information and the test vector, and obtaining a comparison result of the test data and standard data through the comparison circuit;
the controller is used for judging whether an operation ending instruction is executed or not after the test instruction is decoded, if so, ending the test on the memory chip, and if not, executing the decoded test instruction to obtain the comparison result.
2. The test circuit of claim 1, wherein the microprocessor includes a read only memory for storing read instructions; the microprocessor is used for executing the reading instruction to read the storage data in the storage array through the page buffer;
the read-only memory also stores the test instruction, and the controller is used for reading the test instruction matched with the instruction pointer from the read-only memory based on the instruction pointer.
3. The test circuit of claim 1, wherein the comparison circuit is configured to perform an exclusive-or operation on the test data and the standard data to obtain the comparison result;
the controller is further configured to determine failure information of the memory chip based on the comparison result.
4. The test circuit according to any one of claims 1 to 3, wherein when the current test instruction is executed, the controller is configured to obtain a comparison result corresponding to the current address information, perform address increment, determine whether the incremented address information reaches the maximum address, and obtain the comparison result corresponding to the incremented address information if the incremented address information does not reach the maximum address.
5. A memory chip, wherein the memory chip comprises:
a microprocessor and a memory structure, the memory structure comprising a memory array and a page buffer; the microprocessor is at least used for reading the storage data in the storage array through the page buffer;
further comprising a test circuit as claimed in any one of claims 1-4.
6. The method for testing the memory chip is characterized in that the memory chip comprises a microprocessor and a memory structure, wherein the memory structure comprises a memory array and a page buffer; the microprocessor is at least used for reading the storage data in the storage array through the page buffer;
multiplexing the microprocessor to execute the test method, wherein the test method comprises the following steps:
acquiring a test instruction;
decoding the test instruction;
after decoding is completed, starting a test vector generating circuit to generate a test vector based on the address information;
executing the decoded test instruction, including:
multiplexing the page buffer based on the address information and the test vector, and writing test data into the memory array;
multiplexing the page buffer, reading the test data from the memory array, and obtaining a comparison result of the test data and standard data;
after decoding is completed, before the test vector generation circuit is started, the method further includes:
and judging whether an operation ending instruction is executed or not, if so, ending the test on the memory chip, and if not, executing the decoded test instruction to obtain the comparison result.
7. The method of claim 6, wherein the microprocessor includes a read only memory for storing read instructions; the microprocessor is used for executing the reading instruction to read the storage data in the storage array through the page buffer;
the read-only memory further stores the test instruction, and the obtaining the test instruction comprises: and reading the test instruction matched with the instruction pointer from the read-only memory based on the instruction pointer.
8. The test method of claim 6, wherein obtaining the comparison comprises: carrying out XOR logic operation on the test data and the standard data to obtain the comparison result;
or, the test method further comprises: determining fault information of the memory chip based on the comparison result;
or, the test method comprises: and obtaining a comparison result corresponding to the current address information, carrying out address increment, judging whether the incremented address information reaches the maximum address, and if not, obtaining the comparison result corresponding to the incremented address information.
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| CN102314950A (en) * | 2010-02-23 | 2012-01-11 | 摩希斯股份有限公司 | Programmable test engine (PCDTE) for emerging memory technologies |
| CN202120623U (en) * | 2011-07-15 | 2012-01-18 | 桂林电子科技大学 | Embedded static random access memory (SRAM) testing structure based on institute of electrical and electronic engineers (IEEE) 1500 |
| CN110797077A (en) * | 2019-10-28 | 2020-02-14 | 中国科学院微电子研究所 | Memory chip, data processing circuit and data processing method thereof |
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| CN102314950A (en) * | 2010-02-23 | 2012-01-11 | 摩希斯股份有限公司 | Programmable test engine (PCDTE) for emerging memory technologies |
| CN202120623U (en) * | 2011-07-15 | 2012-01-18 | 桂林电子科技大学 | Embedded static random access memory (SRAM) testing structure based on institute of electrical and electronic engineers (IEEE) 1500 |
| CN110797077A (en) * | 2019-10-28 | 2020-02-14 | 中国科学院微电子研究所 | Memory chip, data processing circuit and data processing method thereof |
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