CN111277519A - Exchange chip extension system and switch - Google Patents
Exchange chip extension system and switch Download PDFInfo
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- CN111277519A CN111277519A CN202010108500.2A CN202010108500A CN111277519A CN 111277519 A CN111277519 A CN 111277519A CN 202010108500 A CN202010108500 A CN 202010108500A CN 111277519 A CN111277519 A CN 111277519A
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- 238000004891 communication Methods 0.000 claims abstract description 10
- 230000005540 biological transmission Effects 0.000 claims abstract description 6
- 101150071746 Pbsn gene Proteins 0.000 claims description 5
- 239000000835 fiber Substances 0.000 claims description 5
- 238000012937 correction Methods 0.000 claims description 4
- 230000007246 mechanism Effects 0.000 claims description 4
- 238000012545 processing Methods 0.000 abstract description 11
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000013507 mapping Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
Abstract
The application provides a switching chip extension system, including: the switching chip comprises a plurality of switching ports, and the switching ports comprise a first preset number of serializers; a high-speed backplane connected to the switch port; the PHY chip comprises an input port and an output port, the input serializers of the input port on the Host side of the PHY chip are connected with the serializers of the exchange ports one by one through the high-speed back plate, the output ports on the Line side of the PHY chip comprise output serializers of a second preset number, and the second preset number is larger than the first preset number; and the communication device is used for the exchange chip and the PHY chip to carry out command transmission. The application expands the output port of high-speed external exchange and improves the processing capacity of the exchange chip. The application also provides a switch simultaneously, has above-mentioned beneficial effect.
Description
Technical Field
The invention relates to the technical field of chip extension, in particular to a switch chip extension system and a switch.
Background
The exchange chip generally has 256 serializer serdes, and can extend 256 external exchange ports, but due to the chip design of the exchange chip, the chip can only utilize 144 serdes. And because the hardware process amount limits and the expandable space of the chip is limited, the quantity of the exchange ports which can be led out from the exchange chip is not large, the exchange flow led in through the expanded exchange ports is far lower than the normal processing capacity of the exchange chip, so that the processing capacity of the exchange chip is seriously wasted, the use efficiency of the exchange chip is reduced, and the service life of the exchange chip is also reduced when the exchange chip works for a long time under the normal power.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide a switch chip extension system and a switch, which can improve the processing capacity of a switch chip. The specific scheme is as follows:
the application provides a switching chip extension system, including:
the switching chip comprises a plurality of switching ports, and the switching ports comprise a first preset number of serializers;
a high-speed backplane connected to the switch port;
the PHY chip comprises an input port and an output port, the input serializers of the input port on the Host side of the PHY chip are connected with the serializers of the exchange port one by one through the high-speed back plate, the output port on the Line side of the PHY chip comprises a second preset number of output serializers, and the second preset number is larger than the first preset number;
and the communication device is used for carrying out command transmission between the exchange chip and the PHY chip.
Optionally, the first preset quantity is 2, the flow rate of the serializer is 50G, correspondingly, the second preset quantity is 4, and the flow rate of the output serializer is 25G.
Optionally, the switch chip is a TD chip.
Optionally, the switch chip is a TH3 chip.
Optionally, the PHY chip is a BCM 81724.
Optionally, the PHY chip is further configured to perform FEC forward error correction.
Optionally, the PHY chip is further configured to use a prbs error checking mechanism.
Optionally, the communication device is an MDC/MDIO control bus.
The application provides a switch, includes:
as in the switch chip expansion system described above,
a fiber optic module connected to the expansion system.
The application provides a switching chip extension system, including: the switching chip comprises a plurality of switching ports, and the switching ports comprise a first preset number of serializers; a high-speed backplane connected to the switch port; the PHY chip comprises an input port and an output port, the input serializers of the input port on the Host side of the PHY chip are connected with the serializers of the exchange ports one by one through the high-speed back plate, the output ports on the Line side of the PHY chip comprise output serializers of a second preset number, and the second preset number is larger than the first preset number; and the communication device is used for the exchange chip and the PHY chip to carry out command transmission.
It can be seen that, in the present application, the serializer of the switch chip is connected with the input port on the Host side of the PHY chip through the high-speed backplane, the input serializers of the input port correspond to the serializers one to one, the flow transmitted by the serializers of the first preset number enters the PHY chip through the corresponding input serializers, the PHY chip performs balanced distribution on the flow, the output serializers of the second preset number on the Line side of the PHY chip are output, and the second preset number is greater than the first preset number, thereby completing the expansion of the ports, expanding the output port of high-speed external switching, improving the processing capability of the switch chip, improving the use efficiency, and further improving the service life.
This application still provides a switch simultaneously, has above-mentioned beneficial effect, no longer gives unnecessary details here.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a switch chip expansion system according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a switch according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The chip exchange generally has 256 serializer serdes, and can expand 256 external exchange ports, but due to the chip design of the exchange chip, the chip can only utilize 144 serdes. And because the hardware process amount limits and the expandable space of the chip is limited, the quantity of the exchange ports which can be led out from the exchange chip is not large, the exchange flow led in through the expanded exchange ports is far lower than the normal processing capacity of the exchange chip, so that the processing capacity of the exchange chip is seriously wasted, the use efficiency of the exchange chip is reduced, and the service life of the exchange chip is also reduced when the exchange chip works for a long time under the normal power. In order to solve the above technical problem, the present embodiment provides an extended system of a switch chip, in which a serializer of the switch chip is connected to an input port on the Host side of a PHY chip through a high-speed backplane, input serializers of the input port correspond to serializers one to one, a first predetermined number of serializers transmit a flow to enter the PHY chip through the corresponding input serializers, the PHY chip performs balanced distribution on the flow, the output of the second preset number of output serializers on the Line side of the PHY chip is output, and the second preset number is larger than the first preset number, thereby completing the expansion of the ports, expanding the output ports of high-speed external exchange, improving the processing capacity of the exchange chip and the use efficiency, referring to fig. 1, fig. 1 is a schematic structural diagram of a switch chip expansion system according to an embodiment of the present disclosure, which includes:
a switch chip 100 including a plurality of switch ports 110, the switch ports 110 including a first preset number of serializers 111; a high-speed backplane 2002 connected to the switch port 110; the PHY chip 300 includes an input port 310 and an output port 320, the input serializer 311 of the input port 310 on the Host side of the PHY chip 300 is connected to the serializers 111 of the switch port 110 one by one through the high-speed backplane 200, and the output port 320 on the Line side of the PHY chip 300 includes a second preset number of output serializers 321, where the second preset number is greater than the first preset number; the communication device 400 is used for the exchange chip 100 and the PHY chip 300 to perform command transmission.
The switch chip 100 is not limited in this embodiment, and the switch chip 100 may be a TH chip, a TH2 chip, a TD chip, or a TH3 chip, and is used for being selectable in a user-defined manner. Preferably, the switch chip 100 is a TH3 chip. Generally, the switch chip 100 includes 256 serializers 111serdes, each or two serdes may constitute an external switch port 110, but due to the chip design of the switch chip 100 itself, the switch chip 100 has 128 switch ports 110 at the highest capacity, and the 128 switch ports 110 include 256 serdes at the highest. In the switch, the switch chip 100 is directly connected to the fiber module, so that the fiber module includes 4 lines, and each corresponding flow is 25G, therefore, four serdes of the switch chip 100 need to be utilized, and the flow of each serdes is 25G, which means that the introduced switch flow is far lower than the normal processing capability of the switch chip 100, and the processing capability of the switch chip 100 is seriously wasted.
In this embodiment, the switch chip 100 includes a plurality of switch ports 110, and the switch ports 110 include a first preset number of serializers 111, where the first preset number includes but is not limited to 1, 2, 3, and 4, as long as the purpose of this embodiment can be achieved. The first preset number of each switch port 110 of the switch chip 100 may be equal or different, and the user may set the first preset number according to actual requirements. For example, 128 switch ports 110 are included, wherein the first switch port includes a serializer a and a serializer B, and correspondingly, the input port 310 of the PHY chip 300 should include an input serializer a and an input serializer B, wherein the serializer a corresponds to the input serializer a, and the serializer B corresponds to the input serializer B. Correspondingly, according to the output requirement, the specification of the output serializer 321 of the output port 320 may be set, in an implementation, the output port 320 includes an output serializer 1, an output serializer 2, an output serializer 3, and an output serializer 4, at this time, the flow rates of the serializers a and b are added to obtain the first data; adding the flow of the input serializer A and the flow of the input serializer B to obtain second data; adding the flow rates of the output serializer 1, the output serializer 2, the output serializer 3 and the output serializer 4 to obtain third data; the first data, the second data, and the third data are all equal, and of course, the number of the output serializers 321 may be 5, as long as the number corresponds to the optical fiber module. It can be seen that the switching chip 100 extends the highest transmitted flow of the system to 56 × 256G.
Further to communication device 400, communication device 400 is used for command transmission between switch chip 100 and PHY chip 300. Specifically, a Host side serdes link of the PHY chip 300 is directly connected to a serdes link of the switching chip 100 through the high-speed backplane 200, and is mounted on the communication device 400, such as a PMDC/MDIO Bus, access and mode setting to the PHY chip 300 are completed through an MDIO control Bus, mapping from the Host side to a Line side port is configured reasonably, an internal mode and port mapping of the PHY chip 300 are configured, a required high-speed port is expanded, and a required port is expanded finally.
Based on the above technical solution, in the present embodiment, the serializer 111 of the switch chip 100 is connected to the input port 310 on the Host side of the PHY chip 300 through the high-speed backplane 200, the input serializers 311 of the input port 310 correspond to the serializers 111 one to one, the traffic transmitted by the serializers 111 of the first preset number enters the PHY chip 300 through the corresponding input serializers 311, the PHY chip 300 performs balanced distribution on the traffic, and the traffic is output through the output serializers 321 of the second preset number on the Line side of the PHY chip 300, where the second preset number is greater than the first preset number, so that the expansion of the ports is completed, the output port 320 of high-speed external switch is expanded, the processing capability of the switch chip 100 is improved, the use efficiency is improved, and the service life is further improved.
In an implementation, the first predetermined number is 2, the flow rate of the serializer 111 is 50G, and correspondingly, the second predetermined number is 4, and the flow rate of the output serializer 321 is 25G.
Specifically, one of the switch ports 110 of the switch chip 100 includes two serializers 111, and the flow rate of each serializer 111 is 50G, and the total flow rate is 100G. The Host side of the PHY chip 300 corresponds to the two input serializers 311 one-to-one, so the flow rates of the two input serializers 311 are both 50G, and the total flow rate is 100G. The Line side of the PHY chip 300 includes 4 output serializers 321 through the flow equalization distribution or the average distribution inside the PHY chip 300, and the flow of each of the 4 output serializers 321 is 25G. At this time, when the chips 1004 of the serializers 111 are originally required to be exchanged, only 2 serializers 111 are required to be used through chip extension, and the flow rate of the serializers 111 is increased from 25G to 50G, so that hardware damage caused by low flow rate for a long time is avoided, the utilization efficiency is improved, and the service life is prolonged.
The embodiment provides a specific switching chip 100 extension system, wherein the switching chip 100 is a TH3 chip; PHY chip 300 is BCM 81724. Correspondingly, PHY chip 300 is also used for FEC forward error correction. PHY chip 300 is also used for the prbs error checking mechanism.
In the design supporting the extension of the high-speed switch port by the switch chip TH3, the MAC side servers of the switch chip TH3 and the Host side servers of the BCM81724 are directly connected through the high-speed backplane 200 to extend a required port. The BCM81724 chip can support 56G at the highest for a single servers link and 400G at the highest for a single port, can meet the expansion requirement of a TH3 high-speed port, supports PAM4 and FEC forward error correction functions, can ensure the stability and reliability of the link during high-speed docking, and supports a prbs error check mechanism. The prbs error detection of various schemes can assist the debugging and problem location of the switch. It is understood that the expansion of the switch port 110 means the expansion of the switch traffic, and the expansion of the switch traffic can effectively increase the value of the switch, thereby increasing the competitiveness of the product.
In this embodiment, a BCM81724 chip is used, a Host side serdes link of the BCM81724 chip is directly connected with a switch chip serdes link through a high-speed backplane, and is mounted on an MDC/MDIO Bus, access and mode setting to the BCM81724 are completed through an MDIO control Bus, Host side to Line side port mapping of the BCM81724 chip is configured reasonably, an internal mode and port mapping of the BCM81724 are configured, a required high-speed port is expanded, and a required port is expanded finally. That is to say, using the BCM81724 chip, directly connecting a Host side serdes link of the BCM81724 chip with a switching chip 100serdes link through a backplane, mounting the link on an MDC/MDIO Bus, completing access and mode setting to the BCM81724 through an MDIO control Bus, reasonably configuring mapping from the Host side to a Line side port, and finally expanding a required port.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a switch provided in an embodiment of the present application, where the switch described below and the switch chip expansion system described above may be referred to correspondingly, and the switch includes:
the switch chip expansion system of any of the above,
a fiber optic module 500 connected to an expansion system.
Since the embodiment of the switch corresponds to the embodiment of the switch chip extension system part, please refer to the description of the embodiment of the switch chip extension system part, which is not repeated here.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
A switch chip extension system and a switch provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (9)
1. A switch chip expansion system, comprising:
the switching chip comprises a plurality of switching ports, and the switching ports comprise a first preset number of serializers;
a high-speed backplane connected to the switch port;
the PHY chip comprises an input port and an output port, the input serializers of the input port on the Host side of the PHY chip are connected with the serializers of the exchange port one by one through the high-speed back plate, the output port on the Line side of the PHY chip comprises a second preset number of output serializers, and the second preset number is larger than the first preset number;
and the communication device is used for carrying out command transmission between the exchange chip and the PHY chip.
2. The switch chip expansion system according to claim 1, wherein the first predetermined number is 2, the flow rate of the serializer is 50G, and correspondingly, the second predetermined number is 4, and the flow rate of the output serializer is 25G.
3. The switch chip expansion system of claim 1, wherein the switch chip is a TD chip.
4. The switch chip expansion system of claim 1, wherein the switch chip is a TH3 chip.
5. The switch chip expansion system of claim 4, wherein the PHY chip is a BCM 81724.
6. The switch chip extension system of claim 4, wherein the PHY chip is further configured for FEC forward error correction.
7. The switch chip extension system of claim 4, wherein the PHY chip is further configured for a prbs error checking mechanism.
8. The switch chip expansion system according to claim 1, wherein the communication device is an MDC/MDIO control bus.
9. A switch, comprising:
the switch chip expansion system of any one of claims 1 to 8,
a fiber optic module connected to the expansion system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010108500.2A CN111277519A (en) | 2020-02-21 | 2020-02-21 | Exchange chip extension system and switch |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010108500.2A CN111277519A (en) | 2020-02-21 | 2020-02-21 | Exchange chip extension system and switch |
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| CN111277519A true CN111277519A (en) | 2020-06-12 |
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| CN202010108500.2A Pending CN111277519A (en) | 2020-02-21 | 2020-02-21 | Exchange chip extension system and switch |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120250679A1 (en) * | 2011-03-29 | 2012-10-04 | Amazon Technologies, Inc. | Network Transpose Box and Switch Operation Based on Backplane Ethernet |
| CN103944738A (en) * | 2014-04-14 | 2014-07-23 | 贵州电力试验研究院 | Interchanger supporting function extension |
| CN104580028A (en) * | 2015-01-06 | 2015-04-29 | 盛科网络（苏州）有限公司 | Switch chip message processing method and device based on expansion interfaces |
| CN106330782A (en) * | 2015-06-30 | 2017-01-11 | 中兴通讯股份有限公司 | Port capacity distribution method and device, and switch service board |
| CN108809864A (en) * | 2018-06-15 | 2018-11-13 | 中国电子科技集团公司第四十研究所 | A kind of multi-thread card high density TAP interchangers based on FPGA |
| CN109818941A (en) * | 2019-01-04 | 2019-05-28 | 烽火通信科技股份有限公司 | Realize that 10GE interface equipment supports the system and method for 25GE interface |
-
2020
- 2020-02-21 CN CN202010108500.2A patent/CN111277519A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120250679A1 (en) * | 2011-03-29 | 2012-10-04 | Amazon Technologies, Inc. | Network Transpose Box and Switch Operation Based on Backplane Ethernet |
| CN103944738A (en) * | 2014-04-14 | 2014-07-23 | 贵州电力试验研究院 | Interchanger supporting function extension |
| CN104580028A (en) * | 2015-01-06 | 2015-04-29 | 盛科网络（苏州）有限公司 | Switch chip message processing method and device based on expansion interfaces |
| CN106330782A (en) * | 2015-06-30 | 2017-01-11 | 中兴通讯股份有限公司 | Port capacity distribution method and device, and switch service board |
| CN108809864A (en) * | 2018-06-15 | 2018-11-13 | 中国电子科技集团公司第四十研究所 | A kind of multi-thread card high density TAP interchangers based on FPGA |
| CN109818941A (en) * | 2019-01-04 | 2019-05-28 | 烽火通信科技股份有限公司 | Realize that 10GE interface equipment supports the system and method for 25GE interface |
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Application publication date: 20200612 |