CN111276477B

CN111276477B - Electrostatic discharge protection device

Info

Publication number: CN111276477B
Application number: CN201811480568.2A
Authority: CN
Inventors: 汪广羊
Original assignee: CSMC Technologies Fab2 Co Ltd
Current assignee: CSMC Technologies Fab2 Co Ltd
Priority date: 2018-12-05
Filing date: 2018-12-05
Publication date: 2022-08-12
Anticipated expiration: 2038-12-05
Also published as: CN111276477A

Abstract

The invention relates to an electrostatic discharge protection device, which comprises a first GGNMOS device and a second GGNMOS device which are adjacent, wherein the first GGNMOS device and the second GGNMOS device respectively comprise: a well region; the first conductive type doping area is arranged in the well area and comprises a drain area and a source area; and a gate electrode disposed above a region between the drain region and the source region; the first GGNMOS device and the second GGNMOS device comprise a plurality of GGNMOS transistors, and each GGNMOS transistor comprises a grid, a source region at one side of the grid and a drain region at the other side of the grid; the GGNMOS transistor closest to the two GGNMOS devices is the GGNMOS transistor with the largest DCG, and the DCG is the distance from the drain contact hole to the grid of the GGNMOS transistor. The invention enlarges the DCG of the GGNMOS transistor at the nearest position, can provide better ESD protection capability aiming at the extreme condition, and optimizes the ESD performance between the input and output ports. And the area utilization rate of the wafer is higher, and the manufacturing cost is reduced.

Description

Electrostatic discharge protection device

Technical Field

The present invention relates to electrostatic discharge (ESD) protection, and more particularly, to an ESD protection device.

Background

GGNMOS (Gate group NMOS, i.e., grounded Gate NMOS) is a common CMOS ESD protection device. When more Pin pins are led out from a chip, more GGNMOS protection ports are used, which results in that the GGNMOS needs to occupy a larger wafer (wafer) area.

In order to save more wafer area, one scheme is to remove the N well isolated between the GGNMOSs, so that the GGNMOSs share the P sub leading-out region, and save more area. But this will result in a reduced ESD protection capability of the GGNMOS due to the parasitic NPN turn-on.

Disclosure of Invention

Accordingly, there is a need for an ESD protection device with better ESD protection capability.

An electrostatic discharge protection device comprising first and second adjacent GGNMOS devices, each comprising: a well region of a second conductivity type; the first conductive type doping area is arranged in the well area and comprises a drain area and a source area; and a gate electrode disposed above a region between the drain region and the source region; the first conduction type and the second conduction type are opposite conduction types, the first GGNMOS device and the second GGNMOS device respectively comprise a plurality of GGNMOS transistors, and each GGNMOS transistor comprises a grid, a source region at one side of the grid and a drain region at the other side of the grid; in the first GGNMOS device, the first GGNMOS transistor is the GGNMOS transistor with the largest DCG; in the second GGNMOS device, the second GGNMOS transistor is the GGNMOS transistor with the largest DCG; the first GGNMOS transistor and the second GGNMOS transistor are respectively one of the first GGNMOS device and the second GGNMOS device and the GGNMOS transistor closest to the junction of the first GGNMOS device and the second GGNMOS device, and the DCG is the distance from a drain contact hole to a grid of the GGNMOS transistor.

In one embodiment, the GGNMOS transistors of the first and second GGNMOS devices are arranged in a first direction.

In one embodiment, the first and second GGNMOS devices are a cyclic arrangement of source region-gate-drain region-gate-source region-gate-drain region-gate in a first direction.

In one embodiment, for the first GGNMOS device, the DCG of the GGNMOS transistor is greater closer to the intersection; for the second GGNMOS device, the DCG of the GGNMOS transistor is larger closer to the intersection.

In one embodiment, the first and second GGNMOS devices each comprise more than two sets of GGNMOS transistors, each set of GGNMOS transistors consisting of two adjacent GGNMOS transistors, each set of GGNMOS transistors sharing a drain region, the DCGs of each set of GGNMOS transistors being equal.

In one embodiment, the well region further includes a lead-out region formed on the surface of the well region, the lead-out region is of the second conductivity type, and the lead-out region includes the first structure located at the boundary.

In one embodiment, the extraction region further includes second structures located on both sides of the first and second GGNMOS devices in a second direction, the second structures extending in the first direction, the second direction being perpendicular to the first direction.

In one embodiment, the semiconductor device further comprises an isolation structure formed between the extraction region and the first conductive type doped region.

In one embodiment, the first GGNMOS device is connected with one input/output port of the chip to perform electrostatic discharge protection on the input/output port, and the second GGNMOS device is connected with one input/output port adjacent to the input/output port to perform electrostatic discharge protection on the connected input/output port.

In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

The electrostatic discharge protection device can enhance the ESD capability of the GGNMOS transistor by increasing the DCG of the nearest GGNMOS transistor of the adjacent GGNMOS device (namely, the DCG of the GGNMOS device is set to be the largest GGNMOS transistor of the GGNMOS device), and because the drain resistance of the GGNMOS transistor is increased, part of ESD discharge current can be transferred to other GGNMOS transistors with smaller DCG for discharge. According to the foregoing, the situation that two adjacent GGNMOS devices are biased in a forward direction and a reverse direction, which are extreme and easily cause ESD failure, is also a test item of the ESD test, and the nearest GGNMOS transistor is most easily subjected to ESD failure under such a condition. Therefore, the DCG of the nearest GGNMOS transistor is enlarged, better ESD protection capability can be provided for the extreme condition, and ESD performance between the input and output ports can be optimized.

Drawings

For a better understanding of the description and/or illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the presently understood best modes of these inventions.

FIG. 1 is a schematic diagram of a GGNMOS device connected to two adjacent input/output ports of a chip;

fig. 2 is a layout of a partial structure of two adjacently disposed GGNMOS devices in an embodiment.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

Fig. 1 is a schematic diagram of a GGNMOS device connected to two adjacent input-output (IO) ports of a chip. The drain electrode of the first GGNMOS device is connected with the first input/output port IO _1, and the grid electrode and the source electrode are grounded so as to perform electrostatic discharge protection on the first input/output port IO _ 1; the drain electrode of the second GGNMOS device is connected with the second input/output port IO _2, and the grid electrode and the source electrode are grounded so as to perform electrostatic discharge protection on the second input/output port IO _ 2. It is considered that ESD failure and chip destruction are most likely to occur when two adjacent input/output ports are charged with positive and negative voltages, for example, when a first GGNMOS device is biased forward and a second GGNMOS device is biased backward. Therefore, when an ESD test is performed, an ESD event between the first input/output port IO _1 and the second input/output port IO _2 includes that one IO port is positively charged and one IO port is negatively charged.

In one embodiment, the electrostatic discharge protection device comprises two adjacent GGNMOS devices. Fig. 2 is a layout of a partial structure of two adjacently disposed GGNMOS devices in an embodiment, where GGNMOS1 corresponds to the first GGNMOS device in fig. 1 and GGNMOS2 corresponds to the second GGNMOS device in fig. 1. GGNMOS1 and GGNMOS2 each include a well region (not shown in fig. 2), a first-conductivity-type doped region (not shown in fig. 2), and a gate (gate 120 in GGNMOS1 and gate 220 in GGNMOS 2).

Wherein the well region is of the second conductivity type. Doped regions of the first conductivity type are provided in the well region and include drain and source regions (drain region 114 and source region 112 for GGNMOS1 and drain region 214 and source region 212 for GGNMOS 2). In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the well region is a P-well, and the first conductivity type doped region is an N + doped region; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

Taking GGNMOS1 as an example, gate 120 is disposed over the region between drain region 114 and source region 112. Referring to fig. 2, the GGNMOS1 and 2 each include a plurality of GGNMOS transistors, each of which GGNMOS1 includes a gate 120, a source region 114 on one side of the gate 120, and a drain region 112 on the other side.

In the invention, the distance from a drain contact hole (a black square in fig. 2 is a contact hole) of the GGNMOS transistor to the grid 120 is marked as DCG, and in the GGNMOS1, the GGNMOS transistor closest to the junction of the GGNMOS1 and the GGNMOS2 is the GGNMOS transistor with the largest DCG; in the GGNMOS2, the GGNMOS transistor closest to the junction of GGNMOS1 and GGNMOS2 is the largest DCG GGNMOS transistor. For the embodiment of fig. 2, DCG1> DCG2> DCG3 … …, i.e., the closer to the intersection of GGNMOS1 and GGNMOS2, the larger the DCG of the GGNMOS transistor for GGNMOS 1; likewise, for GGNMOS2, the closer to the intersection of GGNMOS1 and GGNMOS2, the larger DCG of the GGNMOS transistor. The method is different from the conventional method in which DCGs are equal (i.e., DCG1 ═ DCG2 ═ DCG3 … …). Wherein, there may be more than one, for example two, GGNMOS transistors with the largest DCG in each GGNMOS; the common drain GGNMOS transistors may be considered to be equidistant from the interface.

The ellipses on both sides of fig. 2 indicate that the GGNMOS1 and GGNMOS2 may include more GGNMOS transistors, which are omitted from the figure.

In the embodiment shown in fig. 2, the GGNMOS transistors of GGNMOS1 and GGNMOS2 are arranged in a first direction (i.e., lateral in fig. 2). Specifically in the order of source region-gate-drain region-gate-source region-gate-drain region-gate … ….

In the embodiment shown in fig. 2, GGNMOS1 and GGNMOS2 each include more than two sets of GGNMOS transistors, each set of GGNMOS transistors consisting of two adjacent GGNMOS transistors, each set of GGNMOS transistors sharing a drain region, the DCGs of each set of GGNMOS transistors being equal.

In one embodiment, the esd protection device further comprises a lead-out region formed on the surface of the well region, wherein the lead-out region is of the second conductivity type. Referring to fig. 2, in this embodiment, the lead-out region is a P-sub lead-out region, and includes a first structure 32 located at the intersection of GGNMOS1 and GGNMOS2, and also includes a second structure 34 located on both sides of GGNMOS1 and GGNMOS2 in a second direction (i.e., a longitudinal direction in fig. 2), the second structure extending in the first direction, and the second direction being perpendicular to the first direction.

In the embodiment shown in fig. 2, two adjacent GGNMOS devices GGNMOS1 and GGNMOS2 share the lead-out region, and no N-well is arranged between the GGNMOS1 and the GGNMOS2 for isolation, so that the wafer area occupied by the electrostatic discharge protection device can be saved, and the manufacturing cost can be reduced.

In one embodiment, the doping concentration of the extraction region is greater than the doping concentration of the well region.

In one embodiment, the electrostatic discharge protection device further includes an isolation structure formed between the extraction region and the first conductive-type doped region. In one embodiment, the isolation structure may be silicon oxide, such as Shallow Trench Isolation (STI) or field oxide layer formed by LOCOS process.

In one embodiment, the gate 120 (and gate 220) is polysilicon.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. An electrostatic discharge protection device comprising a first and a second adjacent GGNMOS device, wherein each of the first and second GGNMOS devices comprises:

a well region of a second conductivity type;

the first conductive type doping area is arranged in the well area and comprises a drain area and a source area; and

the grid is arranged above the region between the drain region and the source region;

the first conduction type and the second conduction type are opposite conduction types, the first GGNMOS device and the second GGNMOS device respectively comprise a plurality of GGNMOS transistors, and each GGNMOS transistor comprises a grid, a source region at one side of the grid and a drain region at the other side of the grid; in the first GGNMOS device, the first GGNMOS transistor is the GGNMOS transistor with the largest DCG; in the second GGNMOS device, the second GGNMOS transistor is the GGNMOS transistor with the largest DCG; the first GGNMOS transistor and the second GGNMOS transistor are respectively one of the first GGNMOS device and the second GGNMOS device and the GGNMOS transistor closest to the junction of the first GGNMOS device and the second GGNMOS device, and the DCG is the distance from a drain contact hole to a grid of the GGNMOS transistor.

2. The electrostatic discharge protection device according to claim 1, wherein each of the first and second GGNMOS devices is arranged in a first direction.

3. The electrostatic discharge protection device of claim 2, wherein the first and second GGNMOS devices are a cyclic arrangement of source region-gate-drain region-gate-source region-gate-drain region-gate in the first direction.

4. The electrostatic discharge protection device of claim 3, wherein the DCG of the GGNMOS transistor is larger closer to the intersection for the first GGNMOS device; for the second GGNMOS device, the DCG of the GGNMOS transistor is larger closer to the intersection.

5. The electrostatic discharge protection device according to claim 4, wherein the first and second GGNMOS devices each comprise more than two groups of GGNMOS transistors, each group of GGNMOS transistors consists of two adjacent GGNMOS transistors, each group of GGNMOS transistors shares one drain region, and DCGs of each group of GGNMOS transistors are equal.

6. The ESD protection device of claim 2 further comprising an extraction region formed on a surface of the well region, wherein the extraction region is of the second conductivity type, and the extraction region includes the first structure at the interface.

7. The electrostatic discharge protection device according to claim 6, wherein the extraction region further comprises second structures located on both sides of the first and second GGNMOS devices in a second direction, the second structures extending in the first direction, the second direction being perpendicular to the first direction.

8. The ESD protection device of claim 6 further comprising an isolation structure formed between the extraction region and the first-conductivity-type-doped region.

9. The esd protection device of claim 1, wherein the first GGNMOS device connects an input/output port of a chip for esd protection, and the second GGNMOS device connects an input/output port adjacent to the input/output port for esd protection.

10. The esd protection device of any one of claims 1-9, wherein the first conductivity type is N-type and the second conductivity type is P-type.