CN116666375A - Electrostatic protection structure, forming method thereof, embedded d-TOF chip and SiPM chip - Google Patents

Electrostatic protection structure, forming method thereof, embedded d-TOF chip and SiPM chip Download PDF

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Publication number
CN116666375A
CN116666375A CN202210158088.4A CN202210158088A CN116666375A CN 116666375 A CN116666375 A CN 116666375A CN 202210158088 A CN202210158088 A CN 202210158088A CN 116666375 A CN116666375 A CN 116666375A
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doped region
diode
electrostatic protection
chip
ohmic contact
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张斯日古楞
阎大勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202210158088.4A priority Critical patent/CN116666375A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application provides an electrostatic protection structure and a forming method thereof, an embedded d-TOF chip and an SiPM chip, wherein the electrostatic protection structure comprises: a semiconductor substrate, wherein the semiconductor substrate comprises a first diode with a first conducting voltage, and a first end of the first diode is electrically connected with a common high-voltage end welding pad of the embedded d-TOF chip or the SiPM chip; the polycrystalline silicon layer comprises a second diode with a second conduction voltage, a first end of the second diode is connected with a second end of the first diode in series, and the second end of the second diode is electrically connected with a grounding terminal welding pad of the embedded d-TOF chip or the SiPM chip; the electrostatic protection structure guides the voltage which is larger than or equal to the sum of the first conducting voltage and the second conducting voltage on the common high-voltage end welding pad into the grounding end welding pad. The electrostatic protection structure of the technical scheme of the application can solve the problem of insufficient Trigger voltage of the high-voltage electrostatic protection device.

Description

Electrostatic protection structure, forming method thereof, embedded d-TOF chip and SiPM chip
Technical Field
The application relates to the field of semiconductor structures, in particular to an electrostatic protection structure, a forming method thereof, an embedded d-TOF chip and an SiPM chip.
Background
A single photon detection avalanche diode (Single Photon Avalanche Diode, SPAD) is the only solution currently implemented as a direct-Time Of flight (d-TOF) sensor. With the vigorous demands of the fields of automatic driving, AR/VR and the like for 3D imaging, the technology for realizing D-TOF sensing by 3D stacking is mature. When the large array of 3D stacked D-TOF chips is applied to mobile devices such as mobile phones for imaging, the working voltage of SPAD cannot be greater than 25V due to power consumption. In some intelligent home appliances, only a small amount of SPAD is needed, so an embedded integration scheme, namely an embedded d-TOF chip, is usually adopted. In order to improve the detection efficiency of the embedded d-TOF chip, the working voltage of the SPAD is often increased. In addition, on-board line scan radar (Lidar) applications are also gradually using silicon photomultiplier (SiPM) composed of SPAD arrays instead of earlier technologies.
In these applications, the working voltage of SPAD is usually relatively high, so that a higher requirement is put on the Trigger voltage (Trigger voltage) of the electrostatic protection device in the corresponding application.
Disclosure of Invention
The application aims to solve the technical problem of providing the electrostatic protection structure compatible with the embedded d-TOF and SiPM application platforms, and meanwhile, a photomask is not added in the process of integration of the electrostatic protection structure, the technological process is not changed, and the problem of insufficient Trigger voltage of a high-voltage electrostatic protection device can be solved.
In order to solve the above technical problems, the present application provides an electrostatic protection structure integrated on an embedded d-TOF chip or SiPM chip, comprising: a semiconductor substrate, wherein the semiconductor substrate comprises a first diode with a first conducting voltage, and a first end of the first diode is electrically connected with a common high-voltage end welding pad of the embedded d-TOF chip or the SiPM chip; a polysilicon layer on a portion of the semiconductor substrate and isolated from the semiconductor substrate by an isolation structure in the semiconductor substrate, the polysilicon layer including a second diode having a second turn-on voltage, a first end of the second diode being in series with a second end of the first diode, the second end of the second diode being electrically connected to a ground pad of the embedded d-TOF chip or SiPM chip; the electrostatic protection structure guides the voltage which is larger than or equal to the sum of the first conducting voltage and the second conducting voltage on the common high-voltage end welding pad into the grounding end welding pad.
In some embodiments of the application, the first diode comprises: at least one first doped region electrically connected with the common high-voltage terminal bonding pad through a metal interconnection structure; at least one second doped region having a doping type different from that of the first doped region, and electrically connected to the first end of the second diode through the first interlayer metal layer of the metal interconnection structure.
In some embodiments of the present application, the first doped regions and the second doped regions are alternately arranged to form a multi-fingered first diode.
In some embodiments of the present application, the first doped region is P-type doped and the second doped region is N-type doped.
In some embodiments of the present application, the first doped region is N-type doped and the second doped region is P-type doped; the first diode further comprises an N-type buried layer, and the N-type buried layer is connected with the bottom of the adjacent first doped region.
In some embodiments of the present application, a distance between the first doped region and the second doped region is 0.3 μm to 2 μm, and a width of the first doped region is not less than 0.6 μm.
In some embodiments of the present application, a first ohmic contact layer is further included between the first doped region and the metal interconnection structure, a second ohmic contact layer is further included between the second doped region and the first interlayer metal layer, and the first ohmic contact layer and the second ohmic contact layer are isolated by an isolation structure.
In some embodiments of the present application, the lengths of the first ohmic contact layer and the second ohmic contact layer are not less than 30 μm, and the sum of the lengths of all the first ohmic contact layer and all the second ohmic contact layer is not less than 300 μm.
In some embodiments of the application, the second diode comprises: at least one third doped region having a doping type different from that of the second doped region and electrically connected to the second doped region through the first interlayer metal layer; at least one fourth doped region, which is different from the doping type of the third doped region, is electrically connected to the ground terminal pad through the metal interconnection structure.
In some embodiments of the application, the third doped region and the fourth doped region are alternately arranged to form a multi-fingered second diode.
In some embodiments of the application, the distance between the third doped region and the fourth doped region is greater than 0 and no more than 1 μm.
In some embodiments of the present application, a third ohmic contact layer is further included in the third doped region, a fourth ohmic contact layer is further included in the fourth doped region, and a SAB layer is further included on the polysilicon layer, the third doped region, and the fourth doped region between the third ohmic contact layer and the fourth ohmic contact layer.
In some embodiments of the present application, the lengths of the third ohmic contact layer and the fourth ohmic contact layer are not less than 20 μm, and the sum of the lengths of all the third ohmic contact layer and all the fourth ohmic contact layer is not less than 500 μm.
The application also provides a forming method of the electrostatic protection structure, which comprises the following steps: providing a semiconductor substrate; forming a first diode in the semiconductor substrate; forming a polysilicon layer on a part of the semiconductor substrate, wherein the polysilicon layer is isolated from the semiconductor substrate by an isolation structure positioned in the semiconductor substrate; forming a second diode in the polysilicon layer; electrically connecting a second end of the first diode with a first end of the second diode; and electrically connecting the first end of the first diode with a common high-voltage end welding pad of the embedded d-TOF chip or the SiPM chip, and electrically connecting the second end of the second diode with a grounding end welding pad of the embedded d-TOF chip or the SiPM chip.
The application also provides an embedded d-TOF chip, which comprises: a common voltage terminal pad and a ground terminal pad; d-TOF device connected with the common voltage terminal welding pad and the grounding terminal welding pad; the electrostatic protection structure is connected with the common voltage terminal welding pad and the grounding terminal welding pad.
In some embodiments of the application, the d-TOF device comprises: at least one single photon avalanche diode connected to the common high voltage terminal pad; a time-to-digital converter connected to the single photon avalanche diode; a reset circuit connecting the single photon avalanche diode and an operating voltage; and the quenching circuit is connected with the single photon avalanche diode and the grounding terminal welding pad.
The present application also provides an SiPM chip comprising: a common voltage terminal pad and a ground terminal pad; an SiPM device connected with the common voltage terminal welding pad and the grounding terminal welding pad; the electrostatic protection structure is connected with the common voltage terminal welding pad and the grounding terminal welding pad.
In some embodiments of the present application, the SiPM device comprises a plurality of active pixels, each active pixel comprises at least one unit consisting of a single photon avalanche diode and a polysilicon quenching resistor connected in series, each unit is connected in parallel, one end of the unit is connected with the common high voltage end welding pad, and the other end of the unit is connected with the grounding end welding pad.
Compared with the prior art, the technical scheme of the application has the following beneficial effects:
the electrostatic protection structure of the technical scheme of the application can be compatible and integrated on an embedded d-TOF chip or an SiPM chip, and the first end of the first diode is electrically connected with a common high-voltage end welding pad of the embedded d-TOF chip or the SiPM chip, so that the second end of the second diode is electrically connected with a grounding end welding pad of the embedded d-TOF chip or the SiPM chip, and the voltage which is larger than or equal to the sum of the first conducting voltage and the second conducting voltage on the common high-voltage end welding pad can be led into the grounding end welding pad, thereby protecting devices on the embedded d-TOF chip or the SiPM chip from being damaged by high voltage, and simultaneously solving the problem of insufficient Trigger voltage of the existing electrostatic protection device.
In the method for forming the electrostatic protection structure, the process flow of the embedded d-TOF chip or the SiPM chip is not changed in the integration process, wherein the third doping region and the fourth doping region of the second diode, the third ohmic contact layer and the fourth ohmic contact layer can be realized in the same layer, so that a photomask is not required to be added, and the first ohmic contact layer, the second ohmic contact layer, the third ohmic contact layer and the fourth ohmic contact layer can be formed in the same process, thereby greatly reducing the manufacturing cost.
The embedded d-TOF chip and the SiPM chip adopting the technical scheme of the application can be better suitable for workplaces with higher requirements on working voltage due to the adoption of the electrostatic protection structure.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description only and are not intended to limit the scope of the application, as other embodiments may equally well accomplish the inventive intent in this disclosure. It should be understood that the drawings are not to scale. Wherein:
fig. 1 to 8 are schematic structural diagrams illustrating steps in a method for forming an electrostatic protection structure according to an embodiment of the present application;
FIG. 9 is a schematic diagram of an embedded d-TOF chip according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of an SiPM chip according to an embodiment of the application.
Detailed Description
The following description provides specific applications and requirements of the application to enable any person skilled in the art to make and use the application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
At present, the SPAD and TDC low-voltage logic circuits in the embedded d-TOF chip are often isolated by a deep well, but the maximum voltage of the deep well isolation usually cannot meet the requirement of triggering voltage of an electrostatic protection device. In addition, the SiPM chip has no logic circuit, the number of the light shield layers for ion implantation is relatively small, and the requirement for realizing high-voltage electrostatic protection of on-chip integration is very strict. Therefore, the technical scheme of the application provides a high-voltage electrostatic protection structure which can be compatible with two application platforms of embedded d-TOF and SiPM, and meanwhile, the integration process is realized under the conditions of not increasing a photomask and not changing the process flow, and the problem of insufficient Trigger voltage of the existing high-voltage electrostatic protection device can be solved.
The electrostatic protection structure and the forming method thereof, the embedded d-TOF chip and the SiPM chip according to the technical scheme of the application are described in detail below with reference to the embodiments and the accompanying drawings.
Referring to fig. 1, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 may be at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors, also include multilayer structures of the above materials or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and the like. In the embodiment of the present application, the constituent material of the semiconductor substrate 100 is monocrystalline silicon. The semiconductor substrate 100 may be lightly doped according to practical situations. The semiconductor substrate 100 includes an electrostatic protection region 110, and the electrostatic protection region 110 is used to fabricate an electrostatic protection structure according to an embodiment of the present application. In some embodiments, the semiconductor substrate 100 may further include a logic device region 120, where the logic device region 120 may be used to fabricate, for example, a low voltage MOS transistor, such as an embedded d-TOF chip, and an LV-PMOS or LV-NMOS may be fabricated in the logic device region 120. While for SiPM chips there is no logic device region 120 to the right in fig. 1. Other device structures for the embedded d-TOF chip and SiPM chip may be designed in the prior art, and are not shown. Since the electrostatic protection structures of the embedded d-TOF chip and the SiPM chip and the forming method thereof are substantially the same, the electrostatic protection structure of the embedded d-TOF chip and the forming method thereof will be mainly described below as an example.
With continued reference to fig. 1, a first isolation structure 111 is formed in the semiconductor substrate 100 of the electrostatic protection region 110 and logic device region 120 for forming an electrical isolation. The first isolation structure 111 may be a Shallow Trench Isolation (STI). The first isolation structure 111 may be formed in one process with the isolation structures in the embedded d-TOF chip and SiPM chip. Then, a first diode is formed in the semiconductor substrate 100 of the electrostatic protection region 110. The first diode includes a first doped region 113 and a second doped region 114 that are isolated by the first isolation structure 111 and have different doping types, where the first doped region 113 and the second doped region 114 may be P-type doped or N-type doped, and if the doping types of the first doped region 113 and the second doped region 114 are reversed, the electrostatic protection structure is changed in structure, and the case that the first doped region 113 is P-type doped and the second doped region 114 is N-type doped will be described below.
The number of the first doped regions 113 and the second doped regions 114 may be one or more, and if the number of the first doped regions 113 and the second doped regions 114 is plural, the first doped regions 113 and the second doped regions 114 are alternately arranged to form a multi-finger first diode, one of which is shown in fig. 2. The distance between the first doped region 113 and the second doped region 114 is 0.3 μm to 2 μm, and if the distance is too small, the Trigger voltage is too low, and if the distance is too large, the on-resistance is too high, so that the electrostatic discharge capability is reduced. The width W1 of the first doped region 113 is not less than 0.6 μm, and the width of the second doped region 114The degree W2 is not less than 0.4 μm, the widths W1 and W2 are mainly determined by ion implantation and photolithography processes, in order to increase the on-resistance of the first diode after reverse breakdown, it is necessary to make the first doped region 113 and the second doped region 114 have a certain depth, a higher energy implantation is required during the corresponding ion implantation, the regions other than the first doped region 113 and the second doped region 114 need to be blocked by photoresist, a thicker photoresist is required for the high energy ion implantation, and the minimum opening size of the thick photoresist determines the widths W1 and W2. The number of the first doped regions 113 and the second doped regions 114 is determined in accordance with the device size and the electrostatic protection capability. When the lengths of the first doped region 113 and the second doped region 114 are about 30 μm, the total number of the first doped region 113 and the second doped region 114 is 10 to 100, and the specific number is determined by the requirement of electrostatic protection, such as HBM 2KV or others, and the higher the requirement of electrostatic protection, the more the total number of the first doped region 113 and the second doped region 114. Only two of the first doped regions 113 and one of the second doped regions 114 are shown in fig. 1. The first doped region 113 and the second doped region 114 may be formed in one process with the corresponding doped regions in the embedded d-TOF chip and SiPM chip, so that the depth and doping concentration of the first doped region 113 and the second doped region 114 may be referenced to the corresponding doped regions in the embedded d-TOF chip and SiPM chip. In some embodiments, the depth of the first doped region 113 is 1.5 μm to 2.5 μm, and the doping concentration is 5e16cm -3 ～1e18cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the second doped region 114 is 1 μm to 1.5 μm, and the doping concentration is 5e16cm -3 ～1e18cm -3 。
In some embodiments, a method of forming the first diode includes: forming the first doped region 113 in the semiconductor substrate 100 of the electrostatic protection region 110; forming a deep N-well region 121 in the logic device region 120 and a portion of the semiconductor substrate 100 of the electrostatic protection region 110; forming the second doped region 114 in the semiconductor substrate 100 of the electrostatic protection region 110; an N-well 122 is formed in the semiconductor substrate 100 of the logic device region 120 and the deep N-well region 121, wherein the first doped region 113 and the second doped region 114 constitute the first diode. Since the deep N-well region 121 and the N-well 122 are both existing structures in the embedded d-TOF chip, the first doped region 113 and the second doped region 114 may be formed in one process together with the corresponding doped regions in the embedded d-TOF chip and the SiPM chip, so that no new process steps are introduced when forming the first diode in the embodiment of the present application.
After the first diode is formed, a second isolation structure 112 is formed. The second isolation structure is used for isolating the first diode and other adjacent devices. The second isolation structure 112 may be a Deep Trench Isolation (DTI), which may be implemented by a self-aligned DTI process.
Referring to fig. 3, a polysilicon layer 115 is formed at the electrostatic protection region 110, and the polysilicon layer 115 is isolated from the semiconductor substrate 100 by an isolation structure 111 located in the semiconductor substrate 100. The gate oxide layer of the logic device region 120 may be formed prior to forming the polysilicon layer 115. The polysilicon layer 115 of the electrostatic protection region 110 and the polysilicon gate 123 of the logic device region 120 may be formed in the same process. Then, a second diode is formed in the polysilicon layer 115. The second diode includes one or more third doped regions 118 and one or more fourth doped regions 119, and when the third doped regions 118 and the fourth doped regions 119 are each plural, the third doped regions 118 and the fourth doped regions 119 are alternately arranged to form a multi-finger second diode, referring to fig. 4. The distance between the third doped region 118 and the fourth doped region 119 is greater than 0 and not more than 1 μm, because in the low voltage logic circuit process platform, the polysilicon used as the gate terminal is usually an Undoped POLY, and the conductivity of the material is relatively high, so that the electrostatic discharge capability is reduced when the distance between the third doped region 118 and the fourth doped region 119 is too large. The width W3 of the third doped region 118 and the width W4 of the fourth doped region 119 should be greater than 0.3 μm. In order to reduce the contact resistance, the ohmic alloy layer SA is formed on the surface of the polysilicon layer 115, but the polysilicon layer 115 has no isolation structure, so when the width W3 and the width W4 are too small, surface leakage may occur between the ohmic alloy layers SA, and the reliability of the electrostatic protection structure of the present application may be affected in practical application. The number of the third doped regions 118 and the fourth doped regions 119 is determined according to the device size and the electrostatic protection capability, and when the lengths of the third doped regions 118 and the fourth doped regions 119 are about 30 μm, the total number of the third doped regions 118 and the fourth doped regions 119 is 10-100, the specific number is determined by the requirement of electrostatic protection, such as HBM 2KV or others, and the higher the requirement of electrostatic protection, the more the total number of the third doped regions 118 and the fourth doped regions 119 is, so that the total length of the third doped regions 118 and the fourth doped regions 119 is greater than 500 μm. Only two of the third doped regions 118 and one of the fourth doped regions 119 are shown in fig. 3.
The third doped region 118 may be formed in one process with the source 125, drain 126 in the logic device region 120 and the P-type doped region 124 in the polysilicon gate 123, so that the depth and doping concentration of the third doped region 118 may be referenced to the source 125 and drain 126. In some embodiments, the third doped region 118 has a depth of 0.1 μm to 0.4 μm and a doping concentration of 5e18cm -3 ～5e20cm -3 . The fourth doped region 119 may be formed in the same process as the N-type doped region 127 in the logic device region 120, so that the depth and doping concentration of the fourth doped region 119 may be referenced to the N-type doped region 127. In some embodiments, the depth of the fourth doped region 119 is 0.1 μm to 0.4 μm, and the doping concentration is 5e18cm -3 ～5e20cm -3 。
When forming the first doped region 113, the source 125, the drain 126, and the P-type doped region 124 in the polysilicon gate 123, a first ohmic doped layer 116 may also be formed on the surface of the first doped region 113 at the same time. The second ohmic doped layer 117 may be formed at the same time as the fourth doped region 119 and the N-type doped region 127 in the logic device region 120.
Referring to fig. 5, a SAB layer (Salicide Block) is formed on the sidewall and surface of the polysilicon layer 115, a portion of the surface of the third doped region 118, and a portion of the surface of the fourth doped region 119. An ohmic alloy layer SA is then formed in the surfaces of the first and second ohmic doped layers 116 and 117, the third doped region 118 between the SAB layers, the fourth doped region 119 between the SAB layers, the source electrode 125, the drain electrode 126, and the polysilicon gate electrode 123. The first ohmic doped layer 116 and the ohmic alloy layer SA thereon form a first ohmic contact layer, the second ohmic doped layer 117 and the ohmic alloy layer SA thereon form a second ohmic contact layer, and the first ohmic contact layer and the second ohmic contact layer are isolated by an isolation structure (STI in the embodiment of the present application). The lengths of the first ohmic contact layer and the second ohmic contact layer (the lengths in the extending directions of the first doping region 113 and the second doping region 114) are not less than 30 μm, and the sum of the lengths of all the first ohmic contact layer and all the second ohmic contact layer is not less than 300 μm in order to reduce on-resistance after triggering electrostatic protection. After the distance between the third doped region 118 and the fourth doped region 119 and the doping concentration are determined, the on-resistance per unit length is fixed, and by increasing the total length of the first ohmic contact layer and all the second ohmic contact layers, the on-resistance is lower and the electrostatic discharge capability is stronger, which is equivalent to more parallel resistances. When the total length of the first ohmic contact layer and all the second ohmic contact layers is increased, it may be achieved by increasing the lengths of a single first ohmic contact layer and second ohmic contact layer or the number of first ohmic contact layers and second ohmic contact layers.
The ohmic alloy layers SA in the third and fourth doped regions 118 and 119 function as a third and fourth ohmic contact layer, respectively. The lengths of the third ohmic contact layer and the fourth ohmic contact layer (the lengths in the extending directions of the third doped region 118 and the fourth doped region 119) are not less than 20 μm, and the sum of the lengths of all the third ohmic contact layer and all the fourth ohmic contact layer is not less than 500 μm.
Referring to fig. 6, a second end of the first diode is electrically connected with a first end of the second diode; the first end of the first diode is electrically connected to a common high voltage end Pad (HV Pad) of an embedded d-TOF chip or SiPM chip, and the second end of the second diode is electrically connected to a ground end Pad (GND Pad) of the embedded d-TOF chip or SiPM chip. Specifically, the first end of the first diode is a first doped region 113, the second end is a second doped region 114, that is, the first doped region 113 is electrically connected to the common high voltage terminal pad, and the second doped region 114 is electrically connected to the first end of the second diode. In some embodiments, the first doped region 113 is electrically connected to the common high-voltage terminal pad through a metal interconnection structure, fig. 6 only shows the first interlayer metal layer M1 and the top interlayer metal layer TM of the metal interconnection structure, and the number of interlayer metal layers omitted in the middle may be determined according to practical situations. The second doped region 114 is electrically connected to the first terminal of the second diode through the first interlayer metal layer M1. When electrically connected, the first ohmic contact layer and the second ohmic contact layer play a role in reducing internal resistance. The third doped region 118 serves as a second end of the second diode, and is electrically connected to the second doped region 114 through the first interlayer metal layer M1, and specifically, the third doped region 118 may be led out through the third ohmic contact layer. Similarly, the second end (the fourth doped region 119) of the second diode may be led out through the fourth ohmic contact layer and electrically connected to the ground terminal pad through the metal interconnection structure. The metal interconnect structure is formed in dielectric layer 130. Because the metal interconnect structure in the electrostatic protection region 110 may be formed in the same process as the metal interconnect structure of the embedded d-TOF chip or other device of the SiPM chip, the embodiment of the present application does not introduce additional process steps in forming the metal interconnect structure.
The above description is given by taking the first doped region 113 as a P-type doping and the second doped region 114 as an N-type doping as an example, and the electrostatic protection structure and the forming method thereof will be described below when the first doped region 113 is an N-type doping and the second doped region 114 is a P-type doping.
Referring to fig. 7, a semiconductor substrate 200 is provided, and the description of the semiconductor substrate 200 may refer to the foregoing description of the semiconductor substrate 100. The semiconductor substrate 200 includes an electrostatic protection region 210 and a logic device region 220. A first isolation structure 211 is formed in the semiconductor substrate 200 of the electrostatic protection region 210 and the logic device region 220. Then, a first diode is formed in the semiconductor substrate 200 of the electrostatic protection region 210. The first diode is formed by a method different from the method described above, and the method includes: forming an N-type buried layer 213 in the semiconductor substrate 200 of the electrostatic protection region 210; forming the first doped region 214 (N-type) in the semiconductor substrate 100 of the electrostatic protection region 110, wherein the N-type buried layer 213 is connected to the bottom of the adjacent first doped region 214; forming the second doping region 215 (P-type) in the semiconductor substrate 200 of the electrostatic protection region 210; an N-well 222 is formed in the semiconductor substrate 200 of the logic device region 220, wherein the first doped region 214 and the second doped region 215 constitute the first diode.
Referring to fig. 8, the second isolation structure 212 and the polysilicon layer 215 are sequentially formed, and the forming method may refer to the foregoing. Next, a third doped region 218 (N-type) and a fourth doped region 219 (P-type) are formed in the polysilicon layer 215, and the polysilicon gate 223, the source 225 (P-type), the drain 226 (P-type), the P-type doped region 224 and the N-type doped region 227 are formed in the logic device region 220, wherein the third doped region 218 and the N-type doped region 227 are formed in the same process, and the fourth doped region 219 (P-type), the source 225 (P-type), the drain 226 (P-type) and the P-type doped region 224 are formed in the same process.
Next, the SAB layer, the ohmic alloy layer SA and the metal interconnection structure may be formed by the above-mentioned method, and will not be described herein.
Referring to fig. 6, the embodiment of the present application further provides an electrostatic protection structure formed by the above forming method, where the electrostatic protection structure is integrated on an embedded d-TOF chip or SiPM chip, and includes: a semiconductor substrate 100, wherein the semiconductor substrate 100 comprises a first diode with a first on voltage, and a first end of the first diode is electrically connected with a common high voltage end bonding Pad HV Pad of the embedded d-TOF chip or the SiPM chip; a polysilicon layer 115 on a portion of the semiconductor substrate 100 and isolated from the semiconductor substrate 100 by an isolation structure in the semiconductor substrate 100, the polysilicon layer 115 including a second diode having a second turn-on voltage, a first end of the second diode being in series with a second end of the first diode, the second end of the second diode being electrically connected to a ground Pad GND Pad of the embedded d-TOF chip or SiPM chip; the electrostatic protection structure guides the voltage which is larger than or equal to the sum of the first conducting voltage and the second conducting voltage on the common high-voltage end welding Pad HV Pad into the grounding end welding Pad GND Pad.
According to the electrostatic protection structure provided by the embodiment of the application, the second diode is connected in series on the basis of the first diode, so that the Trigger voltage of the high-voltage electrostatic protection device is increased, and further, the first diode and the second diode are designed into a multi-finger structure, so that a sufficiently large opening passage is realized, and the requirement of an embedded d-TOF chip or SiPM chip on electrostatic protection is completely met.
Referring to fig. 9, the present application also provides an embedded d-TOF chip comprising: a Common voltage terminal PAD (Common HV PAD) and a ground terminal PAD (GND PAD); d-TOF device connected with the common voltage terminal welding pad and the grounding terminal welding pad; the above electrostatic discharge Protection structure (ESD Protection) connects the common voltage terminal pad and the ground terminal pad. In some embodiments, the d-TOF device comprises: at least one Single Photon Avalanche Diode (SPAD) connected to the common high voltage side pad; a time-to-digital converter TDC connected to the single photon avalanche diode; reset Circuit (Reset Circuit) connecting the single photon avalanche diode and the operating voltage V DD The method comprises the steps of carrying out a first treatment on the surface of the A quenching Circuit (Quench Circuit) connects the single photon avalanche diode and the ground pad.
When the single photon avalanche diode is of the P type, the working voltage V DD Greater than 0, theVoltage V on common high voltage terminal pad POWER Less than 0; when the single photon avalanche diode is of N type, the working voltage V DD Less than 0, the voltage V on the common high voltage terminal welding pad POWER Greater than 0.
Referring to fig. 10, an SiPM chip of an embodiment of the application includes: a Common voltage terminal PAD (Common HV PAD) and a ground terminal PAD (GND PAD); an SiPM device connected with the common voltage terminal welding pad and the grounding terminal welding pad; the above electrostatic discharge Protection structure (ESD Protection) connects the common voltage terminal pad and the ground terminal pad. Only one active pixel in a multi-channel pre-scan radar is shown in fig. 10, where each active pixel includes at least one unit consisting of a single photon avalanche diode SPAD and a polysilicon Quench Resistor (Quench Resistor) in series, each unit being connected in parallel, with one end connected to the common high voltage terminal pad and the other end connected to the ground terminal pad.
The embedded d-TOF chip and the SiPM chip of the embodiment of the application can be suitable for workplaces with higher requirements on working voltage due to the electrostatic protection structure of the embodiment of the application.
In view of the foregoing, it will be evident to those skilled in the art after reading this disclosure that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present description describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (18)

1. An electrostatic protection structure integrated on an embedded d-TOF chip or SiPM chip, comprising:
a semiconductor substrate, wherein the semiconductor substrate comprises a first diode with a first conducting voltage, and a first end of the first diode is electrically connected with a common high-voltage end welding pad of the embedded d-TOF chip or the SiPM chip;
a polysilicon layer on a portion of the semiconductor substrate and isolated from the semiconductor substrate by an isolation structure in the semiconductor substrate, the polysilicon layer including a second diode having a second turn-on voltage, a first end of the second diode being in series with a second end of the first diode, the second end of the second diode being electrically connected to a ground pad of the embedded d-TOF chip or SiPM chip;
the electrostatic protection structure guides the voltage which is larger than or equal to the sum of the first conducting voltage and the second conducting voltage on the common high-voltage end welding pad into the grounding end welding pad.
2. The electrostatic protection structure according to claim 1, wherein the first diode comprises:
at least one first doped region electrically connected with the common high-voltage terminal bonding pad through a metal interconnection structure;
at least one second doped region having a doping type different from that of the first doped region, and electrically connected to the first end of the second diode through the first interlayer metal layer of the metal interconnection structure.
3. The electrostatic protection structure according to claim 2, wherein the first doped regions and the second doped regions are alternately arranged to form a multi-fingered first diode.
4. The electrostatic protection structure of claim 2, wherein the first doped region is P-type doped and the second doped region is N-type doped.
5. The electrostatic protection structure according to claim 2, wherein the first doped region is N-doped and the second doped region is P-doped; the first diode further comprises an N-type buried layer, and the N-type buried layer is connected with the bottom of the adjacent first doped region.
6. The electrostatic protection structure according to claim 2, wherein a distance between the first doped region and the second doped region is 0.3 μm to 2 μm, and a width of the first doped region is not less than 0.6 μm.
7. The electrostatic protection structure according to claim 2, further comprising a first ohmic contact layer between the first doped region and the metal interconnect structure, and a second ohmic contact layer between the second doped region and the first interlayer metal layer, wherein the first ohmic contact layer and the second ohmic contact layer are isolated by an isolation structure.
8. The structure according to claim 7, wherein a length of the first ohmic contact layer and the second ohmic contact layer is not less than 30 μm, and a sum of lengths of all the first ohmic contact layer and all the second ohmic contact layer is not less than 300 μm.
9. The electrostatic protection structure according to claim 2, wherein the second diode comprises:
at least one third doped region having a doping type different from that of the second doped region and electrically connected to the second doped region through the first interlayer metal layer;
at least one fourth doped region, which is different from the doping type of the third doped region, is electrically connected to the ground terminal pad through the metal interconnection structure.
10. The electrostatic protection structure of claim 9, wherein the third doped region and the fourth doped region are alternately arranged to form a multi-fingered second diode.
11. The electrostatic protection structure according to claim 9, wherein a distance between the third doped region and the fourth doped region is greater than 0 and not more than 1 μιη.
12. The electrostatic protection structure of claim 9, wherein the third doped region further comprises a third ohmic contact layer, the fourth doped region further comprises a fourth ohmic contact layer, and the polysilicon layer, the third doped region, and the fourth doped region between the third ohmic contact layer and the fourth ohmic contact layer further comprise an SAB layer.
13. The structure according to claim 12, wherein a length of the third ohmic contact layer and the fourth ohmic contact layer is not less than 20 μm, and a sum of lengths of all the third ohmic contact layer and all the fourth ohmic contact layer is not less than 500 μm.
14. A method of forming an electrostatic protection structure according to any one of claims 1 to 13, comprising:
providing a semiconductor substrate;
forming a first diode in the semiconductor substrate;
forming a polysilicon layer on a part of the semiconductor substrate, wherein the polysilicon layer is isolated from the semiconductor substrate by an isolation structure positioned in the semiconductor substrate;
forming a second diode in the polysilicon layer;
electrically connecting a second end of the first diode with a first end of the second diode;
and electrically connecting the first end of the first diode with a common high-voltage end welding pad of the embedded d-TOF chip or the SiPM chip, and electrically connecting the second end of the second diode with a grounding end welding pad of the embedded d-TOF chip or the SiPM chip.
15. An embedded d-TOF chip, comprising:
a common voltage terminal pad and a ground terminal pad;
d-TOF device connected with the common voltage terminal welding pad and the grounding terminal welding pad;
the electrostatic protection structure of any one of claims 1 to 13, connecting the common voltage terminal pad and the ground terminal pad.
16. The embedded d-TOF chip of claim 15, wherein the d-TOF device comprises:
at least one single photon avalanche diode connected to the common high voltage terminal pad;
a time-to-digital converter connected to the single photon avalanche diode;
a reset circuit connecting the single photon avalanche diode and an operating voltage;
and the quenching circuit is connected with the single photon avalanche diode and the grounding terminal welding pad.
17. An SiPM chip, comprising:
a common voltage terminal pad and a ground terminal pad;
an SiPM device connected with the common voltage terminal welding pad and the grounding terminal welding pad;
the electrostatic protection structure of any one of claims 1 to 13, connecting the common voltage terminal pad and the ground terminal pad.
18. The SiPM chip of claim 17, wherein the SiPM device comprises a plurality of active pixels, each active pixel comprising at least one cell comprised of a single photon avalanche diode and a polysilicon quench resistor in series, each cell being connected in parallel with one end connected to the common high voltage terminal pad and the other end connected to the ground terminal pad.
CN202210158088.4A 2022-02-21 2022-02-21 Electrostatic protection structure, forming method thereof, embedded d-TOF chip and SiPM chip Pending CN116666375A (en)

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