CN111276445A - 半导体装置以及制造半导体装置的方法 - Google Patents
半导体装置以及制造半导体装置的方法 Download PDFInfo
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Abstract
半导体装置以及制造半导体装置的方法。在一个实例中,一种半导体封装包括:具有顶部表面和底部表面的衬底、安装在所述衬底的所述顶部表面上且联接到所述衬底的所述底部表面上的一个或多个互连件的电子装置、在所述电子装置上方的封盖、围绕所述封盖的外围的壳体,以及在所述封盖和所述壳体与所述衬底之间的囊封物。
Description
技术领域
本发明大体上涉及电子装置,且更明确地说涉及半导体装置和制造半导体装置的方法。
背景技术
先前的半导体封装和形成半导体封装的方法是不适当的,例如,导致成本过量、可靠性降低、性能相对低或封装大小过大。通过比较此类方法与本发明并参考图式,所属领域的技术人员将显而易见常规和传统方法的其它限制和缺点。
发明内容
在第一实例中,一种半导体封装,其包括:衬底,其具有顶部表面和底部表面;电子装置,其在所述衬底的所述顶部表面上且联接到所述衬底的所述底部表面上的一个或多个互连件;封盖,其在所述电子装置上方;壳体,其围绕所述封盖的外围;以及囊封物,其在所述封盖与所述衬底之间和所述壳体与所述衬底之间。
在第一实例中,所述封盖在所述衬底的大部分上方。
在第一实例中,所述封盖具有四个侧面且所述壳体覆盖所有四个侧面。
在第一实例中,所述封盖具有四个侧面且所述壳体几乎覆盖所有四个侧面。
在第一实例中,所述囊封物的表面与所述衬底的表面和所述壳体的一个或多个表面共面。
第一实例进一步包括在所述封盖与所述电子装置之间的粘着材料。
第一实例进一步包括在所述封盖与所述电子装置之间的热界面材料。
在第一实例中,所述封盖包括大体上平坦的热辐射部件。
在第一实例中,所述封盖包括导热金属。
在第一实例中,所述封盖的顶部表面与所述壳体的顶部表面共面,其中所述封盖的所述顶部表面是暴露的。
在第一实例中,所述壳体在所述封盖上方,其中所述封盖并不是暴露的。
在第二实例中,一种形成半导体封装的方法,所述方法包括:将两个或更多个半导体裸片安置在衬底的顶部表面上;在所述衬底的所述顶部表面上的所述半导体裸片之间形成囊封物;将封盖阵列附接在所述两个或更多个半导体裸片上方,其中所述封盖阵列中的封盖在所述半导体裸片中的一个上方,其中所述封盖阵列包含围绕所述封盖阵列中的每一个的外围的壳体;将两个或更多个互连件附接到所述衬底的底部表面以经由所述衬底将所述半导体裸片电联接到所述互连件,以形成所述两个或更多个半导体裸片的子组合件;以及将所述子组合件单切成个别半导体封装,其中封盖在半导体裸片和所述衬底的大部分上方,且所述囊封物的一个或多个表面与所述衬底的一个或多个表面和所述壳体的一个或多个表面共面。
在第二实例中,将所述封盖阵列所述附接在所述两个或更多个半导体裸片上方包含在所述封盖阵列与所述对应半导体裸片之间施加热界面材料。
在第二实例中,所述单切包括穿过所述壳体在所述封盖阵列中的所述封盖之间进行锯割。
在第二实例中,所述形成是在将所述封盖阵列附接到所述两个或更多个半导体裸片上方之前执行。
在第二实例中,所述形成是在将所述封盖阵列附接到所述两个或更多个半导体裸片上方之后执行。
在第三实例中,一种形成半导体封装的方法,所述方法包括:将封盖阵列附接到具有两个或更多个半导体裸片的衬底条上,其中所述封盖阵列中的封盖在所述衬底条的半导体裸片上方,且其中所述封盖阵列包含围绕所述封盖中的每一个的外围的壳体;在所述两个或更多个半导体裸片之间形成囊封物;以及将所述衬底条单切成两个或更多个半导体封装,其中半导体封装的封盖在所述半导体封装的半导体裸片和所述衬底的大部分上方,且其中所述囊封物的一个或多个表面与所述衬底的一个或多个表面和所述壳体的一个或多个表面共面。
在第三实例中,所述单切包括穿过所述壳体在所述封盖阵列中的所述封盖之间进行锯割。
第三实例进一步包括通过将壳体材料倒入所述两个或更多个封盖之间的区中,并固化所述壳体材料以将所述壳体形成为块状物阵列来形成所述封盖阵列。
第三实例进一步包括通过将树脂片材安置于所述两个或更多个封盖上,并施加压力且将所述树脂片材固化到所述两个或更多个封盖之间的区中以形成所述壳体来形成所述封盖阵列。
附图说明
图1示出实例半导体装置的横截面图。
图2A到2L示出制造实例半导体装置的实例方法的横截面图。
图3A到3D示出制造半导体装置的另一实例方法的横截面图。
图4示出半导体装置的另一实例的横截面图。
图5A到5L示出制造半导体装置的另一实例方法的横截面图。
图6A到6D示出制造半导体装置的另一实例方法的横截面图。
具体实施方式
以下论述提供半导体装置和制造半导体装置的方法的各种实例。此类实例是非限制性的,且所附权利要求书的范围不应限于公开的特定实例。在下文论述中,术语“实例”和“例如”是非限制性的。
诸图说明一般构造方式,且可能省略熟知特征和技术的描述和细节以免不必要地混淆本发明。另外,图式中的元件未必按比例绘制。例如,诸图中的一些元件的尺寸可能相对于其它元件放大,以有助于改进对本发明中论述的实例的理解。不同诸图中的相同附图标记表示相同元件。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。
术语“和/或”包含由“和/或”连接的列表中的任何单个物品或任何物品组合。如本发明中所使用,除非上下文另外明确指示,否则单数形式也意图包含复数形式。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。
术语“包括”和/或“包含”为“开放”术语,且指定所陈述特征的存在,但并不排除一个或多个其它特征的存在或添加。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。
术语“第一”、“第二”等可以在本文中用于描述各种元件,且这些元件不应受这些术语限制。这些术语仅用以将一个元件与另一元件区分开来。因此,例如,在不脱离本发明的教示的情况下,可以将本发明中论述的第一元件称为第二元件。应注意,本发明和/或所要求的主题的范围在此方面不受限制。
除非另外指定,否则术语“联接”可以用于描述彼此直接接触的两个元件或描述由一个或多个其它元件间接连接的两个元件。例如,如果元件A联接到元件B,则元件A可以直接接触元件B或由插入元件C间接连接到元件B。类似地,术语“在……上方”或“在……上”可以用于描述彼此直接接触的两个元件或描述由一个或多个其它元件间接连接的两个元件。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。
术语“顶部”和“底部”大体上指装置、特征或结构的相对侧或表面,其对应于如图式中的一个或多个中示出的装置、特征或结构的定向。一般来说,顶侧或表面可指第一侧表面和底侧或表面,且底侧或表面可指定位成与第一表面相对的第二侧或表面。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。
术语“共面”可指位于同一平面或大体上至少部分位于同一平面的两个物体、物体的侧面、物体的表面和/或其它特征。在几何术语中,若存在含有所有点的几何平面,则所述点集共面。一般来说,当两个物体或结构中的每一个的表面、末端、侧面或特征至少部分处于单个平面中时,两个物体或结构可以被称为“共面”。此外,术语“平坦”可指在可接受容限内平坦或几乎平坦的表面。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。
术语“相当大”可指大于或等于一半的部分,和/或可进一步指例如百分之六十或更大、百分之七十或更大、百分之八十或更大或百分之九十或更大的其它部分。在一些实施例中,相当大也可以指100%或更大,例如如果第一结构比第二结构的大小和/或体积大,则通过第一结构比第二结构覆盖较多区域和/或体积,和/或其中第一结构至少部分地超出第二结构的边缘或边界的实质,第一结构可以在第二结构上方且可以被视为覆盖第二结构的相当大部分。此外,在一些实施例中,相当大也可以指小于50%的部分,例如在所述部分具有充分质量和/或数量的情况下。在又其它实施例中,相当大可指所有或几乎所有。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。
本发明描述尤其包含例如倒装式芯片尺度封装(fcCSP)的半导体封装的实例,以及形成倒装式芯片尺度封装的实例方法。在第一实例中,一种半导体封装包括:具有顶部表面和底部表面的衬底、安装在衬底的顶部表面上且联接到衬底的底部表面上的一个或多个互连件的电子装置、电子装置上方的封盖,以及围绕封盖的外围的壳体。囊封物可以在封盖与衬底之间和/或壳体与衬底之间。
在第二实例中,一种形成半导体封装的方法包括:将两个或更多个半导体裸片安置在衬底的顶部表面上;在衬底的顶部表面上的半导体裸片之间形成囊封物;将封盖阵列附接在两个或更多个半导体裸片上方,其中封盖阵列中的一封盖可以在半导体裸片中的一个上方,其中封盖阵列包含围绕封盖中的每一个的外围的壳体;以及将两个或更多个互连件附接到衬底的底部表面以将半导体裸片经由衬底电联接到互连件,以形成两个或更多个半导体裸片的子组合件。可以通过切削裸片之间的囊封物的据割操作将两个或更多个半导体裸片的子组合件单切成个别半导体封装,其中个别半导体封装中的每一个包括在半导体裸片和衬底的相当大部分上方的封盖,且囊封物的一个或多个表面可以与衬底的一个或多个表面和壳体的一个或多个表面共面。
在第三实例中,一种形成半导体封装的方法包括:将两个或更多个半导体裸片联接到衬底条;将块状物阵列安置在两个或更多个半导体裸片上方,其中块状物阵列中的一封盖在半导体裸片中的一个上方;以及在两个或更多个半导体裸片中的第一半导体裸片与第二半导体裸片之间形成囊封物。可以将衬底条单切成两个或更多个半导体封装,其中一个封盖可以在半导体裸片和衬底的相当大部分上方,且其中囊封物的一个或多个表面与衬底的一个或多个表面和壳体的一个或多个表面共面。
其它实例包含于本发明中。在诸图、权利要求书和/或本发明的描述中可以找到此类实例。
图1示出实例半导体装置100的横截面图。在图1中示出的实例中,半导体装置100可以包括衬底110、电子装置120、囊封物130、封盖140、壳体150和互连件160。
衬底110可以包括具有一个或多个导电层的导电结构111和具有一个或多个介电层的介电结构112。电子装置120可以包括互连件121。
衬底110、囊封物130、封盖140、壳体150和互连件160可以被称为半导体封装190,且封装190可以为电子装置120提供保护以免受外部元件和/或环境暴露影响。另外,半导体封装190可以在外部电组件(未示出)与互连件160之间提供电联接。如图1中所示,除了下文的各种其它诸图之外,在一个或多个实施例中,封盖140在衬底110的相当大部分上方。术语“相当大”可指大于或等于一半的部分,和/或可进一步指例如百分之六十或更大、百分之七十或更大、百分之八十或更大或百分之九十或更大的其它部分。在一些实施例中,相当大也可以指100%或更大,例如如果第一结构比第二结构的大小和/或体积大,则通过第一结构比第二结构覆盖较多区域和/或体积,和/或其中第一结构至少部分地超出第二结构的边缘或边界的实质,第一结构可以在第二结构上方且可以被视为覆盖第二结构的相当大部分。此外,在一些实施例中,相当大也可以指小于50%的部分,例如在所述部分具有充分质量和/或数量的情况下。在又其它实施例中,相当大可指所有或几乎所有。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。
图2A到2L示出制造半导体装置100的实例方法的横截面图。图2A示出在早期制造阶段的半导体装置100的横截面图。
在图2A中示出的实例中,衬底110可以包括导电结构111的一个或多个导电层和导电结构112的一个或多个介电层。衬底110可以包括例如印刷电路板(例如,具有芯的预建层压电路结构)或引线框架。在其它实例中,衬底110可以包括高密度扇出结构(HDFO)或堆积式重布结构,例如SLIM(无硅集成模块)或SWIFT(硅晶片集成式扇出技术)结构。在一些实例中,衬底110可以包括介电结构112的介电层,以用于将导电结构111的邻近导电层彼此电隔离。衬底110可以形成为具有顺序地和/或反复地形成导电结构111和介电结构112的相应层的堆积式结构。
导电结构111可以通过衬底110的顶部和底部表面暴露于外部。电子装置120可以电连接到暴露于衬底110的顶部表面的导电结构111的导电层,且互连件160可以电连接到暴露于衬底110的底部表面的导电结构111的导电层。
在一些实例中,导电结构111可以被称为或可以包括金属层、金属布线层或电路图案。导电结构111可以包括例如金(Au)、银(Ag)、铜(Cu)、铝(Al)或钯(Pd)的导电材料。形成导电层111的实例包含使用电镀过程或物理气相沉积(PVD)过程。导电结构111的一个或多个层的厚度的范围可以是约10微米到约20微米。导电层111可以在电子装置120与互连件160之间提供导电路径。
在一些实例中,介电结构112可以被称为绝缘体或钝化层。介电结构112可以包括例如氧化物、氮化物、聚酰亚胺、苯并环丁烯、聚苯并恶唑、双马来酰亚胺三嗪(BT)、酚系树脂或环氧树脂的电绝缘材料。形成介电层112的实例可以包括热氧化、化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、低压化学气相沉积(LPCVD)、等离子体增强式化学气相沉积(PECVD)、片材层压或蒸发。介电结构112的厚度的范围可以是约25微米到约100微米。在一些实例中,介电结构112可以保护导电结构111免受环境暴露影响,且介电结构112可以在衬底110中的导电元件之间提供电隔离。
图2B示出在稍后制造阶段的半导体装置100的横截面图。在图2B中示出的实例中,可以将电子装置120附接到衬底110的顶部部分。在一些实例中,电子装置120可以包括半导体裸片。在一些实例中,半导体裸片120可以包括例如硅(Si)的半导体材料。半导体裸片120可以包括被动电子电路元件(未示出)或例如晶体管的主动电子电路元件(未示出)。半导体裸片120可以包括互连件121。在一些实例中,互连件121可以被称为导电凸块、例如焊球的导电球、例如铜桩的导电桩或例如铜柱的导电柱。互连件121的厚度的范围可以是约40微米到约100微米。
另外,尽管图2B中仅示出一个半导体裸片120,但此并非本发明的限制。在其它实例中,多于一个半导体裸片120可以附接到衬底110的顶部部分。在一些实例中,半导体裸片120可以包括电路,例如数字信号处理器(DSP)、微处理器、网络处理器、功率管理处理器、音频处理器、射频(RF)电路、无线基带芯片上系统(SoC)处理器、传感器或专用集成电路。通过将导电凸块121电连接到衬底110的顶部表面处暴露的导电结构111,半导体裸片120可以附接到衬底110的顶部部分。在一些实例中,半导体裸片120可以通过大规模回焊过程、热压过程或激光接合过程电连接到导电结构111。
图2C示出在稍后制造阶段的半导体装置100的横截面图。在图2C中示出的实例中,可以使用粘着材料21将阵列20和对应封盖140附接到半导体裸片120的顶部部分。粘着材料21可以因此充当封盖140与半导体裸片120的顶部之间的界面,且如在本发明实例中所见,粘着材料也可以覆盖半导体裸片120的侧壁的至少一部分。在一些实例中,粘着材料21可以包括热界面材料(TIM)。TIM 21可以形成于半导体裸片120与阵列20之间。TIM 21可以包含高导热性填料(例如,氮化铝(AlN)、氮化硼(BN)、氧化铝(Al2O3)、碳化硅(SiC)等)、粘合剂或粘着剂(例如,聚合树脂)和/或添加剂。TIM21可以具有在大约5w/m·k到大约100w/m·k的范围内的导热性。可以通过多种方法形成或施加TIM 21,包含喷射、浸渍、注入或丝印涂布。TIM 21的厚度的范围可以是约30微米到约50微米。在一些实例中,TIM 21可以将从半导体裸片120生成的热转移到阵列20。在如图2C中所示的一些实施例和各种其它诸图中,TIM 21可以延伸到半导体裸片120的一个或多个末端,且在其它实施例中,其可以延伸超出和/或延伸到半导体裸片120的一个或多个末端、边缘或拐角上方,且本发明和/或权利要求书的范围在此方面不受限制。在一些实例中,阵列20可以包括封盖140和壳体150。在一些实例中,封盖140可以被称为热辐射部件。在一些实施例中,封盖140可以包括大体上平坦的热辐射部件。应注意,术语“平坦”可指在可接受容限内平坦或几乎平坦的表面。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。
在一些实例中,壳体150可以被称为树脂部分。在如下文将进一步详细论述的一个或多个实施例中,壳体150可以围绕封盖140的外围安置。在一些实施例中,封盖140可以具有四个侧面,且壳体150可以以连续的方式覆盖封盖140的所有四个侧面,或可以以连续或不连续的方式几乎覆盖封盖140的所有四个侧面,例如其中壳体150可以具有凹口、槽或凹槽或其它结构中的一个或多个,所述结构可以防止壳体150完全覆盖封盖140的所有四个侧面和/或封盖140的整个外围,且本发明和/或所要求的主题的范围在此方面不受限制。在描述附接阵列20之前,将首先描述阵列20的形成过程。
在图2D中所示的实例中,可以将多个封盖140布置于模具或载体10上,从而在封盖140之间留下恒定间隔的凹槽或间距。在一些实例中,可以使用粘着材料(未示出)将封盖140附接到模具或载体10。在一些实例中,封盖140可以包括具有良好导热性的导热金属,例如铜(Cu)、铝(Al)、金(Au)或银(Ag)。在一些实施例中,封盖140可以包括大体上平坦的导热金属。应注意,术语“平坦”可指在可接受容限内平坦或几乎平坦的表面。然而,应注意,本发明和/或所要求的主题的范围在此方面不受限制。封盖140的厚度的范围可以是约200微米到约400微米。接下来,在图2E中所示的实例中,可以将凝胶型树脂倒入多个封盖140中的每一个之间的区中且可以通过退火过程固化所述树脂,借此形成壳体150。在图2F中所示的其它实例中,可以将树脂片材150'定位于多个封盖140上。树脂片材150'可以呈半固化状态。接下来,在图2G中所示的实例中,可以通过压力将树脂片材150'定位于多个封盖140中的每一个之间,并通过退火过程固化所述片材,借此形成壳体150。在一些实例中,壳体150可以包括环氧树脂、酚系树脂、玻璃环氧树脂、聚合物、聚酰亚胺、聚酯、硅酮或陶瓷。壳体150的厚度的范围可以是约200微米到约400微米。因此,壳体150将封盖140彼此连接。接着,在图2H中所示的实例中,从模具或载体10分离多个封盖140和壳体150,借此完成阵列20。
阵列20,在图2I中所示的实例中为多个封盖140可以布置成彼此间隔开恒定间隔,且壳体150可以形成于多个封盖140中的每一个之间,从而使得阵列20可以配置成板材形式。由于阵列20允许跳过将相应封盖140布置在半导体裸片120上的个别步骤,因此可以改进生产率。在一些实例中,在多个半导体裸片120附接到衬底110的顶部部分的状态中,可以通过附接单个阵列20将相应封盖140附接到多个半导体裸片120,借此改进生产率。可以根据衬底110的大小和半导体裸片120的数目来附接多个阵列20。在一些实施例中,一个或多个封盖140可以具有四个侧面,且壳体150可以以连续的方式覆盖封盖140的所有四个侧面,或可以以连续或不连续的方式几乎覆盖封盖140的所有四个侧面,例如其中壳体150可以具有凹口、槽或凹槽或其它结构中的一个或多个,所述结构可以防止壳体150完全覆盖封盖140的所有四个侧面和/或封盖140的整个外围,且本发明和/或所要求的主题的范围在此方面不受限制。
返回到图2C,可以将阵列20中的封盖140的某一部分联接到半导体裸片120的顶部表面。在一些实例中,封盖140的区域可以大于半导体裸片120的区域且小于衬底110的区域。在一些实例中,封盖140可以形成为覆盖半导体裸片120,且衬底110的一部分可以暴露于封盖140的外部。因此,不必要在阵列20的整个底部表面上形成粘着材料21。实际上,粘着材料21可以仅形成于封盖140的对应于半导体裸片120的一部分上,借此节约与粘着材料21的形成相关联的成本。另外,由于封盖140具有比半导体裸片120大的区域,因此从半导体裸片120生成的热可以快速辐射到外部。在一些实例中,壳体150可以形成为环绕封盖140的侧表面。因此,封盖140的顶部表面可以暴露于外部,并将从半导体裸片120生成的热快速辐射到外部。
现在移动到图2J,示出在稍后制造阶段的半导体装置100的横截面图。在图2J中示出的实例中,可以将囊封物130形成于衬底110与阵列20之间。囊封物130囊封半导体裸片120和衬底110的顶部部分。在一些实例中,囊封物130可以接触半导体裸片120的侧表面和底部表面而不接触半导体裸片120的顶部表面。在一些实例中,囊封物130可以包括各种囊封或模制材料中的任一种,例如树脂、聚合物化合物、具有填料的聚合物、环氧树脂、具有填料的环氧树脂、具有填料的环氧丙烯酸酯、硅酮材料,其组合或和其等效物。在一些实例中,囊封物130可以通过各种方法中的一种形成,例如压缩模制过程、液相囊封物模制过程、真空层压过程、膏状物印刷过程或薄膜辅助模制过程。囊封物130的厚度的范围可以是约120微米到约200微米。在一些实例中,可以将囊封物130注入衬底110与阵列20之间的区中并进行固化,借此囊封半导体裸片120。
在一些实例中,如图2K中所示出,可以将衬底110、半导体裸片120和阵列20放置在模具中,且可以通过模制入口30将囊封物130注入模具中,借此囊封半导体裸片120。在一些实例中,囊封物130可以保护半导体裸片120免受外部环境影响。可能存在如下实例:壳体150可以包括与关于囊封物130所描述的那些中的一个或多个类似的材料,和/或可以通过与所述描述类似的过程形成。
图2L示出在稍后制造阶段的半导体装置100的横截面图。在图2L中所示的实例中,衬底110、阵列20和囊封物130可以经受单切操作,以分离多个半导体裸片120中的每一个和多个封盖140中的每一个。在一些实例中,可以借助于据割工具分离衬底110、壳体150和囊封物130。在一些实例中,在单切衬底110、阵列20和囊封物130之前,可以将互连件160附接到衬底110的底部表面处暴露的导电结构111。在其它实例中,可以在据割之后将互连件160附接到衬底110的底部表面处暴露的导电结构111。例如,互连件160可以形成为球状网格阵列、焊盘网格阵列或引脚网格阵列。另外,互连件160可以包括锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。形成互连件160的实例包含使用球滴过程、网版印刷过程或电镀过程。互连件160的厚度的范围可以是约150微米到约300微米。互连件160可以充当用于在衬底110与外部电组件(未示出)之间提供电信号的电接点。
完成的半导体装置100可以包括衬底110、安装在衬底110上的半导体裸片120、囊封半导体裸片120的囊封物130、附接到半导体裸片120的顶部部分的封盖140、环绕封盖140的侧表面的壳体150,以及附接到衬底110的底部表面的互连件160。
图3A到3D示出制造半导体装置100的另一实例方法的横截面图。在图3A中所示的实例中,可以将电子装置120附接到衬底110的顶部部分。在一些实例中,电子装置120可以包括半导体裸片。在一些实例中,半导体裸片120可以包括例如硅(Si)的半导体材料。半导体裸片120可以包括被动电子电路元件(未示出)或例如晶体管的主动电子电路元件(未示出)。半导体裸片120可以包括互连件121。在一些实例中,互连件121可以被称为导电凸块、例如焊球的导电球、例如铜桩的导电桩或例如铜柱的导电柱。
另外,尽管图3A中仅示出一个半导体裸片120,但此并非本发明的限制。在其它实例中,多于一个半导体裸片120可以附接到衬底110的顶部部分。通过将导电凸块121电连接到衬底110的顶部表面处暴露的导电结构111,半导体裸片120可以附接到衬底110的顶部部分。在一些实例中,半导体裸片120可以通过大规模回焊过程、热压过程或激光接合过程电连接到导电结构111。
图3B示出在稍后制造阶段的半导体装置100的横截面图。在图3B中所示的实例中,可以将囊封物130形成于半导体裸片120的侧表面处。囊封物130囊封半导体裸片120和衬底110的顶部部分。另外,囊封物130可以将半导体裸片120的顶部表面暴露于外部。在一些实例中,囊封物130可以接触半导体裸片120的侧表面和底部表面而不接触半导体裸片120的顶部表面。在一些实例中,囊封物130可以包括各种囊封或模制材料中的任一种,例如树脂、聚合物化合物、具有填料的聚合物、环氧树脂、具有填料的环氧树脂、具有填料的环氧丙烯酸酯、硅树脂,其组合或和其等效物。在一些实例中,囊封物130可以通过各种方法中的一种形成,例如压缩模制过程、液相囊封物模制过程、真空层压过程、膏状物印刷过程或薄膜辅助模制过程。
图3C示出在稍后制造阶段的半导体装置100的横截面图。在图3C中所示的实例中,可以使用粘着材料21、22将阵列20和对应封盖140附接到半导体裸片120的顶部部分和囊封物130。粘着材料21、22因此可以充当封盖140与半导体裸片120的顶部之间的界面。在一些实例中,粘着材料21、22可以包括热界面材料(TIM)21和粘着剂22。无论是TIM 21还是粘着剂22,粘着材料在一些实例中也可以延伸成覆盖半导体裸片120的侧壁的至少一部分。TIM21可以形成于半导体裸片120与阵列20之间。TIM 21可以包含高导热性填料(例如,氮化铝(AlN)、氮化硼(BN)、氧化铝(Al2O3)、碳化硅(SiC)等)、粘合剂或粘着剂(例如,聚合树脂)和/或添加剂。TIM 21可以具有在大约5w/m·k到大约100w/m·k的范围内的导热性。可以通过多种方法形成或施加TIM 21,包含喷射、浸渍、注入或丝印涂布。TIM 21的厚度的范围可以是约30微米到约50微米。在一些实例中,TIM 21可以将从半导体裸片120生成的热转移到阵列20。粘着剂22可以形成于囊封物130与阵列20之间。粘着剂22的厚度的范围可以是约30微米到约50微米。粘着剂22可以接触囊封物130和阵列20。另外,TIM 21的导热性可以大于粘着剂22的导热性。可能存在TIM 21和粘着剂22可以包括相同和/或连续材料的实例。在一些实例中,阵列20可以包括封盖140和壳体150。在一些实例中,封盖140可以被称为热辐射部件。在一些实例中,壳体150可以被称为树脂部分。图2D到2I中示出形成阵列20的过程。
在图3C中所示的实例中,可以将阵列20中的封盖140的某一部分联接到半导体裸片120的顶部表面。在一些实例中,封盖140的区域可以大于半导体裸片120的区域且小于衬底110的区域。另外,由于封盖140具有比半导体裸片120大的区域,因此从半导体裸片120生成的热可以快速辐射到外部。在一些实例中,壳体150可以形成为环绕封盖140的侧表面。因此,封盖140的顶部表面可以暴露于外部,并将从半导体裸片120生成的热快速辐射到外部。
图3D示出在稍后制造阶段的半导体装置100的横截面图。在图3D中所示的实例中,衬底110、阵列20和囊封物130可以经受锯割操作,以分离多个半导体裸片120中的每一个和多个封盖140中的每一个。在一些实例中,可以借助于据割工具分离衬底110、壳体150和囊封物130。在一些实例中,在锯割衬底110、阵列20和囊封物130之前,可以将互连件160附接到衬底110的底部表面处暴露的导电结构111。在其它实例中,可以在据割之后将互连件160附接到衬底110的底部表面处暴露的导电结构111。例如,互连件160可以形成为球状网格阵列、焊盘网格阵列或引脚网格阵列。另外,互连件160可以包括锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。形成互连件160的实例包含使用球滴过程、网版印刷过程或电镀过程。
完成的半导体装置100可以包括衬底110、安装在衬底110上的半导体裸片120、囊封半导体裸片120的囊封物130、附接到半导体裸片120的顶部部分的封盖140、环绕封盖140的侧表面的壳体150,以及附接到衬底110的底部表面的互连件160。
图4示出半导体装置200的另一实例的横截面图。半导体装置200可以类似于半导体装置100。半导体装置200可以包括形成于封盖140的顶部表面上的壳体250。壳体250可以保护封盖140的顶部表面。
图5A到5L示出制造半导体装置200的另一实例方法的横截面图。图5A示出在早期制造阶段的半导体装置200的横截面图。
在图5A中所示的实例中,衬底110可以包括导电结构111的一个或多个导电层和介电结构112的一个或多个介电层。衬底110可以包括例如印刷电路板(例如,具有芯的预建层压电路结构)或引线框架。在其它实例中,衬底110可以包括高密度扇出结构(HDFO)或堆积式重布结构,例如SLIM(无硅集成模块)或SWIFT(硅晶片集成式扇出技术)结构。在一些实例中,衬底110可以包括介电结构112的介电层,以用于将导电结构111的邻近导电层彼此电隔离。衬底110可以形成为具有反复地或顺序地形成导电结构111和介电结构112的相应层的堆积式结构。
导电结构111可以通过衬底110的顶部和底部表面暴露于外部。电子装置120可以电连接到暴露于衬底110的顶部表面的导电结构111的导电层,且互连件160可以电连接到暴露于衬底110的底部表面的导电结构111的导电层。
在一些实例中,导电结构111可以被称为或可以包括金属层、金属布线层或电路图案。导电结构111可以包括例如金(Au)、银(Ag)、铜(Cu)、铝(Al)或钯(Pd)的导电材料。形成导电结构111的实例包含使用电镀过程或物理气相沉积(PVD)过程。导电结构111可以连接到衬底110和电子装置120。另外,导电结构111可以连接到衬底110和互连件160。
在一些实例中,介电结构112可以被称为绝缘体或钝化层。介电结构112可以包括例如氧化物、氮化物、聚酰亚胺、苯并环丁烯、聚苯并恶唑、双马来酰亚胺三嗪(BT)、酚系树脂或环氧树脂的电绝缘材料。形成介电结构112的实例可以包括热氧化、化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、低压化学气相沉积(LPCVD)、等离子体增强式化学气相沉积(PECVD)、片材层压或蒸发。在一些实例中,介电结构112可以保护导电结构111免受环境暴露影响,且介电结构112可以在衬底110中的导电元件之间提供电隔离。
图5B示出在稍后制造阶段的半导体装置200的横截面图。在图5B中所示的实例中,可以将电子装置120附接到衬底110的顶部部分。在一些实例中,电子装置120可以包括半导体裸片。在一些实例中,半导体裸片120可以包括例如硅(Si)的半导体材料。半导体裸片120可以包括被动电子电路元件(未示出)或例如晶体管的主动电子电路元件(未示出)。半导体裸片120可以包括互连件121。在一些实例中,互连件121可以被称为导电凸块、例如焊球的导电球、例如铜桩的导电桩或例如铜柱的导电柱。
另外,尽管图5B中仅示出一个半导体裸片120,但此并非本发明的限制。在其它实例中,多于一个半导体裸片120可以附接到衬底110的顶部部分。在一些实例中,半导体裸片120可以包括电路,例如数字信号处理器(DSP)、微处理器、网络处理器、功率管理处理器、音频处理器、射频(RF)电路、无线基带芯片上系统(SoC)处理器、传感器或专用集成电路。通过将导电凸块121电连接到暴露于衬底110的顶部表面的导电结构111,半导体裸片120可以附接到衬底110的顶部部分。在一些实例中,半导体裸片120可以通过大规模回焊过程、热压过程或激光接合过程电连接到导电结构111。
图5C示出在稍后制造阶段的半导体装置200的横截面图。在图5C中所示的实例中,可以使用粘着材料21将阵列20'附接到半导体裸片120的顶部部分。
在一些实例中,粘着材料21可以包括热界面材料(TIM)。TIM 21可以形成于半导体裸片120与阵列20'之间。TIM 21可以包含高导热性填料(例如,氮化铝(AlN)、氮化硼(BN)、氧化铝(Al2O3)、碳化硅(SiC)等)、粘合剂或粘着剂(例如,聚合树脂)和/或添加剂。TIM 21可以具有在大约5w/m·k到大约100w/m·k的范围内的导热性。可以通过多种方法形成或施加TIM 21,包含喷射、浸渍、注入或丝印涂布。TIM 21的厚度的范围可以是约30微米到约50微米。在一些实例中,TIM 21可以将从半导体裸片120生成的热转移到阵列20'。在一些实例中,阵列20'可以包括封盖140和壳体250。在一些实例中,封盖140可以被称为热辐射部件。在一些实例中,壳体250可以被称为树脂部分。在描述阵列20'的附接之前,将首先描述阵列20'的形成过程。
在图5D中所示的实例中,可以将多个封盖140以恒定间隔布置于载体40上。在一些实例中,可以使用粘着材料(未示出)将封盖140附接到载体40。在一些实例中,载体40可以包括金属、硅(Si)或玻璃。在一些实例中,封盖140可以包括具有良好导热性的导热金属,例如铜(Cu)、铝(Al)、金(Au)或银(Ag)。封盖140的厚度的范围可以是约200微米到约400微米。接下来,在图5E中所示的实例中,可以通过将布置有封盖140的载体40放置在模具(未示出)上,并将环氧模制化合物(EMC)注入模具中来形成壳体250。在图5F中示出的其它实例中,可以将树脂片材250'定位于多个封盖140上。树脂片材250'可以呈半固化状态。接下来,在图5G中所示的实例中,可以通过压力将树脂片材250'定位于多个封盖140中的每一个之间,并通过退火过程固化所述片材,借此形成壳体250。在一些实例中,壳体250可以包括环氧树脂、酚系树脂、玻璃环氧树脂、聚合物、聚酰亚胺、聚酯、硅或陶瓷。壳体250的厚度的范围可以是约300微米到约500微米。因此,壳体250将封盖140彼此连接。接着,在图5H中所示的实例中,可以除去载体40,借此完成包含多个封盖140和壳体250的阵列20'。由于阵列20'的封盖140的侧表面和顶部表面可以被壳体250覆盖,因此可以防止阵列20'与外部电路之间的不必要电接触。
阵列20',在图5I中所示的实例中为多个封盖140可以布置成彼此间隔开恒定间隔,且壳体250可以形成于多个封盖140中的每一个之间,从而使得阵列20'可以配置成板材形式。由于阵列20'允许跳过将相应封盖140布置在半导体裸片120上的个别步骤,因此可以改进生产率。在一些实例中,在多个半导体裸片120附接到衬底110的顶部部分的状态中,可以通过附接单个阵列20'将相应封盖140附接到多个半导体裸片120,借此改进生产率。可以根据衬底110的大小和半导体裸片120的数目来附接多个阵列20'。
在图5C中所示的实例中,可以将阵列20'中的封盖140的某一部分接触半导体裸片120的顶部表面。在一些实例中,封盖140的区域可以大于半导体裸片120的区域且小于衬底110的区域。在一些实例中,封盖140可以形成为覆盖半导体裸片120,且衬底110的一部分可以暴露于封盖140的外部。因此,不必要在阵列20'的整个底部表面上形成粘着材料21。实际上,粘着材料21可以仅形成于封盖140的对应于半导体裸片120的一部分上,借此节约与粘着材料21的形成相关联的成本。另外,由于封盖140具有比半导体裸片120大的区域,因此从半导体裸片120生成的热可以快速辐射到外部。在一些实例中,壳体250可以形成为环绕封盖140的侧表面和顶部表面。因此,壳体250可以防止阵列20'与外部电路之间的电接触。
图5J示出在稍后制造阶段的半导体装置200的横截面图。在图5J中所示的实例中,可以将囊封物130形成于衬底110与阵列20'之间。囊封物130从衬底110的顶部部分囊封半导体裸片120。在一些实例中,囊封物130可以接触半导体裸片120的侧表面和底部表面而不接触半导体裸片120的顶部表面。在一些实例中,囊封物130可以包括各种囊封或模制材料中的任一种,例如树脂、聚合物化合物、具有填料的聚合物、环氧树脂、具有填料的环氧树脂、具有填料的环氧丙烯酸酯、硅树脂,其组合或和其等效物。在一些实例中,囊封物130可以通过各种方法中的一种形成,例如压缩模制过程、液相囊封物模制过程、真空层压过程、膏状物印刷过程或薄膜辅助模制过程。在一些实例中,可以将囊封物130注入衬底110与阵列20'之间的区中并进行固化,借此囊封半导体裸片120。
例如,如图5K中所示出,可以将衬底110、半导体裸片120和阵列20'放置在模具中,且可以通过模制入口30将囊封物130注入模具中,借此囊封半导体裸片120。在一些实例中,囊封物130可以保护半导体裸片120免受外部环境影响。
图5L示出在稍后制造阶段的半导体装置200的横截面图。在图5L中所示的实例中,衬底110、阵列20'和囊封物130可以经受锯割操作,以分离多个半导体裸片120中的每一个和多个封盖140中的每一个。在一些实例中,可以借助于锯割工具分离衬底110、壳体250和囊封物130。在一些实例中,在锯割衬底110、阵列20'和囊封物130之前,可以将互连件160附接到暴露于衬底110的底部表面的导电结构111。在其它实例中,可以在锯割之后将互连件160附接到暴露于衬底110的底部表面的导电结构111。例如,互连件160可以形成为球状网格阵列、焊盘网格阵列或引脚网格阵列。另外,互连件160可以包括锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。形成互连件160的实例包含使用球滴过程、网版印刷过程或电镀过程。
完成的半导体装置200可以包括衬底110、安装在衬底110上的半导体裸片120、囊封半导体裸片120的囊封物130、附接到半导体裸片120的顶部部分的封盖140、环绕封盖140的侧表面和顶部表面的壳体250,以及附接到衬底110的底部表面的互连件160。
图6A到6D示出制造半导体装置200的另一实例方法的横截面图。在图6A中所示的实例中,可以将电子装置120附接到衬底110的顶部部分。在一些实例中,电子装置120可以包括半导体裸片。在一些实例中,半导体裸片120可以包括例如硅(Si)的半导体材料。半导体裸片120可以包括被动电子电路元件(未示出)或例如晶体管的主动电子电路元件(未示出)。半导体裸片120可以包括互连件121。在一些实例中,互连件121可以被称为导电凸块、例如焊球的导电球、例如铜桩的导电桩或例如铜柱的导电柱。
另外,尽管图6A中仅示出一个半导体裸片120,但此并非本发明的限制。在其它实例中,多于一个半导体裸片120可以附接到衬底110的顶部部分。通过将导电凸块121电连接到暴露于衬底110的顶部表面的导电结构111,半导体裸片120可以附接到衬底110的顶部部分。在一些实例中,半导体裸片120可以通过大规模回焊过程、热压过程或激光接合过程电连接到导电结构111。
图6B示出在稍后制造阶段的半导体装置200的横截面图。在图6B中所示的实例中,可以将囊封物130形成于半导体裸片120的侧表面处。囊封物130从衬底110的顶部部分囊封半导体裸片120。另外,囊封物130可以将半导体裸片120的顶部表面暴露于外部。在一些实例中,囊封物130可以接触半导体裸片120的侧表面和底部表面而不接触半导体裸片120的顶部表面。在一些实例中,囊封物130可以包括各种囊封或模制材料中的任一种,例如树脂、聚合物化合物、具有填料的聚合物、环氧树脂、具有填料的环氧树脂、具有填料的环氧丙烯酸酯、硅树脂,其组合或和其等效物。在一些实例中,囊封物130可以通过各种方法中的一种形成,例如压缩模制过程、液相囊封物模制过程、真空层压过程、膏状物印刷过程或薄膜辅助模制过程。
图6C示出在稍后制造阶段的半导体装置200的横截面图。在图6C中所示的实例中,可以使用粘着材料21、22将阵列20'附接到半导体裸片120的顶部部分和囊封物130。在一些实例中,粘着材料21、22可以包括热界面材料(TIM)和粘着剂22。TIM 21可以形成于半导体裸片120与阵列20'之间。TIM 21可以包含高导热性填料(例如,氮化铝(AlN)、氮化硼(BN)、氧化铝(Al2O3)、碳化硅(SiC)等)、粘合剂或粘着剂(例如,聚合树脂)和/或添加剂。TIM 21可以具有在大约5w/m·k到大约100w/m·k的范围内的导热性。可以通过多种方法形成或施加TIM 21,包含喷射、浸渍、注入或丝印涂布。TIM 21的厚度的范围可以是约30微米到约50微米。在一些实例中,TIM 21可以将从半导体裸片120生成的热转移到阵列20'。粘着剂22可以形成于囊封物130与阵列20之间。
粘着剂22的厚度的范围可以是约30微米到约50微米。粘着剂22可以接触囊封物130和阵列20。另外,TIM 21的导热性可以大于粘着剂22的导热性。可能存在TIM 21和粘着剂22可以包括相同和/或连续材料的实例。在一些实例中,阵列20'可以包括封盖140和壳体150。在一些实例中,封盖140可以被称为热辐射部件。在一些实例中,壳体150可以被称为树脂部分。图5D到5G中示出形成阵列20'的过程。在图6C中所示的实例中,可以将阵列20'中的封盖140的某一部分联接到半导体裸片120的顶部表面。在一些实例中,封盖140的区域可以大于半导体裸片120的区域且小于衬底110的区域。另外,由于封盖140具有比半导体裸片120大的区域,因此从半导体裸片120生成的热可以快速辐射到外部。在一些实例中,壳体250可以形成为环绕封盖140的侧表面和顶部表面。因此,壳体250可以防止阵列20'与外部电路之间的电接触。
图6D示出在稍后制造阶段的半导体装置200的横截面图。在图6D中所示的实例中,衬底110、阵列20'和囊封物130可以经受锯割操作,以分离多个半导体裸片120中的每一个和多个封盖140中的每一个。在一些实例中,可以借助于锯割工具分离衬底110、壳体250和囊封物130。在一些实例中,在锯割衬底110、阵列20'和囊封物130之前,可以将互连件160附接到暴露于衬底110的底部表面的导电结构111。在其它实例中,可以在锯割之后将互连件160附接到衬底110的底部表面处暴露的导电结构111。例如,互连件160可以形成为球状网格阵列、焊盘网格阵列或引脚网格阵列。另外,互连件160可以包括锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。形成互连件160的实例包含使用球滴过程、网版印刷过程或电镀过程。
完成的半导体装置200可以包括衬底110、安装在衬底110上的半导体裸片120、囊封半导体裸片120的囊封物130、附接到半导体裸片120的顶部部分的封盖140、环绕封盖140的侧表面和顶部表面的壳体250,以及附接到衬底110的底部表面的互连件160。
总体来说,一种例如倒装式芯片尺度封装(fcCSP)的半导体封装包括:具有顶部表面和底部表面的衬底、安装在衬底的顶部表面上且联接到衬底的底部表面上的一个或多个互连件的电子装置、在电子装置和衬底的相当大部分上方的封盖、围绕封盖的外围的壳体,以及在封盖和壳体与衬底之间的囊封物,其中囊封物与衬底和壳体的一个或多个末端共面。
形成此半导体封装的方法包含通过首先将封盖或盖阵列形成为块状物阵列将多个封盖或盖附接到封装的相应电子装置或半导体裸片,其中块状物阵列包含固持块状物阵列中的封盖或盖的壳体。接着可以在多个电子装置附接到衬底的情况下将块状物阵列附接到衬底,其中块状物阵列中的一个封盖或盖覆盖相应电子装置。可以在附接块状物阵列之前或附接块状物阵列之后将囊封物模制于电子装置与封盖或盖之间。
可以例如通过在封盖之间穿过囊封物进行锯割而从所得结构单切个别半导体封装。单切后的半导体封装可以具有如下所得结构:封盖或盖覆盖电子装置和衬底的相当大部分,且壳体围绕封盖或盖的外围覆盖衬底的剩余部分。
在一些实施例中,壳体和封盖或盖共面,其中封盖或盖的表面暴露于周围环境。在其它实施例中,壳体完全或大体覆盖封盖或盖,其中封盖或盖并不暴露于周围环境。封盖或盖可以充当热辐射装置,且可以包括导热金属以从电子装置耗散热。在一些实施例中,热界面材料可以在电子装置与封盖或盖之间。
相比就地拾取法或逐个法,形成半导体封装的上文实例方法允许以较高速率将多个封盖附接到多个电子装置,以实现每小时较高的单位制造处理量。此外,所得半导体封装使得半导体装置具有包括半导体装置的较大部分的封盖或盖,以增强来自半导体封装的电子装置的热的热耗散。以块状物阵列形成封盖允许使用标准锯割过程单切个别半导体封装,从而实现个别半导体封装的较小外观尺寸。
本发明包含对某些实例的参考。然而,所属领域的技术人员将理解,在不脱离本发明的范围的情况下可以进行各种改变且可以取代等效物。另外,在不脱离本发明的范围的情况下可以对公开的实例作出修改。因此,预期本发明不限于公开的实例,而是本发明将包含属于所附权利要求书的范围内的所有实例。
Claims (20)
1.一种半导体封装,其包括:
衬底,其具有顶部表面和底部表面;
电子装置,其在所述衬底的所述顶部表面上且联接到所述衬底的所述底部表面上的一个或多个互连件;
封盖,其在所述电子装置上方;
壳体,其围绕所述封盖的外围;以及
囊封物,其在所述封盖与所述衬底之间和所述壳体与所述衬底之间。
2.根据权利要求1所述的半导体封装,其中所述封盖在所述衬底的大部分上方。
3.根据权利要求1所述的半导体封装,其中所述封盖具有四个侧面且所述壳体覆盖所有四个侧面。
4.根据权利要求1所述的半导体封装,其中所述封盖具有四个侧面且所述壳体几乎覆盖所有四个侧面。
5.根据权利要求1所述的半导体封装,其中所述囊封物的表面与所述衬底的表面和所述壳体的一个或多个表面共面。
6.根据权利要求1所述的半导体封装,其进一步包括在所述封盖与所述电子装置之间的粘着材料。
7.根据权利要求1所述的半导体封装,其进一步包括在所述封盖与所述电子装置之间的热界面材料。
8.根据权利要求1所述的半导体封装,其中所述封盖包括大体上平坦的热辐射部件。
9.根据权利要求1所述的半导体封装,其中所述封盖包括导热金属。
10.根据权利要求1所述的半导体封装,其中所述封盖的顶部表面与所述壳体的顶部表面共面,其中所述封盖的所述顶部表面是暴露的。
11.根据权利要求1所述的半导体封装,其中所述壳体在所述封盖上方,其中所述封盖并不是暴露的。
12.一种形成半导体封装的方法,所述方法包括:
将两个或更多个半导体裸片安置在衬底的顶部表面上;
在所述衬底的所述顶部表面上的所述半导体裸片之间形成囊封物;
将封盖阵列附接在所述两个或更多个半导体裸片上方,其中所述封盖阵列中的封盖在所述半导体裸片中的一个上方,其中所述封盖阵列包含围绕所述封盖阵列中的每一个的外围的壳体;
将两个或更多个互连件附接到所述衬底的底部表面以经由所述衬底将所述半导体裸片电联接到所述互连件,以形成所述两个或更多个半导体裸片的子组合件;以及
将所述子组合件单切成个别半导体封装,其中封盖在半导体裸片和所述衬底的大部分上方,且所述囊封物的一个或多个表面与所述衬底的一个或多个表面和所述壳体的一个或多个表面共面。
13.根据权利要求12所述的方法,其中将所述封盖阵列所述附接在所述两个或更多个半导体裸片上方包含在所述封盖阵列与所述对应半导体裸片之间施加热界面材料。
14.根据权利要求12所述的方法,其中所述单切包括穿过所述壳体在所述封盖阵列中的所述封盖之间进行锯割。
15.根据权利要求12所述的方法,其中所述形成是在将所述封盖阵列附接到所述两个或更多个半导体裸片上方之前执行。
16.根据权利要求12所述的方法,其中所述形成是在将所述封盖阵列附接到所述两个或更多个半导体裸片上方之后执行。
17.一种形成半导体封装的方法,所述方法包括:
将封盖阵列附接到具有两个或更多个半导体裸片的衬底条上,其中所述封盖阵列中的封盖在所述衬底条的半导体裸片上方,且其中所述封盖阵列包含围绕所述封盖中的每一个的外围的壳体;
在所述两个或更多个半导体裸片之间形成囊封物;以及
将所述衬底条单切成两个或更多个半导体封装,其中半导体封装的封盖在所述半导体封装的半导体裸片和所述衬底的大部分上方,且其中所述囊封物的一个或多个表面与所述衬底的一个或多个表面和所述壳体的一个或多个表面共面。
18.根据权利要求17所述的方法,其中所述单切包括穿过所述壳体在所述封盖阵列中的所述封盖之间进行锯割。
19.根据权利要求17所述的方法,其进一步包括通过将壳体材料倒入所述两个或更多个封盖之间的区中,并固化所述壳体材料以将所述壳体形成为块状物阵列来形成所述封盖阵列。
20.根据权利要求17所述的方法,其进一步包括通过将树脂片材安置于所述两个或更多个封盖上,并施加压力且将所述树脂片材固化到所述两个或更多个封盖之间的区中以形成所述壳体来形成所述封盖阵列。
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US20210407877A1 (en) * | 2020-06-25 | 2021-12-30 | Intel Corporation | Integrated circuit die packages including a contiguous heat spreader |
US11710675B2 (en) * | 2021-02-17 | 2023-07-25 | Advanced Semiconductor Engineering, Inc. | Package structure and method for manufacturing the same |
US20220319954A1 (en) * | 2021-03-31 | 2022-10-06 | Texas Instruments Incorporated | Package heat dissipation |
TWI822634B (zh) * | 2022-07-20 | 2023-11-11 | 強茂股份有限公司 | 晶圓級晶片尺寸封裝方法 |
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US8564114B1 (en) * | 2010-03-23 | 2013-10-22 | Amkor Technology, Inc. | Semiconductor package thermal tape window frame for heat sink attachment |
US8779582B2 (en) * | 2010-10-20 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Compliant heat spreader for flip chip packaging having thermally-conductive element with different metal material areas |
US9159643B2 (en) * | 2012-09-14 | 2015-10-13 | Freescale Semiconductor, Inc. | Matrix lid heatspreader for flip chip package |
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