CN111276406A - Fan-out type wafer level packaging structure and manufacturing method thereof - Google Patents

Fan-out type wafer level packaging structure and manufacturing method thereof Download PDF

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Publication number
CN111276406A
CN111276406A CN201811479175.XA CN201811479175A CN111276406A CN 111276406 A CN111276406 A CN 111276406A CN 201811479175 A CN201811479175 A CN 201811479175A CN 111276406 A CN111276406 A CN 111276406A
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layer
fan
cured
cured layer
wafer level
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范增焰
吕开敏
全昌镐
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN201811479175.XA priority Critical patent/CN111276406A/en
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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    • H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
    • H01L2224/17107—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area the bump connectors connecting two common bonding areas
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    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/8085—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/80855—Hardening the adhesive by curing, i.e. thermosetting
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A fan-out wafer level package structure and a manufacturing method thereof are provided, the method comprises: providing a supporting wafer layer, and forming an adhesive layer on the supporting wafer layer; adhering a plurality of bare chips to the surface of the adhesive layer, wherein the bare chips are provided with pins, and the pins face to the surface of the adhesive layer; forming a pre-cured layer on the adhesive layer and one side of the bare chip far away from the wafer supporting layer, wherein the pre-cured layer covers the bare chip; forming a cured layer on one side of the pre-cured layer away from the wafer supporting layer; removing the supporting wafer layer and the adhesive layer to expose the pins of the bare chip; forming a rewiring layer on the surface of one side of the pin exposed out of the bare chip, and forming a spherical pin on the rewiring layer; polishing the solidified layer to a predetermined thickness; cutting to form a fan-out wafer level packaging structure; the solidified layer and the pre-solidified layer have different thermal expansion coefficients, and the solidified layer and the die have the same thermal expansion coefficient. The packaging structure produced by the method reduces the warping of the wafer in the fan-out type wafer level packaging process.

Description

Fan-out type wafer level packaging structure and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor chip packaging, in particular to a fan-out type wafer level packaging structure and a manufacturing method thereof.
Background
In the development of a Dynamic Random Access Memory (DRAM) manufacturing process, in the related art, a Window Ball Grid Array (WBGA) is used to package a DRAM package structure 100 (as shown in fig. 1A), which includes a die 101, a molding layer 102 and a pin 103. The design of the bond pad locations on die 101 for openings 110 is critical and needs to be matched to the manufacturing capabilities of the substrate fab. In addition, the DRAM package structure adopting the WBGA method needs to transmit signals through the substrate, and the thickness of the DRAM package structure and the metal wiring lines in the substrate have strict requirements.
The fan-out wafer level package structure in the related art (as shown in fig. 1B) includes a die 101', a molding layer 102', and ball leads 103 '. Because the difference between the thermal expansion coefficients of the plastic packaging layer and the bare chip is large, the whole structure is easy to warp after the plastic packaging layer is formed, and the difficulty of the technology for forming the rewiring layer and the ball-shaped pin is increased.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
In view of the above problems, the present invention provides a fan-out type wafer level package structure and a method for manufacturing the same, so as to solve the bottleneck of substrate design and the warpage problem of the fan-out type wafer level package structure to a certain extent.
The invention provides a manufacturing method of a fan-out wafer level packaging structure, which comprises the following steps: providing a supporting wafer layer, and forming an adhesive layer on the supporting wafer layer; adhering a plurality of bare chips to the surface of the adhesive layer, wherein the bare chips are provided with pins, and the pins face to the surface of the adhesive layer; forming a pre-cured layer on the adhesive layer and one side of the bare chip far away from the wafer supporting layer, wherein the pre-cured layer covers the bare chip; forming a cured layer on one side of the pre-cured layer away from the wafer supporting layer; removing the supporting wafer layer and the adhesive layer to expose the pins of the bare chip; forming a rewiring layer on the surface of one side of the pin exposed out of the bare chip, and forming a spherical pin on the rewiring layer; polishing the solidified layer to a predetermined thickness; cutting to form a fan-out wafer level packaging structure; the solidified layer and the pre-solidified layer have different thermal expansion coefficients, and the solidified layer and the die have the same thermal expansion coefficient.
In some embodiments of the present invention, the step of forming the pre-cured layer comprises: pasting the pre-cured layer on the adhesive layer and the side of the bare chip far away from the supporting wafer layer at 100-120 ℃, wherein the pasting time is 1 min; after the coating, precuring for 0.5-1.5 h at 100-120 ℃.
In some embodiments of the present invention, the temperature of the curing layer formed on the side of the pre-curing layer away from the supporting wafer layer is between 150 ℃ and 200 ℃ for 1 to 3 hours.
In some embodiments of the present invention, the thickness of the pre-cured layer is 200 to 250 μm, and the predetermined thickness of the cured layer is 200 to 400 μm.
In some embodiments of the invention, the pre-cured layer is an epoxy molding compound and the cured layer is a silicon wafer.
By applying the manufacturing method, the invention also provides a fan-out type wafer level packaging structure, which comprises the following steps: the semiconductor device comprises a bare chip, a pre-cured layer, a rewiring layer, a plurality of ball pins and a cured layer. The bare chip is provided with a pin; the pre-curing layer covers and coats the bare chip, and one side of the pin of the bare chip is exposed out of the surface of the pre-curing layer; the rewiring layer is formed on one exposed side of the pins of the bare chip and comprises a passivation layer and a metal layer; a plurality of ball pins are formed on the redistribution layer, and the ball pins are electrically connected with the pins of the bare chip through the metal layer; the solidified layer is formed on one side, far away from the heavy wiring layer, of the pre-solidified layer and covers the pre-solidified layer; wherein the cured layer and the pre-cured layer have different thermal expansion coefficients, and the cured layer and the die have the same thermal expansion coefficient.
In some embodiments of the invention, the pre-cured layer is an epoxy molding compound and the cured layer is a silicon wafer.
In some embodiments of the present invention, the thickness of the pre-cured layer is 200 to 250 μm.
In some embodiments of the present invention, the cured layer has a thickness of 200 to 400 μm.
In some embodiments of the invention, the die is a dynamic random access memory.
The packaging method has the advantages that the fan-out wafer level packaging technology is utilized to carry out rewiring, the ball mounting process is carried out on the rewiring opening, the processes of substrate design, surface mounting, wiring and the like in the traditional packaging are replaced, the transmission performance of the packaging structure can be improved, the size of the packaging structure is reduced, and the bottleneck of substrate design in the traditional WBGA packaging mode is avoided. In addition, the method of the invention reduces the warpage of the wafer in the fan-out wafer level packaging process, particularly in the process of forming the heavy wiring layer and the solder ball pins, reduces the subsequent process difficulty, reduces the warpage of the cut packaging structure and is beneficial to the subsequent repackaging process by additionally applying the curing layer on the pre-curing layer.
Drawings
Fig. 1A is a schematic diagram of a conventional WBGA-type DRAM package structure.
Fig. 1B is a schematic diagram of a conventional fan-out wafer level package structure in the prior art.
Fig. 1C is a schematic diagram illustrating a conventional fan-out wafer level package structure in the prior art in which warpage occurs.
Fig. 2A-2I are schematic views of the fan-out wafer level package structure according to the present invention in various steps of the manufacturing method.
FIG. 3 is a fan-out wafer level package structure manufactured by applying the manufacturing method of the fan-out wafer level package structure of the present invention.
Fig. 4 is a flowchart illustrating a method for manufacturing a fan-out wafer level package structure according to an embodiment of the present invention.
Detailed Description
The following description is provided by way of specific examples to describe embodiments of the fan-out wafer level package structure and the fan-out wafer level package structure, and those skilled in the art can understand the advantages and effects of the present invention from the disclosure of the present specification. The invention is capable of other and different embodiments and its several details are capable of modification and various other changes, which can be made in various details within the specification and without departing from the spirit and scope of the invention. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.
The invention provides a manufacturing method of a fan-out wafer level packaging structure. See fig. 2A-2I and fig. 4. Fig. 2A-2I are schematic views of the fan-out wafer level package structure according to the present invention in various steps of the manufacturing method. The manufacturing method is carried out on an element 200 to be processed. The method comprises the following specific steps:
step S101, providing a supporting wafer layer, and forming an adhesive layer on the supporting wafer layer.
As shown in fig. 2A, a supporting wafer layer 207 is provided, and an adhesive is applied on one side surface of the supporting wafer layer 207 to form an adhesive layer 208. The adhesive layer 208 is intended to completely cover the surface of the support wafer layer 207. Then, alignment marks are made, and a plurality of alignment marks are arranged at the same preset distance according to the specification of the bare chip. The supporting wafer layer 207 may be selected to be a transparent glass or silicon wafer, the supporting wafer layer 207 has a cut mark thereon, and the adhesive layer 208 may be a silicone gel, and those skilled in the art can select a suitable material according to actual needs.
Step 102, adhering a plurality of bare chips to the surface of the adhesive layer.
As shown in fig. 2B, a plurality of single dies 201 cut in advance are adhered to the surface of the adhesive layer 208, and the dies 201 are adhered to the designated positions according to the previous alignment marks to form a predetermined arrangement. The bare chip is provided with a pin, and the pin faces to the surface of the adhesive layer. The distance between the dies 201 is 80-120 μm, for example, the distance between the dies 201 is 90 μm, 100 μm or 110 μm. The present disclosure does not specifically limit this.
Step S103, forming a pre-cured layer on the adhesive layer and the side of the bare chip far away from the supporting wafer layer.
As shown in fig. 2C, an Epoxy Molding Compound (EMC) layer is bonded to the surface of the supporting wafer layer by an adhesive layer to form a pre-cured layer 202. A pre-cured layer 202 covers the previously bonded individual dies 201. Specifically, the pre-curing step S103 is performed in a vacuum chamber, and first, an EMC layer is attached to the surface of the supporting wafer layer 207 through the adhesive layer 208, covering and encapsulating the plurality of previously bonded single dies 201. The EMC layer is pasted at the temperature of 100-120 ℃ within 1 min. And then, pre-curing for 0.5-1.5 h under the condition of keeping the temperature of 100-120 ℃, thus completing the pre-curing of the epoxy plastic packaging material. In one embodiment of the present disclosure, the EMC layer is applied at 110 ℃ and then pre-cured for 1h at 110 ℃. The pre-cured epoxy molding compound is in the form of a solid colloid. The thickness of the pre-cured layer may be 200 to 250 μm, for example, the thickness of the pre-cured layer may be 210 μm, 220 μm, 230 μm, or 240 μm. Those skilled in the art can select a suitable thickness according to actual needs, and the disclosure is not limited thereto. The pre-curing process can be considered to be completed by observing from bottom to top, i.e. from the supporting wafer layer 207 to the pre-cured layer 202, that no air bubbles exist between the die 201 and the EMC forming the pre-cured layer and covering the die 201.
And S104, forming a cured layer on one side of the pre-cured layer away from the supporting wafer layer.
As shown in fig. 2D, the cured layer 204 is formed on a side of the pre-cured layer 202 away from the supporting wafer layer 207, the cured layer 204 completely covers the pre-cured layer 202, and then curing is performed. In some preferred embodiments, a silicon wafer is selected as the solidified layer 202. One skilled in the art can also select other materials as the cured layer according to actual needs. The curing step S104 is performed in the vacuum chamber, and the cured layer 204 is attached to the surface of the pre-cured layer 202 to completely cover the pre-cured layer 202, and is maintained at 150 to 200 ℃ for about 1 to 3 hours, thereby completing the curing. For example, curing is carried out for 2h at 180 ℃. The cured layer may have a thickness of 750 to 850 μm, for example 800 μm. The skilled person can select a suitable thickness according to the actual need. Since some of the volatile matter that is not completely volatilized is also present in the EMC in the pre-curing step, adhesion can be formed when a cured layer such as a silicon wafer is attached. And after the volatile matter is completely volatilized, completely curing and forming. The solidified layer is formed on the surface of the pre-solidified layer, and the thermal expansion coefficients of the solidified layer and the bare chip are the same, so that the warping of the whole wafer is reduced, and the process difficulty of forming the re-wiring layer and the ball-shaped pins subsequently is reduced.
Step S105, removing the supporting wafer layer and the adhesive layer. As shown in fig. 2E, the wafer supporting layer 207 and the adhesive layer 208 are removed, so that the pins 2011 of the die 201 arranged in the pre-cured layer 202 are exposed. Then, the exposed die 201 is cleaned to ensure that no adhesive layer remains on the surface of the pins 2011 of the die 201.
And S106, forming a rewiring layer on the surface of one side of the pin exposed out of the bare chip.
As shown in fig. 2F, a first passivation layer is deposited on the surface of the pre-cured layer 202 on the side where the die pins 2011 are exposed, a groove is formed by photolithography, development and etching, the groove exposes the die pins 2011, a metal layer is formed by depositing a metal in the groove, and a second passivation layer is deposited on the surface of the metal layer and the surface of the first passivation layer, so as to form the redistribution layer 205. The rewiring layer includes a first passivation layer, a second passivation layer, and a metal layer. The method of depositing the first passivation layer and the second passivation layer may be chemical vapor deposition or atomic layer deposition. The material of the passivation layer may be polyimide (polyimide). The method of depositing the metal layer may be physical vapor deposition or electroplating. The material of the metal layer may be one of copper, aluminum, tungsten, and the like, or an alloy material of the above materials. The present disclosure is not so limited.
In one embodiment of the present disclosure, the first passivation layer and the second passivation layer have a thickness of 5 to 10 μm, for example, 6 μm, 7 μm, 8 μm, or 9 μm. The thicknesses of the first passivation layer and the second passivation layer may be the same or different. The thickness of the metal layer is 3 to 5 μm, for example, 4 μm. The present disclosure is not so limited.
Step S107, forming a ball-shaped pin on the redistribution layer.
As shown in fig. 2G, solder balls are soldered to the surface of the redistribution layer 205 to connect with the exposed die pad 2011, forming the ball pad 203. In an embodiment of the present disclosure, the ball-mounting method may be selected from methods using a ball-mounter, a stencil, brushing solder paste, or manual mounting according to actual needs.
And S108, grinding the solidified layer to a preset thickness.
As shown in fig. 2H, a side of the cured layer away from the ball-shaped pins is polished by mechanical polishing, so that the cured layer 204 is polished to a predetermined thickness to meet the package specification. The thickness of the cured layer after polishing is 200-400 μm, for example, the thickness of the cured layer may be 250 μm, 300 μm or 350 μm, and those skilled in the art can select a suitable thickness according to actual needs. The present disclosure is not so limited.
S109, cutting to form the fan-out wafer level packaging structure.
As shown in fig. 2I, the ground element 200 to be machined is measured, marked, and then cut according to the mark, as indicated by the arrow in fig. 2I. The component 200 to be processed is cut into a fan-out wafer level package structure 300 including a single die as shown in fig. 3 by means of laser or diamond cutting. The skilled person can also select other cutting methods according to the actual needs. The fan-out wafer level package structure 300 includes a single die 301, a pre-cured layer 302, die pins 303, a cured layer 304, and a redistribution layer 305.
In some embodiments, the manufacturing method is used to manufacture a package structure of a dynamic random access memory, i.e., die 201/301 is a dynamic random access memory.
In the above-mentioned flow, in order to perform the subsequent steps and ensure the electrical performance of the fan-out wafer level package structure, the surface of the die after removing the adhesive layer and the supporting die layer needs to be cleaned after the supporting step S105. A cleaning step is usually performed after the support removing step S105 and before the passivation wiring step S106. And removing residues of the adhesive layer and the supporting wafer layer on the surface of the pre-cured layer by using a cleaning agent, so that the exposed part of the bare chip is kept clean to ensure the electrical property. For example, the washing method may be water washing, and the detergent is selected to be water.
The manufacturing method of the fan-out wafer level packaging structure utilizes the fan-out wafer level packaging technology to replace the processes of substrate design, surface mounting and the like in the traditional packaging, can improve the transmission performance of the fan-out wafer level packaging structure, reduces the size of the fan-out wafer level packaging structure, and avoids the bottleneck of substrate design in the traditional WBGA packaging mode. In addition, the method of the invention reduces the warpage of the wafer in the fan-out wafer level packaging process, particularly in the process of forming the heavy wiring layer and the solder ball pins, reduces the subsequent process difficulty, and simultaneously reduces the warpage of the fan-out wafer level packaging structure after cutting, thereby being beneficial to the subsequent repackaging process.
By applying the manufacturing method of the invention, the invention also provides a fan-out type wafer level packaging structure, which is shown in fig. 3. As shown in fig. 3, the fan-out wafer level package structure 300 includes: a die 301, a pre-cured layer 302, a redistribution layer 305, ball leads 303, and a cured layer 304. The rewiring layer 305 includes a passivation layer and a metal layer. The pre-cured layer 302 is typically an epoxy molding compound, the pre-cured layer 302 covers and encapsulates the die 301, and the pin side of the die 301 exposes the surface of the pre-cured layer 302. The redistribution layer 305 is formed on the pre-cured layer 302 on the exposed side of the pins of the die 301, and is connected to the pins of the die 301. A plurality of ball pins 303 are formed on the redistribution layer 305. The solidified layer 304 is formed on a side of the pre-solidified layer away from the redistribution layer, and completely covers the pre-solidified layer 302. The cured layer 304 has a different coefficient of thermal expansion than the pre-cured layer 302, and the cured layer 304 has the same coefficient of thermal expansion as the die 301.
The main difference between the fan-out wafer level package structure and the conventional WBGA package structure is that a cured layer with a thermal expansion coefficient different from that of the EMC and the same as that of the die is applied on the EMC layer (pre-cured layer in the present disclosure). The EMC layer is pre-cured, and secondary curing is performed after the curing layer is attached. The packaging process is also different from the conventional fan-out wafer level packaging process due to the dual layer curing. First die 201/301 is arranged by bonding to a surface of support wafer layer 207 to which adhesive layer 208 is applied. EMC is then applied to the surface of the supporting wafer layer 207 through the adhesive layer 208, covering and encapsulating the previously bonded plurality of individual dies 201/301, and pre-curing is completed under the set temperature and pressure conditions for a period of time. The pre-cured EMC is in the form of a solid gel. After the pre-curing is completed, the cured layer 204 is attached to the surface of the pre-cured layer 202, completely covering the pre-cured layer 202, and the curing is completed under the set temperature and pressure conditions for a period of time. And after curing, removing the supporting wafer layer and the adhesive layer, and then carrying out the subsequent steps of laying a rewiring layer, ball planting, polishing, cutting and the like.
In some preferred embodiments, a silicon wafer is selected as the solidified layer 304. One skilled in the art can also select other materials as the cured layer according to actual needs. The thickness of the cured layer 304 is preferably 200 to 400 μm. The thickness of the pre-cured layer 302 is preferably 200 to 250 μm. Those skilled in the art can select the corresponding thickness according to the actual requirement to meet the packaging standard.
In some embodiments, the fan-out wafer level package structure is a dynamic random access memory package structure, i.e., the die 301 is a dynamic random access memory.
The fan-out wafer level packaging structure has the advantages that the manufacturing processes of substrate design, surface mounting and the like in the traditional packaging are replaced, the transmission performance of the packaging structure can be improved, the size of the packaging structure is reduced, and the bottleneck of substrate design in the traditional WBGA packaging mode is avoided. In addition, the packaging structure of the invention reduces the warpage of the wafer in the fan-out wafer level packaging process, particularly in the process of forming a heavy wiring layer and solder ball pins, reduces the subsequent process difficulty, reduces the warpage of the cut packaging structure and is beneficial to the subsequent repackaging process by additionally applying the curing layer on the pre-curing layer.
The above embodiments of the fan-out wafer level package structure and the method for manufacturing the same according to the present invention are not limited to the above embodiments, and it is believed that those skilled in the art can understand the technical solution and the operation principle of the invention. However, the above is only a preferred embodiment of the present invention and does not limit the present invention. The technical solution provided by the present invention can be modified appropriately according to the actual needs by those skilled in the art, and modifications and equivalent changes can be made without departing from the scope of the present invention as claimed. The scope of the invention is to be determined by the following claims.

Claims (10)

1. A manufacturing method of a fan-out wafer level packaging structure is characterized by comprising the following steps:
providing a supporting wafer layer, and forming an adhesive layer on the supporting wafer layer;
bonding a plurality of dies to the adhesive layer surface, the dies having pins facing the adhesive layer surface;
forming a pre-cured layer on the adhesive layer and a side of the die away from the wafer support layer, the pre-cured layer covering the die;
forming a cured layer on one side of the pre-cured layer away from the wafer supporting layer;
removing the supporting wafer layer and the adhesive layer to expose the pins of the bare chip;
forming a rewiring layer on one side surface of the pin exposed out of the bare chip, and forming a spherical pin on the rewiring layer;
grinding the solidified layer to a predetermined thickness;
cutting to form the fan-out wafer level packaging structure;
wherein the cured layer and the pre-cured layer have different coefficients of thermal expansion and the cured layer and the die have the same coefficient of thermal expansion.
2. The method of manufacturing the fan-out wafer level package structure of claim 1, wherein the step of forming the pre-cured layer comprises:
applying the pre-cured layer to the adhesive layer and the side of the bare chip far away from the supporting wafer layer at 100-120 ℃, wherein the applying time is 1 min;
after the coating, precuring for 0.5-1.5 h at 100-120 ℃.
3. The method as claimed in claim 1, wherein the temperature of the curing layer formed on the side of the pre-curing layer away from the supporting die layer is 150-200 ℃ for 1-3 h.
4. The method as claimed in claim 1, wherein the thickness of the pre-cured layer is 200-250 μm, and the predetermined thickness of the cured layer is 200-400 μm.
5. The method of manufacturing the fan-out wafer level package structure of claim 1, wherein the pre-cured layer is an epoxy molding compound and the cured layer is a silicon wafer.
6. A fan-out wafer level package structure, comprising:
a die having a pin;
the pre-curing layer covers and coats the bare chip, and one side of the pins of the bare chip is exposed out of the surface of the pre-curing layer;
the rewiring layer is formed on one exposed side of the pins of the bare chip and comprises a passivation layer and a metal layer;
a plurality of ball pins formed on the redistribution layer, the ball pins electrically connected with the pins of the die through the metal layer; and
the solidified layer is formed on one side, far away from the heavy wiring layer, of the pre-solidified layer and covers the pre-solidified layer;
the cured layer and the pre-cured layer have different coefficients of thermal expansion, and the cured layer and the die have the same coefficient of thermal expansion.
7. The fan-out wafer level package structure of claim 6, wherein the pre-cured layer is an epoxy molding compound and the cured layer is a silicon wafer.
8. The fan-out wafer level package structure of claim 6, wherein the thickness of the pre-cured layer is 200-250 μm.
9. The fan-out wafer level package structure of claim 6, wherein the cured layer has a thickness of 200-400 μm.
10. The fan-out wafer level package structure of claim 6, in which the die is a dynamic random access memory.
CN201811479175.XA 2018-12-05 2018-12-05 Fan-out type wafer level packaging structure and manufacturing method thereof Pending CN111276406A (en)

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US20140138857A1 (en) * 2012-11-16 2014-05-22 Shin-Etsu Chemical Co., Ltd. Encapsulant equipped with supporting substrate, encapsulated substrate having semiconductor devices mounting thereon, encapsulated wafer having semiconductor devices forming thereon, semiconductor apparatus, and method for manufacturing semiconductor apparatus
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Publication number Priority date Publication date Assignee Title
CN102057484A (en) * 2008-06-12 2011-05-11 住友电木株式会社 Semiconductor device mounting substrate
US20140138857A1 (en) * 2012-11-16 2014-05-22 Shin-Etsu Chemical Co., Ltd. Encapsulant equipped with supporting substrate, encapsulated substrate having semiconductor devices mounting thereon, encapsulated wafer having semiconductor devices forming thereon, semiconductor apparatus, and method for manufacturing semiconductor apparatus
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