CN111273159B - Output detection circuit suitable for surge suppression chip - Google Patents

Output detection circuit suitable for surge suppression chip Download PDF

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CN111273159B
CN111273159B CN202010129478.XA CN202010129478A CN111273159B CN 111273159 B CN111273159 B CN 111273159B CN 202010129478 A CN202010129478 A CN 202010129478A CN 111273159 B CN111273159 B CN 111273159B
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CN111273159A (en
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奚冬杰
徐晴昊
李现坤
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CETC 58 Research Institute
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

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  • Emergency Protection Circuit Devices (AREA)

Abstract

The invention discloses an output detection circuit suitable for a surge suppression chip, and belongs to the technical field of electronics. The output detection circuit suitable for the surge suppression chip comprises resistors R1-R9, R12-R16, triodes Q1-Q9, Q14-Q18, a capacitor C1, a diode D1 and a latch comparator; the voltage V of the input end VIN can be realized by utilizing the voltage difference applied between the emitter and the base of the triode under the condition of not needing a thick gate oxide deviceINAnd an output terminal OUT voltage VOUTDetecting the state, namely judging whether the working state of the circuit is normal or not, and simultaneously introducing a latch comparator structure to improve the detection speed; adding hysteresis effect to the detection result, and filtering V generated by load jumpOUTAnd the instantaneous drop is large, thereby avoiding the malfunction of the subsequent control logic.

Description

Output detection circuit suitable for surge suppression chip
Technical Field
The invention belongs to the technical field of electronics, relates to an analog integrated circuit, and particularly relates to an output detection circuit suitable for a surge suppression chip.
Background
With the rapid development of the semiconductor integrated circuit technology level, the surge suppression phenomenon needs to be considered in the implementation process of various electronic devices. Especially considering the implementation characteristics of the switching power supply chip architecture, the output filter capacitor is an indispensable element for the input end of the switching power supply chip architecture. The switching power supply presents capacitive impedance characteristics to the upper-level input, so that the surge current phenomenon exists at the starting moment of the switching power supply, and the current value generated at the moment is far larger than the rated working current limiting value. The generation of the instantaneous surge current is started, so that enough margin and response time need to be reserved when the type selection power supply protection device is used, otherwise, the device of the power supply input part can be aged in advance due to the excessive surge current and even damaged immediately. The surge voltage which exists along with the excessive surge current also causes the aging and the failure of the input end device of the switching power supply, so that the high-voltage surge voltage-resisting characteristic of more than 50ms/80V is required to be provided for the direct current equipment power supply according to the environmental adaptability regulation in various military direct current power supply use occasions. The surge suppression chip has the characteristics of simple structure, high response speed, low loss and the like, and the working voltage range of the surge suppression chip can fluctuate from several volts to hundreds of volts according to different application conditions. In order to control the working state of the chip, the surge suppression chip needs to be added with an output detection function for judging whether the output state of the chip is normal or not.
The circuit architecture of the conventional surge suppression chip is shown in fig. 1, and the resistor voltage dividing networks R1 and R2 are used for detecting the OUT voltage V at the output endOUTSize. When the circuit is working normally VOUTWhen the voltage is less than the set value threshold, the comparator A0 outputs low level, the MOS tube M2 is closed, the voltage of the grid end of the MOS tube M1 is raised by a Charge Pump, and the signal of the output end OUT is equal to the signal of the input end VIN. When the input end VIN signal is too high due to surge voltage, VOUTAbove the set threshold, the comparator A0 outputs high level, the MOS transistor M2 is turned on, and the gate terminal of the MOS transistor M1 is pulled to VOUTMOS transistor M1 is turned off, VOUTClamped to the level shown in this equation:
Figure BDA0002395408290000011
VREFis a reference voltage.
From the above analysis, it can be known that the surge suppression chip needs to satisfy the condition V when working normallyOUT＝VINAnd V isOUTAnd VINThe fluctuation is large over the entire range. If the conventional comparator mode is adopted to detect VOUTAnd VINThe requirement of the voltage difference on the gate oxide withstand voltage of the device is too high (0-V)INUp to several hundred volts) and no process can meet the design requirements, so how to detect the normal working condition becomes the design difficulty of the surge suppression chip.
Disclosure of Invention
The invention aims to provide an output detection circuit suitable for a surge suppression chip, which aims to solve the problem that the conventional surge suppression chip is limited by the gate oxide withstand voltage of a device and is difficult to detect the normal output state.
In order to solve the technical problem, the invention provides an output detection circuit suitable for a surge suppression chip, which comprises resistors R1-R9, R12-R16, triodes Q1-Q9, Q14-Q18, a capacitor C1, a diode D1 and a latching comparator;
the first end of the resistor R1 is connected with the input end VIN, and the second end is short-circuited with the emitter of the triode Q1; the first end of the resistor R2 is connected with the emitter of the triode Q2, and the second end is connected with the collector of the triode Q3; the first end of the resistor R3 is connected with the emitter of the triode Q3, and the second end is connected with GND;
the first end of the resistor R4 is connected with the collector of the triode Q4, and the second end is connected with the emitter of the triode Q5; the first end of the resistor R5 is connected with the collector of the triode Q5, and the second end is connected with the first end of the resistor R6; the first end of the resistor R6 is connected with the base electrode of the triode Q6, and the second end is connected with the collector electrode of the triode Q6;
the first end of the resistor R7 is connected with the output end OUT, and the second end is connected with the emitter of the triode Q7; the first end of the resistor R8 is connected with the collector of the triode Q7, and the second end is connected with the collector of the triode Q8;
the first end of the resistor R12 is connected with the emitter of the triode Q14, and the second end is connected with GND; the first end of the resistor R13 is connected with the collector of the triode Q14, and the second end is connected with the base of the triode Q16; the first end of the resistor R14 is connected with the first end of the capacitor C1, and the second end is connected with GND; the first end of the resistor R15 is connected with the collector of the triode Q4, and the second end is connected with the collector of the triode Q17; the resistor R16 has a first terminal connected to the base of the transistor Q18 and a second terminal connected to GND.
Optionally, the latching comparator comprises triodes Q10-Q13 and resistors R10 and R11;
the first end of the resistor R10 is connected with the base electrode of the triode Q11, and the second end is connected with the collector electrode of the triode Q13;
the first end of the resistor R11 is connected with the collector of the triode Q11, and the second end is connected with the base of the triode Q13;
the collector of the triode Q11 is connected with the collector of the triode Q10, and the collector of the triode Q13 is connected with the collector of the triode Q12;
the emitter of the triode Q11 and the emitter of the triode Q13 are both connected with GND.
Optionally, the collector of the triode Q1 is connected with the collector of the triode Q2, the base of the triode Q1 is connected with the collector thereof, and the base of the triode Q2 is connected with the collector thereof;
the base of the triode Q4 is connected with the first end of the resistor R4, and the emitter is connected with the output end OUT; the base of the triode Q5 is connected with the first end of the resistor R5; the base electrode of the triode Q6 is connected between the resistor R5 and the resistor R6, and the emitter electrode of the triode Q6 is connected with GND; the base electrode of the triode Q8 is connected with the second end of the resistor R8, and the emitter electrode is connected with GND; the collector of the triode Q9 is connected with the collector of the triode Q11, the base of the triode Q11 is connected with the base of the triode Q8, and the emitter of the triode Q9 is connected with GND; the base of the triode Q7 is connected with the first end of a resistor R2;
the base of the triode Q10 is connected with the base of the triode Q5, and the emitter of the triode Q10 is connected with the second end of the resistor R4; the base of the triode Q12 is connected with the base of the triode Q5, and the emitter of the triode Q12 is connected with the second end of the resistor R4;
the collector of the triode Q15 is connected with the collector of the triode Q16, the base of the triode Q16 is connected with the base of the triode Q5, and the emitter of the triode Q15 is connected with the second end of the resistor R4; an emitter of the triode Q16 is connected with GND; the base of the triode Q17 is connected with the collector of the triode Q16, and the emitter of the triode Q17 is connected with the first end of the resistor R16; the collector of the transistor Q18 is connected to EN _ OUT, and the emitter thereof is connected to GND.
Optionally, the first end of the resistor R9 is connected to the base of the transistor Q3, and the second end is connected to the base of the transistor Q14.
Optionally, the first end of the capacitor C1 is connected to the collector of the transistor Q14, and the second end is connected to GND.
Optionally, the positive terminal of the zener diode D1 is connected to GND, and the negative terminal thereof is connected to the base of the transistor Q17.
The invention provides an output detection circuit suitable for a surge suppression chip, which has the following beneficial effects:
1. under the condition of no need of thick gate oxide device, the voltage V of input end VIN is realized by utilizing the voltage difference applied between the emitter and the base of the triodeINAnd an output terminal OUT voltage VOUTDetecting the state, namely judging whether the working state of the circuit is normal or not, and simultaneously introducing a latch comparator structure to improve the detection speed;
2. adding hysteresis effect to the detection result, and filtering V generated by load jumpOUTAnd the instantaneous drop is large, thereby avoiding the malfunction of the subsequent control logic.
Drawings
Fig. 1 is a diagram of a conventional surge suppression chip architecture;
fig. 2 is a schematic diagram of an output detection circuit suitable for a surge suppression chip provided by the invention.
Detailed Description
The following describes an output detection circuit suitable for a surge suppression chip according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides an output detection circuit suitable for a surge suppression chip, which comprises resistors R1-R9, R12-R16, triodes Q1-Q9, Q14-Q18, a capacitor C1, a diode D1 and a latching comparator, wherein the resistors R1-R9, the resistors R12-R16 and the triodes Q1-Q9 are connected with the capacitor C1; the latch comparator comprises triodes Q10-Q13, resistors R10 and R11;
the first end of the resistor R1 is connected with the input end VIN, and the second end is short-circuited with the emitter of the triode Q1; the first end of the resistor R2 is connected with the emitter of the triode Q2, and the second end is connected with the collector of the triode Q3; the first end of the resistor R3 is connected with the emitter of the triode Q3, and the second end is connected with GND; the first end of the resistor R4 is connected with the collector of the triode Q4, and the second end is connected with the emitter of the triode Q5; the first end of the resistor R5 is connected with the collector of the triode Q5, and the second end is connected with the first end of the resistor R6; the first end of the resistor R6 is connected with the base electrode of the triode Q6, and the second end is connected with the collector electrode of the triode Q6; the first end of the resistor R7 is connected with the output end OUT, and the second end is connected with the emitter of the triode Q7; the first end of the resistor R8 is connected with the collector of the triode Q7, and the second end is connected with the collector of the triode Q8; the first end of the resistor R12 is connected with the emitter of the triode Q14, and the second end is connected with GND; the first end of the resistor R13 is connected with the collector of the triode Q14, and the second end is connected with the base of the triode Q16; the first end of the resistor R14 is connected with the first end of the capacitor C1, and the second end is connected with GND; the first end of the resistor R15 is connected with the collector of the triode Q4, and the second end is connected with the collector of the triode Q17; the resistor R16 has a first terminal connected to the base of the transistor Q18 and a second terminal connected to GND. The first end of the resistor R10 is connected with the base electrode of the triode Q11, and the second end is connected with the collector electrode of the triode Q13; the first end of the resistor R11 is connected with the collector of the triode Q11, and the second end is connected with the base of the triode Q13; the collector of the triode Q11 is connected with the collector of the triode Q10, and the collector of the triode Q13 is connected with the collector of the triode Q12; the emitter of the triode Q11 and the emitter of the triode Q13 are both connected with GND. The collector of the triode Q1 is connected with the collector of the triode Q2, the base of the triode Q1 is connected with the collector thereof, and the base of the triode Q2 is connected with the collector thereof; the base of the triode Q4 is connected with the first end of the resistor R4, and the emitter is connected with the output end OUT; the base of the triode Q5 is connected with the first end of the resistor R5; the base electrode of the triode Q6 is connected between the resistor R5 and the resistor R6, and the emitter electrode of the triode Q6 is connected with GND; the base electrode of the triode Q8 is connected with the second end of the resistor R8, and the emitter electrode is connected with GND; the collector of the triode Q9 is connected with the collector of the triode Q11, the base of the triode Q11 is connected with the base of the triode Q8, and the emitter of the triode Q9 is connected with GND; the base of the triode Q7 is connected with the first end of a resistor R2; the base of the triode Q10 is connected with the base of the triode Q5, and the emitter of the triode Q10 is connected with the second end of the resistor R4; the base of the triode Q12 is connected with the base of the triode Q5, and the emitter of the triode Q12 is connected with the second end of the resistor R4; the collector of the triode Q15 is connected with the collector of the triode Q16, the base of the triode Q16 is connected with the base of the triode Q5, and the emitter of the triode Q15 is connected with the second end of the resistor R4; an emitter of the triode Q16 is connected with GND; the base of the triode Q17 is connected with the collector of the triode Q16, and the emitter of the triode Q17 is connected with the first end of the resistor R16; the collector of the transistor Q18 is connected to EN _ OUT, and the emitter thereof is connected to GND. The first end of the resistor R9 is connected with the base electrode of the triode Q3, and the second end is connected with the base electrode of the triode Q14. The first end of the capacitor C1 is connected with the collector of the triode Q14, and the second end is connected with GND. The positive end of the Zener diode D1 is connected with GND, and the negative end of the Zener diode D1 is connected with the base electrode of the triode Q17.
The working principle of the invention is as follows:
1. input VIN voltage VINAnd an output terminal OUT voltage VOUTState detection process analysis
When the OUT voltage V at the output terminalOUT<3|VBEWhen (| V)BEI is an absolute value of a forward conduction voltage difference between a base electrode and an emitter electrode of the transistor, and is typically about 0.7V), and a path between an output end OUT and GND, which is formed by the transistor Q4, the resistor R4, the transistor Q5, the resistor R5, the resistor R6 and the transistor Q6, is not conducted. At the moment, the triode Q3 is turned off, and the base voltage of the triode Q7 is VINAnd V isOUT<VINAnd thus transistor Q7 is off. The latch comparator outputs low level to act on the collector of the triode Q14, the triode Q15 enables the triode Q17 to be turned on, finally the triode Q18 is turned on, and the circuit working state representation signal EN _ OUT (the signal is high normally and low abnormally) is logic low level and represents that the circuit working state is abnormal.
When 3| VBE|<VOUT<VIN-|VBEWhen |
When 3| VBE|<VOUT<VIN-|VBEWhen the current is greater than the predetermined value, | the path between the output terminal OUT and GND, which is composed of the transistor Q4, the resistor R4, the transistor Q5, the resistor R5, the resistor R6, and the transistor Q6, is already turned on. At this time, the transistor Q3 is turned on, and the base voltage of the transistor Q7 is VIN-2|VBEI, but triode Q7 emitter voltage VE(Q7)<VOUT<VIN-|VBEAnd thus transistor Q7 is off. The latch comparator outputs low level to act on the collector of the triode Q14, the triode Q15 enables the triode Q17 to be turned on, finally the triode Q18 is turned on, and the circuit working state representation signal EN _ OUT is logic low level and represents that the circuit working state is abnormal.
When V isIN-|VBE|<VOUT<VINTime of flight
When V isIN-|VBE|<VOUT<VINAt this time, a path between the output terminal OUT and GND, which is formed by the transistor Q4, the resistor R4, the transistor Q5, the resistor R5, the resistor R6, and the transistor Q6, is already turned on. At this time, the transistor Q3 is turned on, and the base voltage of the transistor Q7 is VIN-2|VBEAnd the emitter voltage V of the transistor Q7E(Q7)>VIN-|VBEAnd thus transistor Q7 is on. The latch comparator outputs high level to act on the collector of the triode Q14, the triode Q16 enables the triode Q17 to be closed, finally the triode Q18 is closed, and the circuit working state representation signal EN _ OUT is logic high level and represents that the circuit working state is normal.
2. Hysteresis effect generation analysis
OUT voltage V at output terminalOUTAt low, the transistor Q14 is turned on, and the voltage V at the output end OUT is requiredOUTAnd an input terminal VIN voltage VINThe latch comparator output can only raise the collector of transistor Q14 to turn off transistor Q18 when the voltage difference is small enough, so that the circuit operating state characterization signal EN _ OUT outputs a logic high level, which represents that the circuit operating state is normal.
OUT voltage V at output terminalOUTAt higher, the transistor Q14 is turned off, and the voltage V at the output terminal OUT is requiredOUTAnd inputTerminal VIN voltage VINThe latch comparator output can pull the collector of the transistor Q14 low enough to turn on the transistor Q18, so that the circuit operating state characterization signal EN _ OUT outputs a logic low level, which represents that the circuit operating state is abnormal.
V corresponding to the transistor Q14 when being turned on and turned off can be adjusted by reasonably setting the sizes of the resistor R3 and the resistor R12 and the area ratios of the transistor Q3 and the transistor Q14OUTThreshold value, thereby producing the desired hysteresis size.
In summary, the invention can realize V-pair by using the voltage difference applied between the emitter and the base of the triode without a thick gate oxide deviceINAnd VOUTThe detection of the state can judge whether the working state of the circuit is normal, and simultaneously, a latch comparator structure is introduced to improve the detection speed; the circuit provided by the invention adds a hysteresis effect to the detection result, and filters V generated by load jumpOUTAnd the instantaneous drop is large, thereby avoiding the malfunction of the subsequent control logic.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (1)

1. An output detection circuit suitable for a surge suppression chip is characterized by comprising resistors R1-R9, R12-R16, triodes Q1-Q9, Q14-Q18, a capacitor C1, a diode D1 and a latching comparator;
the first end of the resistor R1 is connected with the input end VIN, and the second end is short-circuited with the emitter of the triode Q1; the first end of the resistor R2 is connected with the emitter of the triode Q2, and the second end is connected with the collector of the triode Q3; the first end of the resistor R3 is connected with the emitter of the triode Q3, and the second end is connected with GND;
the first end of the resistor R4 is connected with the collector of the triode Q4, and the second end is connected with the emitter of the triode Q5; the first end of the resistor R5 is connected with the collector of the triode Q5, and the second end is connected with the first end of the resistor R6; the first end of the resistor R6 is connected with the base electrode of the triode Q6, and the second end is connected with the collector electrode of the triode Q6;
the first end of the resistor R7 is connected with the output end OUT, and the second end is connected with the emitter of the triode Q7; the first end of the resistor R8 is connected with the collector of the triode Q7, and the second end is connected with the collector of the triode Q8;
the first end of the resistor R12 is connected with the emitter of the triode Q14, and the second end is connected with GND; the first end of the resistor R13 is connected with the collector of the triode Q14, and the second end is connected with the base of the triode Q16; the first end of the resistor R14 is connected with the first end of the capacitor C1, and the second end is connected with GND; the first end of the resistor R15 is connected with the collector of the triode Q4, and the second end is connected with the collector of the triode Q17; the first end of the resistor R16 is connected with the base electrode of the triode Q18, and the second end is connected with GND;
the latching comparator comprises triodes Q10-Q13 and resistors R10 and R11; the first end of the resistor R10 is connected with the base electrode of the triode Q11, and the second end is connected with the collector electrode of the triode Q13;
the first end of the resistor R11 is connected with the collector of the triode Q11, and the second end is connected with the base of the triode Q13;
the collector of the triode Q11 is connected with the collector of the triode Q10, and the collector of the triode Q13 is connected with the collector of the triode Q12;
an emitter of the triode Q11 and an emitter of the triode Q13 are both connected with GND;
the collector of the triode Q1 is connected with the collector of the triode Q2, the base of the triode Q1 is connected with the collector thereof, and the base of the triode Q2 is connected with the collector thereof; the base of the triode Q4 is connected with the first end of the resistor R4, and the emitter is connected with the output end OUT; the base of the triode Q5 is connected with the first end of the resistor R5; the base electrode of the triode Q6 is connected between the resistor R5 and the resistor R6, and the emitter electrode of the triode Q6 is connected with GND; the base electrode of the triode Q8 is connected with the second end of the resistor R8, and the emitter electrode is connected with GND; the collector of the triode Q9 is connected with the collector of the triode Q11, the base of the triode Q11 is connected with the base of the triode Q8, and the emitter of the triode Q9 is connected with GND; the base of the triode Q7 is connected with the first end of a resistor R2;
the base of the triode Q10 is connected with the base of the triode Q5, and the emitter of the triode Q10 is connected with the second end of the resistor R4; the base of the triode Q12 is connected with the base of the triode Q5, and the emitter of the triode Q12 is connected with the second end of the resistor R4;
the collector of the triode Q15 is connected with the collector of the triode Q16, the base of the triode Q16 is connected with the base of the triode Q5, and the emitter of the triode Q15 is connected with the second end of the resistor R4; an emitter of the triode Q16 is connected with GND; the base of the triode Q17 is connected with the collector of the triode Q16, and the emitter of the triode Q17 is connected with the first end of the resistor R16; the collector of the triode Q18 is connected with EN _ OUT, and the emitter of the triode Q18 is connected with GND;
the first end of the resistor R9 is connected with the base electrode of a triode Q3, and the second end is connected with the base electrode of a triode Q14;
the first end of the capacitor C1 is connected with the collector of the triode Q14, and the second end is connected with GND;
the positive end of the diode D1 is connected with GND, and the negative end thereof is connected with the base of the triode Q17.
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