CN218514083U - IO port protection circuit - Google Patents
IO port protection circuit Download PDFInfo
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- CN218514083U CN218514083U CN202222434223.1U CN202222434223U CN218514083U CN 218514083 U CN218514083 U CN 218514083U CN 202222434223 U CN202222434223 U CN 202222434223U CN 218514083 U CN218514083 U CN 218514083U
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Abstract
The utility model relates to a power electronic technology field relates to an IO mouth protection circuit, wherein, IO mouth protection circuit, include: the voltage detection circuit is used for detecting the voltage at the external IO port in real time and feeding the voltage back to the switch control circuit; and the switch control circuit is used for controlling the controllable switch to be switched off when the voltage at the external IO port is abnormal.
Description
Technical Field
The disclosure relates to the technical field of power electronics, in particular to an IO port protection circuit.
Background
In unmanned aerial vehicle avionics system, can contain higher voltage usually, for example the power battery voltage that present unmanned aerial vehicle used can reach 60V or even higher, this just leads to in case the signal IO mouth that flies to control and battery positive pole short circuit then can burn out, perhaps the back electromotive force voltage that the water pump that uses on the plant protection unmanned aerial vehicle produced is also very high, in case insert fly to control IO mouth also can burn out it, so it is necessary to protect the IO mouth that flies to control. The existing protection circuit may have one or more of the following disadvantages: (1) When the abnormal voltage is very high, the protection circuit generally occupies a larger circuit board area; (2) In a normal working state, a large power loss or a large and uncertain voltage drop is generated in the protection circuit, for example, when a diode is used as a key device in the protection circuit, a large voltage drop and power loss are generated, and even the circuit works abnormally; (3) Some devices in the protection circuit can be damaged when operated for a long time, for example, the transient suppression diode can be operated in a conducting state for a long time to cause that the dissipated power exceeds the standard so that a tube is burnt out.
SUMMERY OF THE UTILITY MODEL
The present disclosure provides an IO port protection circuit.
According to an aspect of the present disclosure, there is provided an IO port protection circuit including: the input end and the output end of the controllable switch are respectively connected with the internal IO port and the external IO port, the input end of the voltage detection circuit is connected with the external IO port, the output end of the voltage detection circuit is connected with the input end of the controllable switch through the switch control circuit,
the voltage detection circuit is used for detecting the voltage at the external IO port in real time and feeding the voltage back to the switch control circuit;
and the switch control circuit is used for controlling the controllable switch to be switched off when the voltage at the external IO port is abnormal.
Preferably, the voltage detection circuit includes: the first voltage-dividing resistor, the second voltage-dividing resistor and the third voltage-dividing resistor are sequentially connected in series;
the input end of the third voltage-dividing resistor is connected with the external IO port, the output end of the first voltage-dividing resistor is grounded, and the output end of the second voltage-dividing resistor is connected with the switch control circuit;
the switch control circuit is used for controlling the controllable switch to be switched off when the voltage at the output end of the second voltage-dividing resistor is abnormal.
Preferably, the switch control circuit includes: the first pull-up resistor, the two capacitors connected in parallel and the first triode;
the input end of the first pull-up resistor is connected with a power supply, the output end of the first pull-up resistor is respectively connected with the input ends of the two capacitors connected in parallel and the input end of the controllable switch, and the output ends of the two capacitors connected in parallel are grounded;
the base electrode of the first triode is connected with the output end of the voltage detection circuit, the collector electrode of the first triode is connected with the input end of the controllable switch, and the emitting electrode of the first triode is grounded;
and the first triode is used for controlling the controllable switch to be switched off when the voltage at the external IO port is abnormal.
Preferably, the switch control circuit includes: the second pull-up resistor, the third pull-up resistor, the second triode and the third triode;
the input end of the second pull-up resistor is connected with a power supply, the output end of the second pull-up resistor and the collector of the second triode are respectively connected with the input end of the controllable switch, the emitter of the second triode is grounded, and the base of the second triode is connected with the output end of the third pull-up resistor;
the input end of the third pull-up resistor is connected with a power supply, the base of the second triode is also connected with the collector of the third triode, the emitter of the third triode is grounded, and the base of the third triode is connected with the output end of the voltage detection circuit.
Preferably, the controllable switch is a field effect transistor, a gate of the field effect transistor is connected to an output terminal of the switch control circuit, a source of the controllable switch is connected to the internal IO port, and a drain of the controllable switch is connected to the external IO port.
Preferably, the controllable switch is a solid-state relay, a first control end and a second control end of the solid-state relay are respectively connected with the internal IO port and the external IO port, and an input end of the solid-state relay is connected with the switch control circuit.
Preferably, the method further comprises the following steps: the two ends of the protection circuit are respectively connected with the internal IO port and the controllable switch;
and the protection circuit is used for reducing the instantaneous voltage at the internal IO port when the voltage at the external IO port is abnormal.
Preferably, the protection circuit includes: a transient diode and a current limiting resistor;
the internal IO port is connected with the input end of the current-limiting resistor, and the output end of the current-limiting resistor is respectively connected with the transient diode and the controllable switch;
the transient diode is used for clamping the transient voltage at the internal IO port to a preset voltage when the voltage at the external IO port is abnormal.
In the embodiment of the disclosure, the problems that the existing protection circuit occupies a larger circuit board area and has large power loss are solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic diagram illustrating constituent modules of an IO port protection circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating constituent modules of another IO port protection circuit provided in an embodiment of the present disclosure;
fig. 3 illustrates a schematic diagram of an IO port protection circuit provided in an embodiment of the present disclosure;
fig. 4 shows a schematic diagram of another IO port protection circuit provided in an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the subject matter of the present disclosure.
It is understood that the above-mentioned method embodiments of the present disclosure can be combined with each other to form a combined embodiment without departing from the logic of the principle, which is limited by the space, and the detailed description of the present disclosure is omitted.
Fig. 1 illustrates an IO port protection circuit provided in an embodiment of the present disclosure, and as shown in fig. 1, the IO port protection circuit includes: the voltage detection circuit is used for detecting the voltage at the external IO port in real time and feeding the voltage back to the switch control circuit; and the switch control circuit is used for controlling the controllable switch to be switched off when the voltage at the external IO port is abnormal. Compared with the circuit board area occupied by the protection circuit in the prior art, the IO port protection circuit provided by the embodiment of the disclosure has the advantages of smaller power consumption.
Specifically, IN fig. 1, IO _ IN is an IO port protected IN a circuit board or a module, IO _ EXT is an external access IO port, a signal is transmitted to IO _ EXT (an external IO port) through IO _ IN (an internal IO port), when a voltage at IO _ EXT exceeds a preset voltage, it is determined that the voltage at IO _ EXT (an external IO port) is abnormal, a switch control circuit is driven, and then the controllable switch is controlled to be turned off, so that the IO _ IN (an internal IO port) and the IO _ EXT (an external IO port) are turned off, and therefore external abnormal voltage and current can be prevented from flowing backwards into the circuit board or the module.
In an embodiment of the present disclosure and other possible embodiments, as shown in fig. 2, the circuit further includes: the two ends of the protection circuit are respectively connected with the internal IO port and the controllable switch; and the protection circuit is used for reducing the instantaneous voltage at the internal IO port when the voltage at the external IO port is abnormal. Since both the switch control circuit and the controllable switch require a certain response time, the protection circuit provides a momentary protection when the controllable switch is not fully opened.
In an embodiment of the present disclosure and other possible embodiments, the voltage detection circuit includes: the first voltage-dividing resistor, the second voltage-dividing resistor and the third voltage-dividing resistor are sequentially connected in series; the input end of the third voltage-dividing resistor is connected with the external IO port, the output end of the first voltage-dividing resistor is grounded, and the output end of the second voltage-dividing resistor is connected with the switch control circuit; the switch control circuit is used for controlling the controllable switch to be switched off when the voltage at the output end of the second voltage-dividing resistor is abnormal.
Specifically, as shown in fig. 3, the first voltage dividing resistor, the second voltage dividing resistor and the third voltage dividing resistor are resistors R4, R5 and R8, the resistors R4, R5 and R8 constitute a voltage divider, the voltage dividing ratio can be determined by adjusting the resistance values of the resistors R4, R5 and R8, the voltage detection circuit can detect the voltage at IO _ EXT (external IO port) in real time through the resistors R4, R5 and R8, when no abnormal voltage appears, the voltage at the point a in fig. 3 changes with the voltage change at IO _ EXT (external IO port), that is, when the voltage at IO _ EXT (external IO port) increases, the voltage at the point a also increases.
In an embodiment of the disclosure, among other possible embodiments, the switch control circuit includes: the first pull-up resistor, the two capacitors connected in parallel and the first triode; the input end of the first pull-up resistor is connected with a power supply, the output end of the first pull-up resistor is respectively connected with the input ends of the two capacitors connected in parallel and the input end of the controllable switch, and the output ends of the two capacitors connected in parallel are grounded; the base electrode of the first triode is connected with the output end of the voltage detection circuit, the collector electrode of the first triode is connected with the input end of the controllable switch, and the emitting electrode of the first triode is grounded; and the first triode is used for controlling the controllable switch to be switched off when the voltage at the external IO port is abnormal.
Specifically, as shown in fig. 3, the first pull-up resistor is R3, the two capacitors connected in parallel are C1 and C2, respectively, the first triode is Q2, the voltage between the base (B pole) and the emitter (E pole) of the first triode Q2 controls the on/off of the first triode Q2, and when the voltage between the base (B pole) and the emitter (E pole) is higher than the conduction threshold, usually 0.7V, the collector (C pole) and the emitter (E pole) of the first triode Q2 will be conducted, otherwise they will not be conducted.
Further, the voltage at the base (B pole) of the first triode Q2 is equivalent to the voltage at the a point, when there is no abnormal voltage at IO _ EXT (external IO port), the voltage between the base (B pole) and the emitter (E pole) is lower than the conduction threshold, the first triode Q2 is not conductive, the controllable switch is not off, and a signal can be normally communicated between IO _ IN (internal IO port) and IO _ EXT (external IO port); when the voltage at an external IO port (IO _ EXT) suddenly rises and abnormal voltage exists, the voltage at the base (B pole) of the first triode Q2 rises, so that the voltage between the base (B pole) and the emitter (E pole) is higher than the conduction threshold voltage of the first triode Q2, and the collector (C pole) and the emitter (E pole) of the first triode Q2 are conducted, at the moment, the emitter (E pole) of the first triode Q2 is connected with 0 potential, the supply voltage of the controllable switch is small, and the controllable switch is disconnected. Therefore, the abnormal voltage at IO _ EXT (external IO port) cannot flow to IO _ IN (internal IO port), that is, cannot flow into the circuit board or the module, thereby protecting the core device from being damaged.
In the embodiments of the present disclosure and other possible embodiments, the controllable switch is a field effect transistor, a gate of the field effect transistor is connected to the output terminal of the switch control circuit, a source of the controllable switch is connected to the internal IO port, and a drain of the controllable switch is connected to the external IO port. The field effect transistor may be an N-channel MOSFET.
Specifically, as shown IN fig. 3, when there is no abnormal voltage at IO _ EXT (external IO port), the collector (C pole) and the emitter (E pole) of the first transistor Q2 are not conducted, the gate (G pole) of the controllable switch Q1 is pulled up to the voltage VCC by the first pull-up resistor R3, the voltage between the gate (G pole) and the source (S pole) of the controllable switch Q1 is higher than the conducting voltage of the controllable switch Q1, which causes the source (S pole) and the drain (D pole) of the controllable switch Q1 to be conducted, i.e., the controllable switch Q1 is not disconnected, so that a normal communication signal can be conducted between IO _ IN (internal IO port) and IO _ EXT (external IO port); when abnormal voltage exists at an IO _ EXT (external IO port), a collector (C pole) and an emitter (E pole) of the first triode Q2 are conducted, the emitter (E pole) of the first triode Q2 is connected with a 0-point, the potential of a grid (G pole) of the controllable switch Q1 is about 0.2V, the voltage between the grid (G pole) of the controllable switch Q1 and a source (S pole) of the controllable switch Q1 cannot be higher than the conducting voltage of the controllable switch Q1, then the source (S pole) and a drain (D pole) of the controllable switch Q1 are disconnected, the abnormal voltage at the IO _ EXT cannot flow to the IO _ IN, namely cannot flow into the circuit board or the module, and the core device is protected from being damaged.
In this disclosure and other possible embodiments, the protection circuit includes: a transient diode and a current limiting resistor; the internal IO port is connected with the input end of the current-limiting resistor, and the output end of the current-limiting resistor is respectively connected with the transient diode and the controllable switch; and when the voltage at the external IO port is abnormal, a user clamps the instantaneous voltage at the internal IO port to a preset voltage by the transient diode.
Specifically, as shown in fig. 3, the output end of the current limiting resistor R1 is connected to the source (S pole) of the controllable switch Q1, and when abnormal voltage occurs in IO _ EXT (external IO port), and the source (S pole) and the drain (D pole) of the controllable switch Q1 are not completely turned off, the transient diode TVS1 clamps the abnormal voltage to a certain low potential, and then limits current through the current limiting resistor R1, so as to limit abnormal energy from reaching the circuit board or the module, thereby preventing the core device from being damaged.
In this disclosure, in other possible embodiments, the controllable switch may further be a solid-state relay, a first control end and a second control end of the solid-state relay are respectively connected to the internal IO port and the external IO port, and an input end of the solid-state relay is connected to the switch control circuit.
Specifically, as shown IN fig. 4, the first control terminal 6 of the solid-state relay U1B is connected to IO _ IN (internal IO port) through a protection circuit, the second control terminal 5 is connected to IO _ EXT (external IO port), and when there is no abnormal voltage IN IO _ EXT (external IO port), the switch control circuit adds an external voltage to the two input terminals 3 and 4 of the solid-state relay U1B, so that the first control terminal 6 and the second control terminal 5 of the solid-state relay U1B are turned on; on the contrary, when IO _ EXT (external IO port) has an abnormal voltage, the switch control circuit does not add an external voltage to the input terminals 3 and 4, so that the first control terminal 6 and the second control terminal 5 of the solid-state relay U1B are disconnected, and it is ensured that the abnormal voltage at IO _ EXT cannot flow to IO _ IN, that is, cannot flow into the circuit board or the module.
In this disclosure, in other possible embodiments, the switch control circuit may further include: the second pull-up resistor, the third pull-up resistor, the second triode and the third triode are connected in series; the input end of the second pull-up resistor is connected with a power supply, the output end of the second pull-up resistor and the collector of the second triode are respectively connected with the input end of the controllable switch, the emitter of the second triode is grounded, and the base of the second triode is connected with the output end of the third pull-up resistor; the input end of the third pull-up resistor is connected with a power supply, the base of the second triode is also connected with the collector of the third triode, the emitter of the third triode is grounded, and the base of the third triode is connected with the output end of the voltage detection circuit.
It should be noted that, in the embodiment of the present invention, only the components of the controllable switch (the field effect transistor is replaced by the relay) and the switch control circuit are changed, and the components and connection modes of the protection circuit and the voltage detection circuit are the same as those described in the previous embodiment.
Specifically, as shown in fig. 4, the output end of the second pull-up resistor R15 is connected to the input end 3 of the solid-state relay U1B, the collector C of the second transistor Q6 is connected to the input end 4 of the solid-state relay U1B, the base B of the second transistor Q6 is connected to the collector C of the third transistor Q8 and the output end of the third pull-up resistor R17, respectively, and the base of the third transistor Q8 is connected to the output end of the voltage dividing resistor R20 in the voltage detection circuit.
As shown IN fig. 4, when there is no abnormal voltage at IO _ EXT (external IO port), the voltage between the base B and the emitter E of the third transistor Q8 is lower than the conduction threshold voltage of the third transistor Q8, so that the collector C and the emitter E of the third transistor Q8 are not conducted, the base B of the second transistor Q6 is pulled up to the voltage VCC by the third pull-up resistor R17, and at this time, the voltage between the base B and the emitter E of the second transistor Q6 is higher than the conduction threshold voltage of the second transistor Q6, so that the collector C and the emitter E of the second transistor Q6 are conducted, and since the emitter E of the second transistor Q6 is grounded, it can be ensured that there are external voltages at the two input terminals of the solid state relay U1B, so that the first control terminal 6 and the second control terminal 5 of the solid state relay U1B are conducted, i.e., it can be ensured that a normal communication signal can be communicated between IO _ IN (internal IO port) and IO _ EXT (external IO port).
On the contrary, when an abnormal voltage exists IN the IO _ EXT (external IO port), the voltage between the base B and the emitter E of the third triode Q8 is higher than the conduction threshold voltage of the third triode Q8, so that the collector C and the emitter E of the third triode Q8 are conducted, the emitter E of the third triode Q8 is grounded, and the voltage of the base B of the second triode Q6 is smaller, and at this time, the voltage between the base B and the emitter E of the second triode Q6 is lower than the conduction threshold voltage of the second triode Q6, so that the collector C and the emitter E of the second triode Q6 are not conducted, and no external voltage exists at the two input ends of the solid-state relay U1B, and therefore, the first control end 6 and the second control end 5 of the solid-state relay U1B are not conducted, and it is ensured that the abnormal voltage at the IO _ EXT cannot flow to the IO _ IN, that is, i.e., cannot flow into the circuit board or the module.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (8)
1. An IO port protection circuit, comprising: the input end and the output end of the controllable switch are respectively connected with the internal IO port and the external IO port, the input end of the voltage detection circuit is connected with the external IO port, the output end of the voltage detection circuit is connected with the input end of the controllable switch through the switch control circuit,
the voltage detection circuit is used for detecting the voltage at the external IO port in real time and feeding the voltage back to the switch control circuit;
and the switch control circuit is used for controlling the controllable switch to be switched off when the voltage at the external IO port is abnormal.
2. The circuit of claim 1, wherein the voltage detection circuit comprises: the first voltage-dividing resistor, the second voltage-dividing resistor and the third voltage-dividing resistor are sequentially connected in series;
the input end of the third voltage-dividing resistor is connected with the external IO port, the output end of the first voltage-dividing resistor is grounded, and the output end of the second voltage-dividing resistor is connected with the switch control circuit;
the switch control circuit is used for controlling the controllable switch to be switched off when the voltage at the output end of the second voltage-dividing resistor is abnormal.
3. The circuit of claim 1, wherein the switch control circuit comprises: the first pull-up resistor, the two capacitors connected in parallel and the first triode;
the input end of the first pull-up resistor is connected with a power supply, the output end of the first pull-up resistor is respectively connected with the input ends of the two capacitors connected in parallel and the input end of the controllable switch, and the output ends of the two capacitors connected in parallel are grounded;
the base electrode of the first triode is connected with the output end of the voltage detection circuit, the collector electrode of the first triode is connected with the input end of the controllable switch, and the emitting electrode of the first triode is grounded;
and the first triode is used for controlling the controllable switch to be switched off when the voltage at the external IO port is abnormal.
4. The circuit of claim 1, wherein the switch control circuit comprises: the second pull-up resistor, the third pull-up resistor, the second triode and the third triode;
the input end of the second pull-up resistor is connected with a power supply, the output end of the second pull-up resistor and the collector of the second triode are respectively connected with the input end of the controllable switch, the emitter of the second triode is grounded, and the base of the second triode is connected with the output end of the third pull-up resistor;
the input end of the third pull-up resistor is connected with a power supply, the base of the second triode is also connected with the collector of the third triode, the emitter of the third triode is grounded, and the base of the third triode is connected with the output end of the voltage detection circuit.
5. The circuit of claim 1, wherein the controllable switch is a field effect transistor, a gate of the field effect transistor is connected to the output of the switch control circuit, a source of the controllable switch is connected to the internal IO port, and a drain of the controllable switch is connected to the external IO port.
6. The circuit of claim 1, wherein the controllable switch is a solid-state relay, a first control terminal and a second control terminal of the solid-state relay are respectively connected to the internal IO port and the external IO port, and an input terminal of the solid-state relay is connected to the switch control circuit.
7. The circuit of any one of claims 1-6, further comprising: the two ends of the protection circuit are respectively connected with the internal IO port and the controllable switch;
and the protection circuit is used for reducing the instantaneous voltage at the internal IO port when the voltage at the external IO port is abnormal.
8. The circuit of claim 7, wherein the protection circuit comprises: a transient diode and a current limiting resistor;
the internal IO port is connected with the input end of the current-limiting resistor, and the output end of the current-limiting resistor is respectively connected with the transient diode and the controllable switch;
the transient diode is used for clamping the transient voltage at the internal IO port to a preset voltage when the voltage at the external IO port is abnormal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222434223.1U CN218514083U (en) | 2022-09-14 | 2022-09-14 | IO port protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222434223.1U CN218514083U (en) | 2022-09-14 | 2022-09-14 | IO port protection circuit |
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| Publication Number | Publication Date |
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| CN218514083U true CN218514083U (en) | 2023-02-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222434223.1U Active CN218514083U (en) | 2022-09-14 | 2022-09-14 | IO port protection circuit |
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| CN (1) | CN218514083U (en) |
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